Improving vertical GaN p–n diode performance with room temperature defect mitigation

Defect mitigation of electronic devices is conventionally achieved using thermal annealing. To mobilize the defects, very high temperatures are necessary. Since thermal diffusion is random in nature, the process may take a prolonged period of time. In contrast, we demonstrate a room temperature annealing technique that takes only a few seconds. The fundamental mechanism is defect mobilization by atomic scale mechanical force originating from very high current density but low duty cycle electrical pulses. The high-energy electrons lose their momentum upon collision with the defects, yet the low duty cycle suppresses any heat accumulation to keep the temperature ambient. For a 7 × 105 A cm−2 pulsed current, we report an approximately 26% reduction in specific on-resistance, a 50% increase of the rectification ratio with a lower ideality factor, and reverse leakage current for as-fabricated vertical geometry GaN p–n diodes. We characterize the microscopic defect density of the devices before and after the room temperature processing to explain the improvement in the electrical characteristics. Raman analysis reveals an improvement in the crystallinity of the GaN layer and an approximately 40% relaxation of any post-fabrication residual strain compared to the as-received sample. Cross-sectional transmission electron microscopy (TEM) images and geometric phase analysis results of high-resolution TEM images further confirm the effectiveness of the proposed room temperature annealing technique to mitigate defects in the device. No detrimental effect, such as diffusion and/or segregation of elements, is observed as a result of applying a high-density pulsed current, as confirmed by energy dispersive x-ray spectroscopy mapping.


Introduction
Gallium nitride (GaN) is one of the most promising wide bandgap semiconductor materials for the next generation of power electronics [1,2].The combination of superior semiconductor characteristics, such as a large bandgap, high electric breakdown field, good thermal and chemical stability, and better figure of merit have made it a suitable candidate for high-power and high-frequency applications [3][4][5].Currently, mainstream industry ′ s focus for GaN power devices is on the lateral structure due to the high mobility offered by the intrinsic two-dimensional electron gas [6,7].However, lateral devices require a higher footprint to achieve high breakdown voltage, suffer from low heat dissipation capacity, and exhibit parasitic conduction under high voltages [3,8].As a result, lateral devices are limited to low-to medium-voltage applications (less than 1 kV).On the other hand, vertical geometry devices offer several advantages over lateral devices, such as better scaling factors and thermal management, a higher critical electric field and breakdown voltage, and better radiation tolerance [9,10].Several studies have reported the attractive performance of vertical GaN-on-GaN p-n diodes, which have a high breakdown voltage (4-6 kV) [11][12][13] and low specific on-resistance (less than 0.5 mΩ cm 2 ) [10,14].
Vertical GaN-based p-n diodes and Schottky diodes are attractive alternatives to their Si-based counterparts due to their low noise, loss, and junction capacitance [15,16].The performance and reliability of vertical devices significantly depend on the device structure, defect density, and doping concentration.The availability of bulk GaN substrates and the homoepitaxial growth of GaN-on-GaN yield a few orders of magnitude lower threading dislocations and defects density compared to GaN on foreign substrates [17].However, the consistency and uniformity of GaN wafers are still challenging, which can significantly impact the homoepitaxial growth of GaN devices.Additional defects can be incorporated into the device during ion implantation, a widely used process in semiconductor device fabrication for doping and edge termination [18,19].It is necessary to recover the defects generated by high-energy ion bombardment during doping in order to prevent premature breakdown and performance degradation of the device.Doping of p-type GaN is a complex process.Activation of implanted p-type dopants, such as Mg in GaN, requires high-temperature (>1300 • C) annealing.Techniques such as multicycle rapid thermal annealing (MRTA), symmetrical MRTA, and ultrahigh-pressure annealing have been demonstrated in the literature to achieve efficient activation of dopants and restore the ion-implantationinduced crystal damage [20][21][22].However, these processes involve multiple rapid heating and cooling cycles at high pressure in addition to conventional annealing and often require cap layers to prevent nitrogen loss in the GaN surface [23,24].
In this research, we use low-temperature processing of an as-implanted p-type GaN layer of a vertical p-n diode and high-density current pulses for a short period of time to mitigate the ion-implantation defects of the device.When the current is injected into the device, we consider electron-lattice and electron-defect interactions to describe the proposed annealing process.Electron-lattice scattering is a low-momentum process that generates joule heat.If the heat is allowed to accumulate, it creates more defects through thermomechanical stress, eventually causing thermal runaway in the device.Electron-defect interaction, on the other hand, is a higher momentum process, where electron energy is imparted to the defects, mobilizing and eventually eliminating them.A unique aspect of our proposed technique is the near room temperature defect mitigation using a very small duty cycle pulsed current to circumvent the effect of joule heating associated with the high-density current.We exploit the effectiveness of high-density pulsed current-induced electron wind force (EWF) to improve the crystal quality and electrical transport properties of the as-received device.The detailed fundamental mechanism behind EWF annealing is given in [25].Previously, high-density current-induced EWF has been reported to be effective to improve crystallinity and performance of GaN high-electron mobility transistors [26], 2D materials [27] and devices [28], metal thin film [29], and bulk alloys [30,31].This low-temperature defect mitigation technique could be a potential efficient alternative to high-temperature annealing of electronic devices by reducing the time, energy, and process complexity.

Experimental procedures
The specimens used in this study are vertical PiN diodes, fabricated by a metal organic chemical vapor deposition process using a Taiyo Nippon Sanso SR4000HT reactor.On an unintentionally doped n-type GaN substrate, a Si-doped (n ≈ 2 × 10 16 cm −3 ) 8 µm n-type drift layer was grown, followed by a 500 nm Mg-doped (n ≈ 1 × 10 18 cm −3 ) p-type layer.The square grid diodes were fabricated with a Pd/Pt/Au anode metal, a Ti/Al/Ni/Au backside contact, a Cl 2 plasma etch trench isolation, a ∼600 nm deep implant isolation trench, and a ∼300 nm deep single zone junction termination extension edge termination trench, all by nitrogen implant.The asimplanted diode structures were processed at low temperatures below 300 • C without a high-temperature annealing step, which gave ∼6.3% activation of Mg with a hole concentration of 6.3 × 10 16 cm −3 .More details on the fabrication and characterization are given in [9].
Room temperature pulsed current annealing was performed using a high current pulse generator.A pulsed current of up to 7 × 10 5 A cm −2 density was applied to the device for 1 min with a 20 µs pulse width and 2 Hz frequency, giving a duty cycle of 4%, as shown in figure 1(b).Such a small duty cycle impedes the generation of large joule heating despite the very high current density.The real-time temperature during the process was monitored using an Optris PI-640 thermal microscope.The maximum temperature rise during the pulsed current annealing was found to be 28.8 • C (shown in figure 1(c)).
Electrical characterizations of the devices were performed with a Keithley 2636B source measuring unit.The forward I-V characteristics were recorded from 0 to 5 V.The reverse leakage current measurements were taken from 0 to −200 V.The crystal quality and residual stress of the GaN layer before and after pulsed current annealing were studied using a highresolution micro-Raman technique.Before taking Raman measurements, the metal electrodes were etched away using an aqua regia solution.High-resolution Raman spectra were recorded with a Horiba LabRAM HR Evolution coupled with a 100X, NA = 0.9 microscope objective using a 532 nm green laser and 1800 gm mm −1 grating.Cross sections of the device were investigated under an FEI Talos F200X transmission electron microscope (TEM) with a scanning (STEM) system equipped with an energy dispersive x-ray spectroscopy (EDX) detector.The electron transparent samples for the TEM study were prepared by an in-situ lift-out method using an FEI Scios-2 DualBeam focused ion beam system.

Results and discussion
The forward I-V characteristics of the as-received and pulsed current annealed GaN p-n diodes are shown in figure 2(a).All of the devices demonstrate good rectifying behavior.The turnon voltage was extracted from the linear extrapolation of the I-V curve.The high-density pulsed current annealing process does not seem to impact the turn-on voltage of the devices.The turn-on voltage of all devices is found to be ∼3.1 V, which is expected for GaN-based devices [32].It is important to note that the turn-on voltage of the p-n diode depends on the device structure, the quality of the ohmic contacts, the contact geometry, the doping concentration, and the built-in voltage of the p-n junction [33,34].During the pulsed current annealing process, all of these factors mostly remain unaltered, resulting in a constant turn-on voltage of the diodes.The reverse I-V characteristics of the devices up to a −200 V anode current are shown in figure 2(b).With the increase of current density, the maximum leakage current (at −200 V) decreases slightly compared to the as-received device.The slight improvement of the leakage current might be attributed to the mitigation of crystal defects near the anode and GaN interface, an improvement of the anode ohmic contact.However, the constant turnon voltage of the devices indicates no change in ohmic contact quality.In addition, during the pulsed current annealing, the sample temperature remains at room temperature and does not have enough energy to increase the activation of Mg ions.Therefore, the lower leakage current is the result of the reduced defect density at the interface.A slight jump of leakage current is observed at a current density of 7 × 10 5 A cm −2 , which could be due to the initiation of new defects at high current density.This factor limits the selection of the maximum current density of the pulsed current used for annealing.
The specific on-resistance (R on ) and ideality factor have been extracted from the forward I-V curves and are presented in figure 2(c).The R on value of the diode is found to decrease with the increase in current density.An approximately 26% reduction in specific on-resistance has been observed after treatment with 7 × 10 5 A cm −2 current density compared to the as-received device.The ideality factor of the as-received device is calculated to be 2.65, which suggests that the transport mechanism of the device is dominated by the recombination and generation process.The deviation of the ideality factor from its theoretical value of 2 indicates the presence of crystal defects in the epitaxial layers of the device.A small decrease in the ideality factor of pulsed current annealed devices is observed.The rectification ratio, defined by I max, forward /I max, reverse at ±5 V, of the devices also increases after the pulsed current annealing process, as shown in figure 2(d).The rectification ratio increases by more than 50% after treatment with a 7 × 10 5 A cm −2 pulsed current compared to the as-received device.The enhanced transport properties of the pulsed current annealed GaN p-n diode might be attributed to the improved crystal quality of the GaN and the lower defect density at the epitaxial interfaces.
Micro-Raman spectroscopy was performed on the asreceived and 7 × 10 5 A cm −2 pulsed current density annealed samples in order to investigate the crystal quality and residual stress of the GaN.The E 2 (high) and A 1 (LO) Raman peaks of the GaN layer before and after pulsed current annealing are shown in figures 3(a) and (b), respectively.The peak positions and full width at half maximum (FWHM) values were extracted after fitting the peaks using the pseudo-Voigt  model.The FWHM values of E 2 (high) and A 1 (LO) peaks of the GaN layer of the as-received sample are found to be 2.24 and 6.32 cm −1 , respectively.After pulsed current annealing, the FWHM values of E 2 (high) and A 1 (LO) peaks decrease to 2.22 and 6.13 cm −1 , respectively.The relatively narrower FWHM of the E 2 (high) and A 1 (LO) peaks for the pulsed current annealed device compared to the as-received counterpart represents better crystal quality of the former [35].The residual stress in the GaN layer has also been estimated by comparing the E 2 (high) peak position to the stress-free GaN E 2 (high) peak (567 cm −1 ) [18,35,36].The GaN layer of the as-received device was under compression.The estimated stress value of the GaN for the as-received sample is 44.11MPa, whereas the corresponding value for The GaN layer of the as-received device exhibits crystalline defects at both interface regions and away from the interface.The GaN layer of the pulsed current annealed sample appears to contain fewer defects, especially away from the interface.The high-density current pulse was applied in the direction of the anode to the cathode of the device, which suggests that the direction of the EWF is from the cathode to the anode.As a result, the defects deep in the GaN layer diffuse toward the interface under the influence of strong EWF.
For better elucidation of regions of localized defects and lattice strain, geometric phase analysis (GPA) has been performed on the HRTEM images, and the corresponding atomic strain mapping (ε xx ) results are shown in figures 5(e)-(h).The deposition process and ion-implantation-induced localized defects could include point defects such as vacancies and interstitials, 1D defects such as dislocations, and 2D defects such as stacking faults and twinning.The generated dislocations in the GaN layer are mostly threading dislocations of three kinds: edge, screw, and mixed type [37].The GPA provides the strain field of dislocations around the dislocation cores.The edge type dislocation results in tension and compression strain pairs [38,39], which can be identified by the blue and red dipole marks on the GPA strain maps.The screw dislocations are usually identified by the twisted or rotational displacement field, which corresponds to a circular or helical pattern around the dislocation core on the GPA strain map.The atomic strain maps of the as-received sample (figures 5(e) and (f)) show higher edge-type threading dislocations near the interface (figure 5(e)), which are significantly annealed after pulsed current treatment (figure 5(g)).The annihilation of edge dislocations after pulsed current annealing is more prominent away from the interface (figure 5(h)).The reduction of screw dislocations is also noticeable after pulsed current annealing.The dislocation densities in the GaN were estimated using ImageJ software, which are found to be 9.21 × 10 11 cm −2 and 3.04 × 10 11 cm −2 for the as-received and pulsed current annealed GaN layers, respectively.The pulsed current annealing appears to be less effective near the Pd/p-GaN interface  due to weak current spreading, which results in weaker EWF in the p-GaN compared to the n-GaN.
The presence of dislocations incorporates compressive and tensile stresses around the dislocation core, producing local strain heterogeneity in the crystal lattice.Therefore, the lower dislocation density of the pulsed current annealed sample indicates relaxation of localized lattice strain in the GaN layer, which is also consistent with the obtained Raman results.The dislocations act as precursors of electronic defects such as traps and nonradiative recombination and scattering centers, which deteriorate the electrical and optical performances of GaN-based devices [40,41].The reduction of dislocation density inhibits the carriers to recombine nonradiatively, increasing their lifetimes [41,42], which explains the improved performance of the pulsed current annealed device compared to its as-received counterpart.Other defects, such as vacancies and interstitials, are also expected to be annealed to some extent under the influence of EWF.However, within the obtained HRTEM image resolution, it was not possible to discern such defects between the two samples.
Cross-sectional EDX mapping was performed in STEM mode in order to monitor the diffusion of elements, if any, under high-density current pulses.The EDX maps of elements of as-received and pulsed current annealed samples are shown in figures 6(a)-(l), respectively.High density current induced elemental segregation and diffusion are common phenomena, known as electromigration, in electronic devices [43,44].However, no segregation or diffusion of elements can be observed across the device layers despite applying a highdensity current.This is due to the very low duty cycle of the pulsed current, which actively suppresses the temperature rise due to joule heating.The EDX results further confirm the localized defect-specific application of EWF without perturbing the surrounding lattice atoms.
The obtained results illustrate that process-induced defects are possible to mitigate at room temperature using EWF generated by high-density pulsed current.Here, the pulsing parameters are optimized for improved performance of the GaN diode.This room temperature annealing technique could potentially be useful for other electronic devices.However, when applying this technique on devices, care should be taken when selecting the pulsing parameters such as the duty cycle, pulse width, and pulsing time to avoid any joule heating, which could accumulate heat locally, generating new defects.Here, we used an ex-situ pulsing method to improve the performance of bulk devices.To gain further understanding of the mechanism of mitigation of different kinds of defects, such as point defects and dislocations, in-situ pulsing experiments inside a TEM should be investigated.

Conclusions
In this study, a room temperature defect mitigation technique has been demonstrated to improve the performance of a lowtemperature processed vertical GaN p-n diode.Our technique exploits the EWF generated by a high-density pulsed current to minimize the ion-implanted defects of the GaN layer.Low duty cycle current pulses were used to suppress the joule heating, while the scattering of electrons by defects exerts strong EWF to mobilize the defects.This pulsed current annealing has improved the transport properties of the GaN p-n diode, as demonstrated by lower specific on-resistance, a smaller ideality factor, a slightly lower leakage current, and a higher rectification ratio.The improvement of the GaN crystal quality has been confirmed by Raman studies, which showed narrower Raman E 2 (high) and A 1 (LO) peaks and relaxation of ionimplanted strain to some extent after pulsed current annealing.The TEM results along with GPA strain maps of HRTEM images further confirm the reduced defect and dislocation density of the GaN layer of the pulsed current annealed device compared to the as-received counterpart, while the EDX maps reveal no noticeable diffusion of elements as a result of applying a high-density current pulse.The demonstrated technique has the potential to eliminate high-temperature thermal annealing and associated process complexities, where room temperature device processing is required without compromising device performance.Finally, the annealing effect of the proposed technique was observed for a few days to weeks, suggesting that the events are not transient.However, longer term effects on the breakdown and long-term aging of the device are yet to be investigated.

Figure 1 .
Figure 1.(a) Schematic cross section of the GaN p-n diode, (b) the pulsed current annealing parameters with low duty cycle, and (c) a thermal microscope image showing real-time temperature rise during pulsed current annealing.

Figure 2 .
Figure 2. (a) Forward I-V characteristics, (b) reverse I-V characteristics, (c) specific on-resistance and ideality factor, and (d) rectification ratio and maximum leakage current at −200 V.

Figure 3 .
Figure 3. (a) The E 2 (high) and (b) A 1 (LO) Raman peaks of the GaN of the as-received and pulsed current annealed (7 × 10 5 A cm −2 ) samples.The peaks were fitted using the pseudo-Voigt model.

Figure 5 .
Figure 5. HRTEM images of the as-received sample (a) near the GaN-Pd interface and (b) the GaN layer away from the interface; HRTEM images of the pulsed current annealed sample (c) near the GaN-Pd interface and (d) the GaN layer away from the interface; geometric phase analysis strain maps of (e), (f) the as-received and (g), (h) pulsed current annealed HRTEM images.

Figure 6 .
Figure 6.EDX mapping of (a)-(f) the as-received and (g)-(l) the pulsed current annealed (7 × 10 5 A cm −2 ) sample.(a) High angular dark field image and (b)-(f) corresponding elemental maps of the as-received sample; (g) high angular dark field image and (h)-(l) corresponding elemental maps of the pulsed current annealed sample.