Measurement and gate-voltage dependence of channel and series resistances in lateral depletion-mode β-Ga2O3 MOSFETs

Lateral depletion-mode, beta-phase gallium oxide (β-Ga2O3) metal-oxide-semiconductor field-effect transistors (MOSFETs) with source-drain spacings of 3 µm, 8 µm, and 13 µm are studied using a modified transfer length method (TLM) to obtain sheet resistances in the gated and ungated regions as well as to observe their gate electric field dependence. The modified TLM requires the contact resistance to be independent of the gate-source voltage, or changing current density. We verify this by performing measurements on conventional TLM structures in dark and UV conditions and observe a changing current density with constant contact resistance, enabling the development of the proposed method. The conventional and modified TLM give sheet resistances of 20.0 kΩ sq−1 ± 1.0 kΩ sq−1 and 27.5 kΩ sq−1 ± 0.8 kΩ sq−1, respectively. Using a traditional method for determining the channel resistance, the modified TLM improves the convergence of the channel resistances between the three devices, showing higher accuracy than the conventional TLM structures. Gate-source voltage dependence of the sheet resistances is seen in the ungated regions, leading to non-ideal behavior which cannot be observed using the traditional method and conventional TLM structures. These results and analysis methods are important in improving MOSFET parameter extraction and understanding the gate electric field effects on the channel and series resistances in β-Ga2O3 MOSFETs.

Lateral depletion-mode, beta-phase gallium oxide (β-Ga 2 O 3 ) metal-oxide-semiconductor field-effect transistors (MOSFETs) with source-drain spacings of 3 µm, 8 µm, and 13 µm are studied using a modified transfer length method (TLM) to obtain sheet resistances in the gated and ungated regions as well as to observe their gate electric field dependence. The modified TLM requires the contact resistance to be independent of the gate-source voltage, or changing current density. We verify this by performing measurements on conventional TLM structures in dark and UV conditions and observe a changing current density with constant contact resistance, enabling the development of the proposed method. The conventional and modified TLM give sheet resistances of 20.0 kΩ sq −1 ± 1.0 kΩ sq −1 and 27.5 kΩ sq −1 ± 0.8 kΩ sq −1 , respectively. Using a traditional method for determining the channel resistance, the modified TLM improves the convergence of the channel resistances between the three devices, showing higher accuracy than the conventional TLM structures. Gate-source voltage dependence of the sheet resistances is seen in the ungated regions, leading to non-ideal behavior which cannot be observed using the traditional method and conventional TLM structures. These results and analysis methods are important in improving MOSFET parameter extraction and understanding the gate electric field effects on the channel and series resistances in β-Ga 2 O 3 MOSFETs. * Author to whom any correspondence should be addressed.
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Introduction
The modernization of the electrical grid and the widespread adoption of electric vehicles require the development of high performance, power electronic components. Beta-phase gallium oxide (β-Ga 2 O 3 ) is an attractive material for high-power applications owing to its ultra-wide bandgap of ∼4.8 eV [1,2], projecting a breakdown electric field of approximately 6 MV cm −1 -8 MV cm −1 , leading to an extremely high Baliga's figure of merit of 3300 which is approximately 3-10 times larger than that of GaN and SiC [3]. In addition, because β-Ga 2 O 3 is the only wide bandgap semiconductor that can be grown from the melt [4][5][6], there is economic incentive to develop β-Ga 2 O 3 -based power devices.
Improved growth, material quality and fabrication techniques lead to rapidly increasing β-Ga 2 O 3 power device performance with breakdown voltages, V BR , up to 8.32 kV, breakdown fields up to 6.45 MV cm −1 , and high power figure of merit up to 13.2 GW cm −2 [7][8][9][10][11][12][13][14][15][16][17]. Field-effect transistors (FETs) designed for radio frequency performance have also been fabricated [18][19][20]. Many studies focus on optimizing the V BR and on-resistance, R on , of Schottky barrier diodes and FETs [7,9,14,15,19,[21][22][23][24][25][26], however, these results are heavily affected by parasitic resistance, such as contact and series resistances [22]. Conventional hall and transfer length method (TLM) structures are often used to measure mobility and sheet resistances [7, 9-11, 18, 21, 22, 27, 28], but their utility in explaining field-effect device behavior is limited. Accurately determining the parasitic and channel resistance contributions in a transistor is a difficult challenge but is crucial for modeling and designing future device architectures. As β-Ga 2 O 3 metal-oxide-semiconductor FETs (MOSFETs) are optimized with additional fabrication steps, it becomes increasingly more important to characterize devices without the use of conventional test structures. Previous research on the use of the TLM on FETs was performed on gated-TLM (GTLM) structures based on GaAs metal-semiconductor FETs to measure the series and channel resistances by considering a changing gate length and constant source-gate and drain-gate spacings [29,30]. Byun et al created an analytical model based on effective gate length modulation to determine the source series resistance variation with gate-source voltage, V GS [30].
We report on the development of a modified TLM that considers the varying sheet resistance between the source and drain of depletion-mode β-Ga 2 O 3 MOSFETs, allowing direct extraction of realistic device parameters and observation of their gate-dependent behavior. The modified TLM has an advantage over using conventional TLM structures in that it can provide more accurate series and channel resistances and show non-ideal series resistance dependence on the gate voltage, which cannot be observed with the conventional TLM. Different with this previous research, our method is designed for power electronic MOSFETs that incorporate a varying gate-drain spacing, L GD , requiring a modification from the conventional GTLM. Recently, there have been studies using similar methods on 2D FETs [31,32], but this is believed to be the first report on applying this method to β-Ga 2 O 3 FETs.

Experimental methods
The β-Ga 2 O 3 MOSFET devices are fabricated via similar processes according to Moser et al [28]. A 50 nm Si-doped β-Ga 2 O 3 homoepitaxial layer is grown by molecular beam epitaxy on a commercially available semi-insulating (010) Fe-doped β-Ga 2 O 3 substrate. The epitaxial layer has a target doping concentration of 2.4 × 10 18 cm −3 which is confirmed using electrochemical capacitance-voltage measurements. Plasma-enhanced atomic layer deposition is used to deposit ∼20 nm of Al 2 O 3 as the gate dielectric and an evaporated Ni/Au gate is patterned with lift-off. Ohmic contacts to the epitaxy layer are created with a Ti/Al/Ni/Au evaporated metal stack and rapid-thermal annealing at 470 • C for 1 min in a nitrogen ambient environment. Contact pads are added with additional Ti/Au evaporation. A cross-section schematic of a β-Ga 2 O 3 MOSFET device is shown in figure 1(a). The spacing between source and drain, L SD , varies between 3 µm, 8 µm, and 13 µm, while the gate length, L G , and gate-source spacing, L GS , remain constant at 2 µm and 0.50 µm, respectively. This series of FETs is similar to conventional TLM structures with varying electrode spacing. Figure 1(a) defines the terms used in the analysis where, R C is the contact resistance, R S is the source side semiconductor resistance, R D is the drain side semiconductor resistance, and R ch is the channel resistance. In the following analysis, the source/drain extension regions are referred to as the ungated regions and the portion directly underneath the gate is referred to as the gated, or channel, region. Figure 1(b) shows a microscope photo image of a 2 × 50 µm β-Ga 2 O 3 MOSFET with L SD = 3 µm. DC characterization measurements were performed in a commercial probe station in air and at room temperature using an Agilent 4156B [33] semiconductor parameter analyzer.

Results and discussion
The TLM structures on this sample consist of contacts with a width of 80 µm and spacings of 5 µm to 30 µm at 5 µm intervals, inset of figure 2(a). The epitaxial layer is the same as for the MOSFET devices.   (c) Resistance vs length, with 5% uncertainty, and linear fit lines for TLM structures measured in dark (gray, square) and UV exposure (red, circle) conditions. The inset in (c), shows the increase of the transfer length of the contact due to the increased current. The arrow indicates that the y-intercept, and therefore R C , is nearly the same under dark and UV conditions. TLM measurement is repeated while exposed to UV illumination (265 nm, 2.8 W cm −2 ) as shown in figure 2(b) to study the effect of changing current density on the current crowding near the contacts, similar to the gate-source effect in MOSFETs. Figure 2(c) plots the resistance against the contact spacing. The measured resistance can be written as where R sh is the semiconductor sheet resistance, L is the contact spacing, and W is the contact width. A plot of R vs. L gives R sh from the slope and R C from the y-intercept. The transfer length, L T , is the average distance a charge carrier travels in a semiconductor under the contact before entering the contact and is thus a measure of current crowding. This can be determined from the x-intercept of R vs. L. Four TLM structures are measured showing significant variation in R sh across the sample, potentially due to doping inhomogeneity. Table 1 summarizes results from the conventional TLM measurements including specific contact resistivity, ρ C , and increase in apparent channel thickness, t ch,UV /t ch,Dark , due to the decreasing depletion region under UV illumination. The standard deviation of these results ranged between 5% and 12% of the mean. These values are in agreement with previous reports [7,11,22,24,34]. As seen from figure 2(c) and table 1, R C remains relatively unchanged between dark and UV conditions, while L T increases, causing ρ C to increase. The larger current forces L T to increase, while R sh decreases. Such an inverse relationship between sheet resistance and contact resistivity, given by, due to illumination is also seen in solar cell studies [35][36][37].
The constant R C in dark and UV conditions observed in the TLM measurements, figure 2(c), suggests that the increase in current due to an external source, such as illumination, has no effect on R C . Similarly in MOSFETs, V GS modulates the current as an external source. Therefore, R C is not a function of V GS and is assumed constant in the following analysis.
The DC transfer and output characteristics of three FETs with L SD of 3 µm, 8 µm, and 13 µm are shown in figures 3(a)-(f). The transfer characteristics are measured at very low V DS to minimize changes in the potential distribution between the drain and the gate, which is required for channel resistance measurements. The measured FETs are located near each other to reduce the effect of R sh variation. The threshold voltage, V th , determined from linear extrapolation of transfer curves at a V DS of 10 mV, is ∼−3.5 V for all devices. All FETs exhibit good linearity when V GS > V th , considering they are depletion-mode, and pinch-off capability due to I ON /I OFF ratios ranging from 10 7 -10 9 at low V DS . The worst-case gate current ranges between 2 × 10 −10 mA mm −1 and 2 × 10 −9 mA mm −1 . At a V DS of 10 mV, the maximum transconductance, G M , of the FETs with L SD of 3 µm, 8 µm, and 13 µm are 20 µS mm −1 , 13 µS mm −1 , and 9 µS mm −1 , respectively. From the output curves in figure 3, the on-resistance, R on , at a V GS of 2 V is found to be 115 Ω mm ± 6 Ω mm, 260 Ω mm ± 13 Ω mm, and 330 Ω mm ± 17 Ω mm for the FETs with L SD of 3 µm, 8 µm, and 13 µm, respectively. These results are comparable to other β-Ga 2 O 3 MOSFET devices [11,22,23]. Overall, the MOSFETs show good field-effect behavior.
Currently, the accepted way to extract the FET channel resistance, R ch , is from where R sh,G is the sheet resistance in the gated region, and R C and R sh are determined from conventional TLM structures. The terms R sh L GS and R sh L GD are equal to R S and R D , respectively, rewritten in terms of a sheet resistance. R on is equal to V DS /I D and calculated from the transfer curves in figures 3(a), (c), and (e) at a V DS of 10 mV. The channel resistance, R ch , is converted to a sheet resistance, R sh,G , for better comparison to the modified TLM and is shown in figure 4(a).
The inset in figure 4(a) shows the large maximum separation of 24 kΩ sq −1 ± 1.2 kΩ sq −1 in R sh,G at high V GS between devices with different L SD . This is due to variation in R sh across the sample, as was seen in the conventional TLM results. A more precise R sh can be obtained using the modified TLM described below.
With the added gate contact in the MOSFET, the sheet resistance between the source and drain is no longer assumed to be uniform as in conventional TLM structures. We modify the TLM accordingly by separating the ungated and gated regions of the semiconductor. Referring to figure 1, R on is written as where R ′ sh and R ′ sh,G are the sheet resistances in the ungated and gated regions, respectively, found from the modified TLM. These are different than R sh and R sh,G which are found from conventional TLM structures and equation (2), respectively. Because the minimum spacing between the gate and either the source or drain contacts, L GS in this case, is approximately ten times larger than the channel thickness, the depletion region can be assumed to reside directly underneath the gate and the effective L G remains constant at all V GS [29]. Similarly, there is assumed to be no V GS dependence on R C as discussed previously. Equation (3) suggests that plotting R on vs (L GS + L GD ) should yield a straight line with a slope of R ′ sh and intercept of 2R C + R ′ sh,G L G . It is not possible to also determine R C from this method alone, so R C is taken from the conventional TLM structure results, 22.5 Ω mm ± 1.1 Ω mm, to determine R ′ sh,G . However, if additional FETs with varying L G , as in the GTLM, are fabricated, then R C can be extracted without the use of conventional TLM structures. A linear regression is performed on the R on values for −3 V ⩽ V GS ⩽ 3 V. The goodness-of-fit measure, R 2 , is above 0.95 for the entire V GS range used in the analysis. Figures 4(b) and (c) show the extracted R ′ sh,G and R ′ sh , respectively, from the modified TLM using the transfer curves from figures 3(a), (c), and (e) at a V DS of 10 mV. Figure 4(b) shows a strong V GS dependence for R ′ sh,G , as expected, which ranges from 650 kΩ sq −1 ± 32 kΩ sq −1 at a V GS of −3 V to 20.0 kΩ sq −1 ± 1.0 kΩ sq −1 at a V GS of 3 V. This is due to the decreasing depletion region under the gate with increasing V GS .
A weaker, but significant V GS dependence is seen with R ′ sh , figure 4(c), which ranges from 153 kΩ sq −1 ± 22 kΩ sq −1 at a V GS of −3 V to 27.5 kΩ sq −1 ± 0.8 kΩ sq −1 at a V GS of 3 V. This is further shown in figure 4(d) by the linear regression at V GS of −3 V and 3 V where there is an increase in the slope with decreasing V GS . In the idealized case, there should be no V GS dependence in the ungated region. This could be due to multiple effects including lateral depletion region growth and unpassivated surface states at the Al 2 O 3 /air interface that trap injected charge from the gate metal. These are more prominent when a depletion region is present, which is consistent with the trend in figure 4(c). This observation is being actively investigated by simulation and measurements to ascertain surface and interface trap passivation in β-Ga 2 O 3 MOSFETs. At higher V GS , R ′ sh flattens to 27.5 kΩ sq −1 ± 0.8 kΩ sq −1 , a significant difference from the TLM result. A much better convergence of the R sh,G plots for the devices with L SD of 3 µm, 8 µm, and 13 µm is achieved using R ′ sh at a V GS of 3 V in place of R sh in equation (2), figure 4(e). The inset in figure 4(e) shows the reduced separation between of 5.6 kΩ sq −1 ± 0.3 kΩ sq −1 in R sh,G at high V GS .
Lv et al published output curves of β-Ga 2 O 3 FET devices with two different L GD and used equation (2) to determine R ch . They measured R sh from the traditional TLM structures to be 13 kΩ sq −1 but using the modified TLM and plotting R on vs L GD gives R ′ sh ranging from 7 kΩ sq −1 to 9 kΩ sq −1 , a factor of 0.53-0.7 less than what is reported. In another β-Ga 2 O 3 device work [9], applying the modified TLM determines R ′ sh of 3.5 kΩ sq −1 similar to their R sh from conventional TLM structures, but a similar V GS dependence is seen at sh increases to 10 kΩ sq −1 . Bittle et al and Urban et al used a similar method to the modified TLM on back-gate organic FETs and graphene transistors, respectively [31,32]. They observed similar trends as figure 4(b) as well as an additional effect of a changing R C with V GS due to the back-gate. R C dependence on V GS does not apply here due to the top gate geometry and the significant distance between the gate and the source/drain contacts.
We have successfully applied a modified TLM to determine the source, drain, and channel resistances in depletionmode β-Ga 2 O 3 FETs. However, further improvements can be made by increasing the accuracy of R ′ sh,G and minimizing the assumptions. Gated-TLM structures can provide a more precise R C , and therefore R ′ sh,G , as well as further validation of R ′ sh and R ′ sh,G . The assumptions in this method are that (1) the contacts and (2) ungated regions have no V GS dependence, (3) and the FETs used in this analysis have the same R ′ sh and R ′ sh,G . Assumption (1) is validated by the UV measurements on the conventional TLM structures, figure 2(c). From figure 4(c), assumption (2) is observed to be incorrect and requires further study to develop an accurate model. Assumption (3) can be validated by using devices near each other, as was done in this work, and the R 2 fit parameter greater than 0.95 for the entire V GS range.
One significant advantage of this method is that it can be applied to various FET architectures including state-of-theart lateral enhancement-mode, recessed-gate, delta-doped, and field-plated FETs. Possible variations of this method could also be developed to fit a particular design.

Conclusion
In conclusion, we apply a modified TLM to lateral depletionmode β-Ga 2 O 3 MOSFETs to extract transistor sheet resistances in the gated and ungated regions, observed their V GS dependence, and compared them to those of the conventional TLM structures. A constant R C is seen in dark and UV TLM measurements, allowing us to assume no effect on the contact with changing current density in the FET. The V GS dependence in R ′ sh , the sheet resistance in the ungated regions from the modified TLM, is a non-ideal behavior and further work is needed to understand its cause. One possible hypothesis is that unpassivated surface states in the Al 2 O 3 /air interface trap charge from the gate contact, increasing the effective L G .

Data availability statement
The data cannot be made publicly available upon publication because no suitable repository exists for hosting data in this field of study. The data that support the findings of this study are available upon reasonable request from the authors.