AlGaN/GaN superlattice-based multichannel RF transistors for high linearity and reliability: a simplified simulation approach

Multichannel RF power amplifiers offer high frequency operation, high current and RF power, combined with excellent linearity. 3D and 2D simulation is used to investigate how changes in device architecture impact both the linearity and off-state reliability, allowing an improved linear design which does not compromise reliability. Linearity is assessed by extraction of gm3/gm′′ , and third order intercept (TOI) as a function of gate bias, using a straightforward 2D approximation which is computation time and resource efficient compared to the full 3D simulation normally used for these devices. Off-state reliability is assumed to be linked to dielectric failure, and hence peak electric field as a measure of reliability is evaluated at gate corners and edges using a full 3D simulation. It is found that introducing a channel number-dependent doping in the AlGaN/GaN-based superlattice structure can be used to enable an improved transconductance–linearity. It is also found that there is a strong increase in TOI as gate dielectric thickness or fin width is increased. On the other hand, in order to maintain reliability, increased fin height is found to be essential in order to reduce electric field as dielectric thickness is increased. Finally, a device architecture for improving linearity, power and reduced OFF-state field is suggested.


Introduction
AlGaN/GaN-based HEMTs have established themselves as the most suitable candidate for RF power amplifiers and power switching applications. This is due to the high twodimensional electron gas (2DEG) density, mobility, saturation velocity, thermal conductivity, and high breakdown voltage compared to other semiconductors [1][2][3][4]. GaN Fin-FETs and single quantum-well based GaN trigate transistors have demonstrated enhanced gate controllability, high ON/OFF ratio, normally OFF-operation, high OFF-state BV (500 V), high linearity and low thermal resistance [5][6][7][8][9][10][11]. Recently, lateral GaN transistors with multiple quantum-wells stacked on top of each other, have received increasing attention due to higher electron density (up to 5 × 10 13 cm −2 ) and lower ON-resistance (R S < 80 Ω sq −1 ) than conventional HEMTs and GaN FinFETs [12]. Such multi-channel field-effect transistors (FETs) have already demonstrated excellent suitability for high power RF applications in terms of output current density (>2.7 A/mm), power density (P out > 9.5 W mm −1 at 30 GHz), power added efficiency, PAE (>45% at 30 GHz), frequency of operation (f T /f max = 47 GHz/124 GHz) and linearity (OIP3/P 1dB = 14 dB at 30 GHz) [13]. However, owing to their complex epitaxy and gate architecture, the physics and operation of such transistors are not that well investigated. This makes device optimization non-trivial to achieve its full potential for commercial applications. An optimized device structure is crucial not only to maximize the device performance but also for better reliability.
Linearity of transistors is a crucial parameter in RF power amplifiers. Non-linearity in AlGaN/GaN transistors are mainly caused by increased source-access region resistance [14], selfheating [15,16] and optical phonon scattering [17]. The detrimental effect of non-linearity is particularly significant in high power RF applications. It causes intermodulation distortion (IMD) where multiple frequency components along with the input signal are produced at the output stage of the amplifier. A well-designed linear amplifier also simplifies the circuit design, which reduces their area and power consumption. Many studies have been carried out to improve the linearity in a conventional single-channel HEMT. This includes using a thin n-GaN layer in the buffer [18], graded-AlGaN channel [19], double-channel heterostructures [20], lateral gates [21], transitional recessed gate [22] and nanowire-channel HEMTs [23]. Although, AlGaN/GaN based multichannel devices have huge potential for use as power amplifiers, not many studies have been devoted to address the linearity in these devices. Shinohara et al demonstrated improved linearity in multichannel FETs by superimposing fins of different width [24]. In this paper, a multichannel GaN transistor is shown to improve linearity by modulating the epitaxy through a reduction in the first and second differentials of g m with gate-to-source voltage (V GS ). This improvement has been demonstrated by solving Poisson's equation and drift-diffusion equations, using the Silvaco ATLAS device simulator. A comprehensive study of such a structure, until now, was hindered primarily due to the high computation time, iterations and resources involved in simulating such a complex 3D structure. To overcome this, a novel and time-efficient 2D simulation technique to design the stack is proposed.
Reliability will be a crucial aspect for the commercial adoptability of multichannel devices along with high power performance. The pursuit of improved linearity with multiple channels will require tri-gate structures rather than the planar gate in conventional GaN HEMTs [12,24,25] in order to be able to control all of the stacked channels. This gate architecture introduces edges and corners to the device geometry which are known to cause electric field crowding detrimental to device reliability [26,27]. Again, reliability studies available in literature focus primarily on single channel conventional GaN-HEMTs only, which are often not that relevant to assess reliability of multichannel GaN transistors. In this work, we have also addressed some of the possible reliability issues such improved linearity transistors may encounter. Conventional GaN HEMTs can have many modes of failure arising for instance from thermal degradation of contacts, hot electron trapping in dielectric and semiconductors, and material failures due to the high electric field and hot electrons [28,29]. In particular, dielectric degradation becomes a serious concern due to electric field crowding at edges and corners of the fin. Degradation processes like current collapse, dynamic R ON , time dependent dielectric breakdown, can be electric fielddriven by the charge (de)trapping in the dielectric layer. Traps can also be generated in the dielectric during the operation of the device in both OFF-state and ON-state [30]. Here, focus is on the OFF-state dielectric degradation under the gate region, by biasing the transistor with V GS < V T and V DS = 0. Driftdiffusion solver in a 3D space has been used to estimate the distribution of electric field in the dielectric. The peak electric field in the dielectric is found to be dependent on fin geometry.
Designing a structure for simultaneous better linearity and reliability can lead to degradation in power-performance. Device improvements are discussed varying the width, separation and height of fin and dielectric thickness. Finally, an optimisation strategy which encompasses improved linearity, power and reliability is proposed. This analysis is applicable to both high-power RF devices and RF switches.

Device structure
Different epitaxies of multichannel FETs have been reported [12,24,25], however the AlGaN/GaN-based superlattice structure of Heikmann et al [31] has been demonstrated to be a good candidate for multichannel FETs, successfully preventing hole gas formation. Figure 1(a) shows one such epitaxial structure designed using that approach having multiple layers of AlGaN/GaN heterostructures, considering here a sevenchannel 2DEG system. The 2DEG at the topmost AlGaN/GaN interface results from spontaneous and piezoelectric polarization, for which the surface donor states act as the source of electrons. Using this design, in our simulation this topmost 2DEG has a density of 3 × 10 12 cm −2 under the gate. The AlGaN/GaN interfaces underneath are populated by polarization in the AlGaN together with carriers from the n-doped graded AlGaN barrier (N D = 1 × 10 19 cm −3 ), which results in 2DEG of 1.5 × 10 12 cm −2 in each of the remaining six channels. Selective donor doping of the graded AlGaN layers is also helpful in reducing the scattering of free electrons in the 2DEG.
A conventional top gate will be able to control only the topmost channel since the bottom channels would be electrostatically shielded by this topmost channel. Gates wrapped on three sides of a fin (or Ω-gate) help deplete carriers laterally in addition to the top gate control. The schematic cross-section through one such fin is shown in figure 1(b). To reduce the gate leakage, the device was taken to have conformally deposited layer of Silicon Nitride (SiN) as the dielectric layer. SiN is chosen since it forms a type-II band alignment with GaN resulting in negative valence band offset (∆E V ). As a result, it forms a hole-barrier-free region under the gate preventing hole accumulation. Thus, the undesirable scenario of enhanced electric field in the gate dielectric is avoided [32]. As gate metal, Ni with a work-function of 5 eV, was used to wrap around the fins on three sides to have effective control of all the channels. In figure 1(c), the equilibrium band diagram of the structure and the electron concentration along a cutline in y-axis (AA', shown in figure 1(b)) at the centre of fin is plotted. It shows channels at each of the AlGaN/GaN interface. The 3D structure of the multichannel transistors, used in this work, having multiple such fins along with source and drain contacts is illustrated in figure 1(d), with the simulation considering just a single fin.

Method of simulation
As the lateral electric field from the side gates helps deplete all channels in addition to the top gate, this necessitates the solution of electrostatics in the x-y plane (figure 1(b)) coupled with drift-diffusion equations in multiple carrier transport yz planes. Transport studies of such an architecture in 3D space, however, are time-consuming and prone to convergence issues. To solve this issue: (1) the symmetry of the structure in the x-y plane of figure 1(b) has been exploited to define a half-fin structure and (2) a source (Ohmic) contact has been introduced as shown in figure 2(a). This introduction, which has been facilitated by the fact that ON-resistance of such devices is dominated by channel-resistance [23,33], helps pin all the channels to a common potential. Thus, this accessregion free structure will approximately imitate the operation of a 3D three-terminal FET device in ON-state in the linear (low V DS ) regime. However, it fails once the channels are pinched-off. It will also introduce slight distortion of the real transfer curve near the threshold voltage, V T if channels pinchoff at different voltages. The simulation of such a 2D structure will involve only solving electrostatics using the Poisson's equation without the need to solve transport equations. Quantum effects are not considered in this work. This time and resource-efficient technique helps the optimisation of complex 3D-multichannel device epitaxy by 2D simulations which would otherwise not be practical. For such Ohmic operation devices without access regions, the terminal-to-terminal voltage drops, V GS and V DS can be replaced by intrinsic potential difference v GS  show more electrostatic control from the gate than the channels sandwiched (CH 2 to CH 6 ) between them. This is due to the influence of the top gate and GaN back-gating effect, respectively, along with the side gate. The rest of the sandwiched channels (CH 2 -CH 6 ) are electrostatically shielded from the top and back-gate. For such devices, akin to junction FETs, the conductivity occurs in the bulk of the fin away from the gate-dielectric interface. As a result, the effect of surface scattering arising from gate bias on channel mobility can be assumed negligible. In such scenario, a constant channel mobility as a function of gate bias is a valid assumption. Such architectures with low access-region resistances have demonstrated excellent device linearity at high drain currents [23,33]. The transfer function, I DS -V GS of each channel can be estimated by extracting the bias-dependent 2DEG density, n s−i , where n s−i is extracted from the integral of the free electron distribution in the vicinity of the ith AlGaN/GaN interface. The resulting n s−i -V GS is plotted in figure 3(a). As expected, the electrostatic control of each channel depends on its position in the stack. The n s−i in sandwiched channels, CH 2-5 , overlaps on top of each other and differs from CH 1 and CH 7 . The current drive follows the order: CH 1 > CH 7 > CH 2-6 . This can be attributed to higher 2DEG and gate coupling in CH 1 . An analytical expression of intrinsic transistor transconductance, g m−i of ith channel is obtained by assuming operation of the transistor in the linear region using, where, I DS−i is the drain current in ith channel, e is the electron charge, n s−i is the carrier density (in cm −2 per channel per fin) in the ith channel, w is the width of the fin, µ is the mobility, L G is the gate-length, and v DS and v GS are the voltage drops of the intrinsic transistor (without access regions) along drainsource and gate-source respectively. Then using the earlier assumed invariance in mobility, the g m−i (in S/channel/fin) in the gated region of the transistor is, Assuming the constants µ = 1600 cm 2 V −1 s −1 , w = 60 nm, v DS = 0.5 V and L G = 250 nm; g m−i is plotted as shown in figure 3(b), and has magnitude CH 1 > CH 7 > CH 2 -6 .

Design for high linearity
We demonstrated, using the 2D simulations outlined in section 3, a methodology for approximating the transconductance of each individual channel in a multichannel GaN FET. Hence the differential electrostatic control of each channel can be exploited to spread their transconductance curve along the voltage axis. The second derivative of g m which is proportional to IMD has been extracted to investigate the effectiveness of this linearization strategy [21,35]. In this work the contribution of gate capacitance, C G whose contribution towards IMD is less than 10% has not been explored [36].
The electrostatic control of each channel can be tuned by modulating the AlGaN barrier doping. CH 1 could have another degree of freedom in the form of the thickness of the top AlGaN layer. The etch-depth of the fin below CH 7 , could influence the electrostatic behaviour of CH 7 . To explore the effects of each of these parameters separately on each channel, half-fin simulations have been performed by varying only one parameter at a time on the original structure in figure 1. Figure 4(a) shows the n s−1 -V GS and g m−1 -V GS of CH 1 for different thicknesses of the top AlGaN layer. There is only a marginal increase in |V T | and g m−1 as thickness increases. Growing a very thick topmost AlGaN layer will result in a truly side-gated transistor. The response of the sandwiched channels to modulation in the AlGaN n-doping is captured in figure 4(b) by plotting the response of CH 2 . Lowering the doping results in a lower carrier density at the AlGaN/GaN interfaces, which needs lower |V G | for its depletion. This can be observed from both the n s−2 and g m−2 plot. Figure 4(c) shows the response of CH 7 on etch-depth. It is observed that the changes in n s , g m and V T are insignificant over a large change in etch-depths. From the result obtained from figures 4(a)-(c), it can be determined that n-doping in AlGaN layer is the crucial parameter for changing the g m curve. Thus, the epitaxy in figure 1(a) has been modified aiming to improve linearity as shown in figure 4(d). The thickness of the top AlGaN layer has been increased to 24 nm from 16 nm and doping in the graded AlGaN layer is decreased as the layers are grown, as shown in figure 4(d). Note that this is one of the many solutions available for improving the linearity. The resulting g m of each channel is plotted in figure 4(e), which shows that the g m curves are separated along the voltage axis unlike in the original structure in figure 3(b).
This placement of g m curves of CH 2 to CH 7 along the voltage axis is a strong function of equilibrium carrier density, n s in the respective channels. The g m curve of CH 1 is an outlier from the trend. This can be attributed to the combined effect of higher n s and coupling from the top gate. The net effect of g m of all the channels is plotted in figure 4(f) as a function of V GS and is compared to that in the original heterostructure in figure 1(b). The modification in epitaxy has resulted in a gradual rise in g m while keeping the same V T . The second derivative of g m (=g ′ ′ m ) is observed to be lower for the improved structure in the ON-state operation except for The improvement in linearity as measured by g ′ ′ m is achieved at the cost of reduced n s , which reduces the g m too. So, g ′ ′ m is not sufficient as a measure of linearity, since a larger modulation in n s may further improve the g ′ ′ m but can degrade the high-power performance. Third order intercept (TOI) is a better figure of merit to measure this power-linearity trade-off, which extracts the maximum output power for which the signal can be assumed linear. A methodology to extract TOI using I DS -V GS from the simulation is discussed in this section. The two-port output signal, V o (t) for an input signal, V G (t) in the presence of non-linearity is given by [37,38] where k i are the coefficients in a Volterra series expansion. For a sinusoidal input signal V G (t) = A cos (ωt), such a system will result in output power (units of dBm), where R is the load resistance. This expression has the desired gain term and an undesirable gain compression term. TOI is defined to be when the two terms are equal, at which Then, the power at TOI becomes P TOI = 10 × log 10 Thus, k 3 1 /k 3 gives an estimate power at TOI which can be approximated to g 3 m /g ′ ′ m from equation (1) P TOI = 10 × log 10 In figure 5, P TOI has been extracted from the I DS -V GS data obtained from 2D-simulations (width normalized to 1 mm) and assuming a load resistance, R of 50 Ω. The original structure along with the channel-dependent doping is plotted.
Both the structures show a peak, called linearity sweet spots (inset of figure 5), tending to infinity at the zero-crossing in g ′ ′ m . Channel-dependent doping has moved the sweet spot towards positive V GS . Although, P TOI is preserved towards the right of sweet spot, a degradation is found in linearized structure for lower values of V GS . Thus, it is crucial to tune the location of linearity sweet spots (section 7) in order to preserve or even improve the high-power performance.

Reliability
To harness any linearity gains of channel-dependent doping in multichannel devices, for real-world usability reliability should also be given attention. This is particularly significant since three sided wrapped-gate dielectric and metal contact will cause electric field crowding at corners and edges. In this section, reliability of the device linearized in section 4 is considered. The distribution of the electric field in OFF-state operation has been explored using the conventional 3D simulations, since as noted earlier 2D simulation cannot describe OFF-state. Since the device is biased in OFF-state, the results are not affected by the choice of transport model. This part of the study has been performed (V GS < V T = −6 V) on fully depleted fins with vertical side walls. The device simulated with drain-source separation of 4 µm and gate length of 400 nm is shown in figure 6(a). No field plates are considered in this study.
Various planes have been probed to identify the location of the maxima in the electric field. In figure 6(b), an xy cut-plane is taken in the middle of the fin (z = 0) and the electric field contour is plotted. High field in the dielectric is observed at the bottom edge in dielectric near the gate. The field profile at the corners of the gate is plotted in figure 6(c) where the x-y cut-plane is taken at the edge of the gate (z = 0.2 µm). Here the bottom corners show even higher fields. This undesirable increase in field is an unavoidable consequence of the 3D device architecture; however the actual value obtained from the simulations is mesh and curvature of corner dependent. Hence, for comparative purposes, a common mesh is used at all edges/corners and the field is probed at a constant distance of 2 nm from the corner. The increase in field at corners can also be seen in figure 6(d) where the y-x cut-plane in the dielectric near the side gate (along x = −63 nm or the dotted line in figure 6(c)) is plotted. This brings to focus the necessity to mitigate the field at the bottom corners for OFF-state reliability. The effect of various process parameters like etch-depth, dielectric thickness. fin-width, and fin-separation has been studied by the selfconsistent solution of Poisson and drift-diffusion equations in 3D.  Figure 7 shows the effect of etch depth on the electric field at the gate corners. Etch-depth, t is defined as the over etching of the fin from the bottommost 2DEG. The magnitude of the field at corners reduces as the etch-depth is increased (assuming a depleted buffer). This trend can be explained based on the displacement, x i of the corners from the 2DEG as shown in figure 7(a). The larger the displacement the smaller would be the electric field. The 'diminishing returns' in reduction in peak electric field can be attributed to the inverse square dependence of field on displacement. The displacement, x i can be modulated by changing: (1) the etch-depth, t i and (2) the dielectric thickness, d i . Increasing the etch-depth will monotonically increase this displacement. On the other hand, increasing the dielectric thickness pushes the corner laterally away from the bottommost 2DEG as well as vertically closer to it. The displacement, x i can be modelled by the parabolic relationship

Etch depth and dielectric thickness
where, d i is the dielectric thickness and d z is the depletion distance of 2DEG in the z-direction. The displacement, x i has a minimum at d i = t/2, which corresponds to a maximum in the electric field. However, for any practical implementation, as suggested from figure 7, it is highly recommended to have t ≫ d i . This also helps in lowering the sensitivity of corner E-Field to d i as shown in figure 8(b). The field for etch-depth, t =50 nm follows a parabolic curve which peaks at t/2 =25 nm, in accordance with equation (6). Whereas in the case of etchdepth, t =200 nm, the increase in field is insignificant. This increasing trend in electric field with dielectric thickness is counter-intuitive to that seen in conventional HEMTs but arises because the corner curvature is kept constant in the simulation. A thinner dielectric results in a slightly lower E-field at the corner and higher g m . However, of course it comes at the cost of increased field in the bulk of the dielectric enabling easier electron (de)trapping resulting in reduced stability. This has been shown in figures 8(c) and (d) where x-y cut planes at the edge of the gate (at z = 0.2 µm) show the electric field distribution. The device with thinner dielectric (d i = 10 nm) shows a relatively higher magnitude of electric field (compared to that at corners) on the edges than the device with thicker dielectric (d i = 35 nm).  Figure 9 shows the effect of varying the fin-width on the distribution of electric field in the x-y plane at the edge of the gate. Two fin-widths are considered, w =60 nm and w =30 nm whose V T are around −6 V and −2.5 V respectively. Both the devices have been depleted by biasing at a high V GS = −50 V which makes the variation in V T insignificant for comparison. The larger fin-width device (w = 60 nm) exhibits a higher electric field at the corners compared to the smaller width device (w = 30 nm). This is due to the larger depletion charge present in wider fins. Once the fins are depleted most of the potential drops in the buffer leaving behind a higher field on the corners of wider fins. Also, a relatively higher field is observed on the edges and bulk of the dielectric in the case of wider fins for the same reason. This effect of fin width on OFF-state reliability has been experimentally verified in [39]. The effect of changing the fin-separation, s for a fixed width (w =60 nm) device is shown in figure 10. The device with a smaller fin-separation is observed to have a higher peak Efield at the corners due to the proximity of corner fields from neighbouring fins. However, in general the fin separation has only a limited effect on corner field. Also, the width of device will have to be scaled to compensate the reduction in current drive from wider separation of fins.

Effect of geometry on linearity and power
The changes in the device parameters to reduce the peak electric field (discussed in section 5) will impact the linearity of the channel-dependent doped structure in section 4. To confirm this, the 2D technique developed in section 3 has been invoked again to compute g ′ ′ m and TOI. By fixing the epitaxy as in the linearized structure, variations are made in the etch-depth, dielectric thickness, fin-width, and separation independently. This is summarized in figure 11. As shown in figures 11(a) and (d), the linearity of the device is found not to be affected by etch-depth, t and fin separation, s. This is since these two parameters can be assumed to have negligible effect on the ON-state behaviour. A thicker dielectric thickness is found to desirably reduce g ′ ′ m in figure 11(b). This can be attributed to the increase in |V T |, which would result in a more gradual rise of g m with V GS . It can also be observed that as the dielectric thickness increases, the linearity sweet spot moves towards negative V GS . From figure 11(c), a thinner fin is also found to reduce g ′ ′ m . This reduction, despite having a lower V T , comes at the cost of lower 2DEG density in thinner fins. Again, the rightwards movement of sweet spot could hamper P TOI as fin width is reduced.
To find the 'usefulness' of these devices by modifying the dielectric thickness and fin-widths, TOI has been calculated in figure 12. With the reduction in dielectric thickness ( figure 12(a)), the V GS range for which P TOI remains unaffected shrinks. This happens due to the movement of linearity sweet spot towards positive V GS , as seen from the peak in the plot. Thus, a thicker dielectric improves the power performance along with linearity. In the case of reducing fin-width, as shown in figure 12(b), the simulated P TOI suffers from the both the rightward movement of sweep spot in V GS and lower current carrying capacity due to reduced 2DEG density. This reveals an important trade-off exists between reliability and

Improved device architecture
The modification in linearity from channel-dependent doping and thicker dielectric along with reduction in peak electric field obtained from a deep etch-depth can be exploited to design a linear RF power amplifier with lower off-state electric field. One such design has been implemented and compared with the original structure (used in figure 2). The modifications in device geometry to achieve this are summarized in table 1. The result so obtained is shown in figure 13. The improved structure, as shown in figures 13(a) and (b), shows a flatter g m and effectively smaller g ′ ′ m . This reduction in g ′ ′ m is the combined effect of channel number dependentdoping and thicker dielectric. Thicker dielectric helps compensate the rightward displacement in V GS of linearity sweet spot arising from channel number dependent-doping. This can be observed from the identical zero-crossing of g ′ ′ m in figure 13(b) and peaks in P TOI in figure 13(c). This tuning of sweet spot has increased P TOI for V GS left of sweet spot and no degradation to its right. The lowering of peak electric field in dielectric for the improved structure is observed in figure 13(e) compared to the original structure in figure 13(d). This has been made possible primarily by a deeper etch depth and marginally by wider separated fins.

Conclusions
The AlGaN/GaN-based multichannel devices have been investigated for better linearity and reduced off-state electric field by varying the epitaxy and fin geometry in the active region under the gate. Linearity have been evaluated using a simple 2D electrostatic simulation, instead of simulations requiring solution of carrier transport equations in the 3D space. This technique helps design such multichannel transistors in a time and resource-efficient manner. A gradual change in doping level with depth in the superlattice helps to spread the effective transconductance curve along the gate-voltage axis, without a steep rise. Peak OFF-state E-field near the gate corner in the dielectric is used as the measure of offstate reliability. This high field can be reduced by having deep etch-depth of fins and thinner fins, and to a lesser extent by increasing their separation from each other. TOI is shown to be strongly affected by fin-width and dielectric thickness. TOI degrades for thinner width devices due to reduced 2DEG density and linearity sweet spot modulation, giving rise to a reliability-power trade-off. A thicker dielectric helps improve TOI by increasing the threshold voltage and tuning the linearity sweet spot, respectively. Ultimately, an architecture is proposed with channel-dependent doping, deeper etch depth, thicker dielectric thickness and wider fin-separation which improves the linearity and reduces the OFF-State field.

Data availability statement
All data that support the findings of this study are included within the article (and any supplementary files).