Improved drain lag by reduced surface current in GaN HEMT via an ultrathin HfO2 blanket layer

This paper reports the influence of an ultrathin 1.5 nm atomic-layer-deposited HfO2 blanket layer as a gate dielectric on GaN high-electron-mobility transistors (HEMTs) grown on a 4H-SiC substrate. Transistors with a gate length of 250 nm and a source-to-drain distance of 3 µm were manufactured. The proposed technique involves HfO2 deposition at 250 ∘C prior to the gate metallization with no additional lithography steps. This approach reduced the drain lag by 83% compared to the conventional design with no gate dielectric. The HfO2 layer suppressed the parasitic lateral conduction from the gate, reduced surface trapping, and improved gate electrostatics. The manufactured devices exhibited nearly three orders of magnitude decreased surface leakage, better turn-on behavior, and improved cut-off frequency f T linearity by 16%. High quality metal-oxide interface formation was confirmed by the conductance method. Results demonstrate that the blanket HfO2 deposition is a promising approach to improve the current dispersion characteristics and gate electrostatics of GaN HEMTs without incurring major changes to the established fabrication techniques.


Introduction
Gallium nitride based high-electron-mobility transistors (HEMTs) are afflicted by trapping-induced current dispersions [1]. Upon recovering from their off-states with a non-zero drain potential, HEMTs display a severe reduction of the drain current, which is called drain lag. This lagging behavior lowers the radio-frequency power output substantially [1][2][3][4]. The dominant mechanism of drain lag is trapping on the surface above the drain access region [1]. Filled traps deplete the two-dimensional electron gas (2DEG), increase the channel resistance, and shift the threshold voltage.
Drain lag can be mitigated by inserting gate dielectrics. For example, Hove et al showed that a Si 3 N 4 (10 nm)/Al 2 O 3 (5 nm) gate dielectric stack can suppress drain lag [5]. Similarly, Anand et al studied an Al 2 O 3 (5 nm)/Si 3 N 4 (5 nm) gate dielectric stack and achieved a similar improvement [6]. However, thick gate dielectrics produce devices with highly reduced transconductances due to the increased gate-tochannel spacing [7]. Also, thick gate dielectrics lead to a significant threshold hysteresis due to bulk traps residing within the dielectrics [8].
Besides these adverse impacts the gate dielectrics have on the IV characteristics, thick dielectrics also present structural instability issues. For example, HfO 2 and Al 2 O 3 layers show poly-crystallization at temperatures as low as 500 • C and 600 • C, respectively [9]. Poly-crystal films are not desirable as they are less reproducible, less uniform, and exhibit higher leakage currents compared to amorphous layers [10]. Solid phase transitions are especially worrisome in the case of GaN HEMTs, which experience temperatures of up to 900 • C during fabrication and show peak hot-spot temperatures of around 250 • C during nominal operation. These issues ultimately limit the commercialization of MOS-HEMT and MIS-HEMT devices.
On the other hand, ultrathin films have the potential to alleviate these problems while offering prominent improvements over the Schottky-gate design. Thin atomic-layer-deposition (ALD) layers are thermodynamically more stable and less likely to exhibit phase transitions under thermal cycling [10]. Also, bulk trap densities associated with thin layers are usually smaller. In general, the first few ALD cycles passivate the semiconductor surface, while subsequent ALD cycles increase bulk trap densities [11]. For example, Sim et al investigated the impact of ALD HfO 2 thickness on silicon field effect transistors. They reported that transistors with 1.8 nm thick gate dielectric exhibited the least threshold voltage instability compared to the transistors with 2.5 nm and 3.3 nm films [12]. Similarly, Kim et al studied ALD AlN layers on GaN. They noted that trap densities of the 7.4 nm thick AlN layer were four times that of the 1.5 nm layer, while both samples displayed similar leakage characteristics [13]. Therefore, downscaling the gate dielectric thickness can be a promising compromise for improving transistor threshold stability, reliability characteristics, and transconductance.
There is very little work on ALD ultrathin gate dielectrics on AlGaN/GaN HEMTs. For example, Yuan-Zheng et al studied a 3.5 nm Al 2 O 3 gate dielectric [14]. Zhang et al demonstrated a 5 nm thick SiN x plasma enhanced ALD (PEALD) layer on recessed GaN HEMTs [15]. To demonstrate further downscaling of the GaN HEMT gate dielectrics, we studied a 1.5 nm thick gate dielectric. To the best of our knowledge, this work represents the thinnest ALD gate dielectric study on AlGaN/GaN HEMTs. The 1.5 nm film thickness choice is motivated as follows: In an earlier study, we investigated ultrathin ALD HfO 2 film growth characteristics over a crystalline host (TiO 2 ). We observed that ALD HfO 2 deposition exhibited the typical traits of the island growth mode [16]. We also discovered that full surface coverage, conformality, and island coalescence could only be obtained after 15 ALD cycles, corresponding to a film thickness of 1.5 nm as measured by transmission electron microscopy (results not shown). In light of this experiment, we opted to limit the downscaling of the gate dielectric to 1.5 nm.
In this work, we decided to employ HfO 2 as a gate dielectric material to demonstrate the benefits of the ultrathin approach. Nevertheless, we believe that our approach is material system independent. As explained above, susceptibility to solid phase transitions and increase in the bulk trap densities is known to increase with dielectric thickness regardless of the material. On the other hand, there are several reasons why we decided on HfO 2 to demonstrate this technology. First, using HfO 2 as an ultrathin layer is attractive from a reliability point of view. HfO 2 is a dense material and can suppress gate metal electromigration and oxygen diffusion into the epitaxy and produce more reliable devices [17]. HfO 2 exhibits a large conduction band offset with AlGaN, which helps reduce gate leakage [18]. Gao et al showed that adsorbed water moisture on the AlGaN barrier exacerbates the current collapse phenomenon [19]. HfO 2 is known to exhibit hydrophobic surface properties [20]. Hydrophobicity could reduce the surface sensitivity of the GaN HEMTs and help fabricate more stable devices. Finally, HfO 2 is a high-k dielectric and does not significantly reduce the device transconductance.
This paper studied the influence of an ultrathin (1.5 nm) HfO 2 gate dielectric on GaN HEMTs. The HfO 2 deposition before the gate metallization reduced the electron injection into surface states near the gate contact. Manufactured devices exhibited a highly suppressed drain lag behavior, superior leakage, turn-on, and linearity characteristics than those without the HfO 2 application. No degradation of the IV properties was observed.

Device fabrication
The Fe-doped AlGaN/GaN epitaxial structure was grown on a 3 ′ ′ 4H-SiC substrate by metal-organic chemical vapor deposition (MOCVD). The barrier structure consisted of a 10 Å AlN spike, a 20 nm Al 0.28 Ga 0.72 N, and a 3 nm GaN cap layer. Fabrication was commenced with the ohmic contact patterning by optical lithography. Then, a Ti/Al/Ni/Au stack was deposited via electron-beam evaporation and annealed in an N 2 environment at 840 • C for 30 s. Following a Cl 2 based 100 nm mesa etch, a 75 nm silicon nitride passivation layer (SiN x ) was deposited in a plasma-enhanced chemical-vapor-deposition system (PECVD). After the SiN x passivation layer deposition, e-beam lithography was used to define the T-gate foot regions. Then, the SiN x was selectively dry-etched in the foot regions. Subsequently, one set of the devices received the 1.5 nm HfO 2 film by ALD using tetrakis dimethylaminohafnium and deionized water as precursors at 250 • C. After the HfO 2 deposition, both samples were annealed at 450 • C for 10 min in N 2 . Following the annealing step, T-gate head regions were defined using e-beam lithography, and a Ni/Au gate stack was deposited using e-beam evaporation. Finally, samples were annealed at 400 • C for 30 s in N 2 for Schottky interface stabilization. The device cross-section and design dimensions are outlined in figure 1(a). The process flow is displayed in figure 1(b). Figure 2 shows the simulated conduction band energy diagram of the gate stacks. Band diagram calculations were carried out in Silvaco ATLAS [21]. The band alignment parameters between HfO 2 and GaN were taken from the literature [22]. As shown in figure 2, HfO 2 deposition increases the barrier height for electrons and can effectively reduce the electron injection into the epitaxy.

Results and discussion
Double-pulsed measurements were taken to analyze the trapping behavior under and near the gate. Quiescent voltages were set to (V GQ1 , V DQ1 ) = (−6 V, 0 V) and (V GQ2 , V DQ2 ) = (−6 V, 25 V), respectively, for gate and drain lag. The pulse width was 500 µs, and the duty cycle was 0.1% to effectively fill the traps.  deposited sample only showed a 25 mV shift. Both samples displayed an identical gate lag response, indicating that the devices equally suffered from trapping underneath the gate caused by bulk trap states in the barrier. These traps can not be passivated with surface modifications; therefore, they are not of interest in the present study.
Next, the drain lag suppression mechanism was investigated by surface conduction measurements. In the virtual gate model, the trap states on the barrier surface are filled with electrons upon electron injection from the gate electrode. This trap filling action depletes the channel near the gate electrode and shifts the threshold voltage [1]. Therefore, surface leakage correlates well with the drain lag performance [23]. Surface current was measured by adopting the approach by Tan et al with a gate-to-gate distance (L gg ) of 5 µm [23]. Figures 4(a) and (b) shows the cross-sectional view of the devices used in the surface conduction measurements. Figure 5(a) displays the results. The surface current is reduced by about three orders of magnitude, which is in close correlation with the drain lag improvement. These results are consistent with earlier reports on SiN x passivation in the literature, i.e. as the HfO 2 film surrounds the gate metal, it reduced electron conduction to the traps on the drain access region and improved both the leakage characteristics and drain lag performance [23]. Similarly, Liu et al investigated 10 nm ALD Al 2 O 3 blanket layers and achieved a comparable improvement in the surface current [24]. This comparable improvement albeit the difference in the film thicknesses might be because thicker films may support additional lateral conduction mechanisms. Grain boundary formations in thick polycrystalline ALD films introduce parasitic conduction paths, usually via variants of Poole-Frenkel and trap-assisted tunneling mechanisms [25,26]. Since the HfO 2 film studied in this work is only 1.5 nm thick, polycrystalline grain formation and associated conduction mechanisms could be inhibited, thereby improving the surface leakage characteristics. However, more work is needed to confirm this argument.
To verify the proper operation of transistors, Schottky leakage ( figure 5(b)) and two-way I D − V G and I G − V G (figures 6(a) and (b)) measurements were conducted. Schottky leakage results display two orders of magnitude decrease. This reduction is owing to the large conduction band difference between HfO 2 and GaN [22]. As summarized in table 1, this improvement in the gate leakage is comparable to or even better than some of the reported work on thicker gate dielectrics. Two-way measurements show that both samples exhibited negligible counter-clockwise hysteresis, indicating that trapping in the oxide was insignificant [8]. Table 1   verifies the view that bulk traps in the thick dielectrics lead to an inferior threshold voltage stability performance. Also, the HfO 2 deposited transistor delivered better turn-on characteristics, as evidenced by the reduced subthreshold slope of 94 mV dec −1 at V D = 0.1 V due to the leakage reduction [28].   voltage. Specifically, the negatively shifted threshold voltage in the HfO 2 deposited transistor suggests a higher electron density underneath the gate electrode compared to the reference device. This increased electron density reduces the intrinsic resistance of the transistor, resulting in a higher drain current. Thus, the shift in the threshold voltage is likely the primary cause of the observed difference in the drain current. Also, as expected, the ultrathin high-k HfO 2 film insertion did not significantly degrade the transconductance (only 5% reduction) [7]. This drop is almost negligible compared to transconductance loses of the thicker dielectric insertion attempts (see table 1). The off-state breakdown characteristics of the transistors were studied to understand the impact of the HfO 2 layer on gate electrostatics. The drain current was limited to 2 mA mm −1 during the breakdown measurements to avoid catastrophic damage, in a similar fashion to the [29,30]. The drain voltage at which this current limit was attained was determined to be the breakdown voltage. The results are displayed in figure 8. The devices exhibited a soft-breakdown behavior within the studied drain voltage range, which indicates a poor depletion of electrons despite the pinching-off of the channel. This is an expected behavior as the gate length is only 250 nm, which makes the devices susceptible to short-channel effects such as punch-through [29]. On the other hand, the HfO 2 sample demonstrated an 88 V off-state breakdown voltage at V G = −6 V, two times that of the reference transistor, which is a clear improvement compared to the conventional HEMT. Ohno et al investigated the influence of surface passivation on the breakdown performance and found that the suppression of electron trapping at the surface relieves the high electric field formation in the drain access region and improves the breakdown characteristics [31]. In parallel with Ohno's findings, we believe that the suppression of surface trapping by the reduced surface current improved the gate electrostatics and, consequently, the breakdown behavior.
The conductance method was adopted to study the HfO 2 film quality [32]. Parallel capacitance-conductance measurements were taken over the frequency range 10 kHz-1 MHz. Figure 9 shows the conductance method results. Trap density was calculated by fitting G p /ω = qωτ it D it (1 + (ωτ it ) 2 ) −1 to the calculated G p /ω curves, where q is the elementary charge, ω is the radial measurement frequency, D it is the trap density, and τ it is the trap time constant [33]. The calculations were carried out under the assumptions of discontinuum of trap energy levels (as opposed to a trap continuum near the interface) and negligible series resistance. The trap density results are given in figure 10(a). Our trap density results are compatible with the literature [18,34]. The HfO 2 deposited sample showed an as much as 60% reduction in the trap density within the studied range, demonstrating the quality of the HfO 2 -GaN interface. This trap density reduction suggests that the HfO 2 film was able to passivate a significant portion of the surface traps. Figure 10(b) shows the extracted trap time constants τ it using the conductance method. The trap lifetimes of the HfO 2 deposited sample were approximately 3 µs, which is 50% more than the reference sample's trap lifetimes. This could be due to the formation of HfON and GaON bonds at the interface [35].  Small-signal measurements were taken over the frequency range 0.4-28 GHz at various gate biases ( figure 11). The pad parasitics were not de-embedded. The peak f T dropped by approximately 5% due to the reduced transconductance. Linearity was evaluated by defining a gate voltage swing (GVS) parameter corresponding to the values larger than 95% of the peak f T . Linearity improved by 16%, corresponding to a GVS span of 1.86 V. This improvement can be understood quantitatively by referring to the governing equations of the small-signal regime. As a first-order approximation, f T is 1/2πτ int where τ int is the total time for electrons to go across the confines of the gate electrode. Under the influence of drain bias, τ int must be replaced with τ tot = τ int + τ drain , where τ drain accounts for the spreading of the effective gate length [7]. We propose that HfO 2 deposition has reduced the variations in τ drain by hindering the electron flow to the surface, thereby limiting the lateral reach of the gate depletion region, thereby improving the gate electrostatics and linearity. However, this argument is not yet conclusive and warrants further investigation.

Conclusions
Blanket deposition of a 1.5 nm thin HfO 2 layer shows a remarkable success in suppressing drain lag. HfO 2 dielectric hampers lateral conduction of electrons injected from the gate contact, reduces trapping on the device surface, and does not degrade the transistor transport properties. The proposed manufacturing technique is readily applicable to the conventional GaN HEMT fabrication processes, requiring only one additional step with no lithography.

Data availability statement
The data cannot be made publicly available upon publication because no suitable repository exists for hosting data in this field of study. The data that support the findings of this study are available upon reasonable request from the authors.

Acknowledgments
E Özbay acknowledges partial support from Türkiye Bilimler Akademisi (TUBA). This work was supported by Turkcell Technology within the framework of 5G and Beyond Joint Graduate Support Program coordinated by the Information and Communication Technologies Authority. The authors would like to thank E Aras, S Zafar, and M I Nawaz for their help with the small-signal measurements as well as D Yilmaz, V Baris, and T Semiz for their support in device fabrication.