Low temperature atomic hydrogen annealing of InGaAs MOSFETs

Recent work showing a strong quality improvement of the Si/SiO2 material system by low temperature atomic hydrogen annealing (AHA), and the fact that III–V semiconductors outperform Si in many applications makes the investigation of AHA on III–V/high-k interfaces to a very interesting topic. In this work, the potential of AHA as a low temperature annealing treatment of InGaAs metal–oxide–semiconductor field-effect transistors is presented and compared to conventional annealing in a rapid thermal process (RTP) system using forming gas. It is found that post metal annealing in atomic hydrogen greatly enhances the quality of the metal–oxide–semiconductor structure in terms of effective mobility, minimum subthreshold swing, and reliability. The device performance is comparable to RTP annealing but can be performed at a lower temperature, which opens up for integration of more temperature-sensitive materials in the device stack.


Introduction
Today's digitalized society relies on the advancement of silicon complementary metal oxide semiconductor (CMOS) technology, but the limitations of down-scaling in combination with the rapidly increasing demand for added functionality not easily achieved in Si has pushed efforts to development of III-V semiconductor technology. The direct bandgap and higher carrier mobility of III-Vs would enable for highperformance optoelectronic and high frequency applications * Author to whom any correspondence should be addressed.
Original content from this work may be used under the terms of the Creative Commons Attribution 4.0 licence. Any further distribution of this work must maintain attribution to the author(s) and the title of the work, journal citation and DOI. [1,2]. Further, the ability to form highly-transparent interfaces to superconducting electrodes, as well as large spin-orbit interaction, make narrow bandgap III-Vs interesting for emerging quantum technologies [3,4].
In III-V metal-oxide-semiconductor field-effect transistor (MOSFET) technology, the gate oxide is usually deposited using atomic layer deposition (ALD). ALD provides the possibility to deposit a gate oxide with high dielectric constant and thus a low equivalent oxide thickness (EOT). A bilayer of Al 2 O 3 /HfO 2 provides a high-quality interface to the semiconductor combined with a low EOT [5]. However, one of the key issues with III-V/high-k interfaces is to reduce the amount of interface traps, oxide traps and charged defects leading to degraded device performance. This is in general more difficult as compared with Si technology, due to complex oxides formed by the presence of several atomic species, as well as lower thermodynamic stability of III-Vs as compared with Si.
The density of interface traps (D it ) is one limiting factor of the device performance in terms of the subthreshold swing (SS), see equation (1) SS = kT q ln (10) (C ox + qD it ) /C ox (1) where, k is the Boltzmann constant, T is the temperature, q is the elementary charge, C ox is the oxide capacitance and D it is the density of traps which mainly originates from traps at the interface, as well as border traps. Also, a charged interface and border defects act as scattering centers, leading to increased channel scattering and reduced mobilities [6]. Reducing the effects of such defects are of importance to obtain high quality device operation, with high mobility and low subthreshold swings. However, several studies have shown that annealing of InGaAs/HfO 2 , InGaAs/Al 2 O 3 or InGaAs/(Al 2 O 3 /HfO 2 ) stacks in gas mixtures containing hydrogen leads to a significant reduction of D it [7][8][9][10][11][12] and increased mobility which can be explained by hydrogen passivating electrically-active border-and interface traps that inhibit Fermi level movement [8]. It has also been shown that hydrogen can passivate both O and Al dangling bonds, thus neutralizing fixed charges [9]. Even though annealing in gas mixtures containing hydrogen generally improves the device performance, III-Vs still suffer in device variability. This is due to the inability to realize high quality high-k and high-k/III-V interface at low annealing temperatures. In Si technology a high temperature reliability anneal at 900 • C is performed to yield high quality oxide and reliability. This can unfortunately not be performed in III-V technology due to their temperature sensitivity. It has however been shown that atomic hydrogen annealing (AHA), i.e. annealing a sample in a low pressure flow of hydrogen radicals, can greatly improve the oxide quality and reliability in Si/SiO 2 material systems [13,14]. AHA at as low temperature as 100 • C gives even higher oxide quality than annealing at 900 • C in molecular hydrogen [14]. AHA has also shown great impact on Ge/GeO 2 interfaces [15]. So far the investigation of AHA in combination with III-Vs is lacking. Here, we investigate the potential of AHA as a low-temperature annealing process that possibly could give improved device performance and less device variability of III-V MOSFETs.
One application of III-V technology is as an add-on to silicon CMOS in the back-end-of-line (BEOL) for 3D heterogeneous integration. The BEOL technology has stringent demands on the temperature budget, which could fit well with the lower temperature used for III-V technologies. Thus, also a lowtemperature annealing process is required. The investigation in this paper is focused on the InGaAs material system but should be applicable to other III-Vs, for instance GaN, which is very interesting for high-power applications.
Here, we postulate and systematically investigate the use of AHA to lower the temperature needed during the annealing process of InGaAs MOSFETs. This is performed by fabrication and annealing of InGaAs MOSFETs. The device performance is evaluated in terms of SS and effective mobility, µ n . The mobility is related to the conductivity, σ, according to (2), where n and p corresponds to the electron and hole carrier concentrations, and µ n and µ p corresponds to the mobility of electrons and holes respectively. Since our device is unipolar, (2), can be rewritten as (3), which shows that the conductivity is directly proportional to the extracted mobility: Investigation of threshold voltage (V T ) shifts and reliability measurements have also been performed as well as the gate current dependence on annealing temperature. The device performance is greatly enhanced with a peak performance when AHA is performed at 250 • C for 30 min. The effective mobility and SS are comparable to if rapid thermal process (RTP) annealing in forming gas is performed at 350 • C. The lower annealing temperature makes it possible for integration of more temperature-sensitive materials in the device stack.

Method
The devices used for this study are junction-less InGaAs MOS-FETs fabricated on InP substrates. A schematic of the process flow is shown in figure 1.
Prior epitaxial growth, the substrate, InP:Fe (100), was cleaned using an optimized pre-growth cleaning procedure [16]. The substrates were cleaned by oxidation in ozone for 10 min followed by removal of the formed oxide by HF 1:1000 in order to get an as clean and pristine surface as possible. The epitaxial layers were then grown by metal organic vapor-phase epitaxy (MOVPE) in an Aixtron 200/4 reactor. After the pre-growth etch step, a thin (4 nm) InP buffer layer was grown followed by growth of an In 0.71 Ga 0.29 As layer (13 nm). The growth was performed at 600 • C and 100 mbar using trimethylgallium (Ga(CH 3 ) 3 ), trimethylindium (In(CH 3 ) 3 ), arsine (AsH 3 ) and phosphine (PH 3 ) as precursors, with H 2 as carrier gas. MOSFETs were then fabricated, with varying gate lengths between 6 and 30 µm and gate widths of 6 and 70 µm. The devices were electrically isolated from each other by a mesa etch defined by UV lithography and wet etching (H 3 PO 4 :H 2 O 2 :H 2 O (1:1:25) followed by HCl:H 2 O (1:1)). Source and drain electrodes were defined by UV-lithography, electron beam evaporation (Ti/Pd/Au) and lift-off in acetone. Before deposition of the gate oxide the samples were cleaned and the InGaAs surface passivated by 8 min ozone cleaning at room temperature followed by immersion in (NH 4 ) 2 S:H 2 O (1:1) for 20 min. The deposited gate oxide consisted of a bilayer of Al 2 O 3 /HfO 2 (1/10 nm) deposited by thermal ALD at 300 • C and 120 • C, respectively. Then the gate metal was defined by UV lithography, electron beam evaporation (Ti/Pd/Au) and lift-off in acetone.   Fabricated devices were indium glued on a stainlesssteel sample plate and then transferred into a UHV chamber (p < 10 −9 mbar) for AHA. A beam of hydrogen radicals (H·) was created using a commercial thermal cracker (from MBE Komponenten GmbH), operating at a cracking temperature of 1700 • C-1730 • C with a H 2 base pressure of 2 × 10 −6 mbar and mounted 15-20 cm above the sample. Devices were annealed at temperatures between 100 • C and 350 • C for time intervals between 20 and 60 min. Sample temperatures above 250 • C were measured directly using a pyrometer and temperatures below the pyrometer limit (T < 250 • C) were measured using a thermocouple connected to the sample plate, which was calibrated using the pyrometer at higher temperatures. For comparison, devices were also annealed in H 2 (without thermal cracker) and Ar gas environment.
The devices were electrically evaluated by extraction of SS and effective mobility. The effective mobility is obtained from the slope of a least squares linear fit to the on-resistance (R on ) versus gate length (L g ), fitted for devices with L g between 6 and 30 µm, see equation (4) where, C g ∼ 0.6 µF cm −2 is the gate capacitance and V ov is the overdrive voltage (0.3 V). The devices were further investigated by reliability measurements, where the devices were stressed at a specific V ov for 300 s and then the threshold voltage, V T , shift was measured. A fresh device was used for each stress voltage.

Results and discussion
The electrical characterization showed a great improvement of the device performance by AHA, with a peak µ n ∼ 4500 cm 2 Vs −1 and SS ∼ 100 to ∼110 mV/decade for AHA performed at 250 • C for 30 min. This is 100 • C lower temperature than RTP annealing but gives comparable device performance. The thermionic limit of SS at room temperature is 60 mV/decade, and the higher extracted value here can be explained by the relatively thick gate oxide of ∼10 nm. However, similar devices fabricated previously have measured SS below 80 mV/decade [16]. Please, note that in all figures (except figure 10) data from devices fabricated during different process runs are included. The devices are fabricated according to the same process scheme and should be very similar. The only parameter extracted that clearly depends on the specific process run is V T , which is very sensitive to the conditions in the ALD chamber during deposition of the high-k, which may vary slightly from run to run. The spread between devices from the same process run is however small. In figures 7 and figure 9 the different process runs are indicated to make this clear. Figure 3 shows the minimum SS (a) and effective mobility (b) for samples annealed in atomic hydrogen for 30 min at different temperatures. Both SS and µ n are compared to samples annealed in a RTP system at 350 • C for 5 min in forming gas. A comparison between PMA and PDA is also included. Before annealing a 95% confidence interval gives SS from ∼190 to ∼200 mV/decade and µ n from ∼1200 to ∼2300 cm 2 Vs −1 . It is clear that PMA gives better result than PDA both in terms of SS and effective mobility. The highest performance for PMA samples is at an annealing temperature of 250 • C, showing a strong improvement in mobility to µ n ∼ 4500 cm 2 V −1 s −1 as well as a reduction in SS down to ∼100 to ∼110 mV/decade. The performance then decreases with higher temperature, which could be related to diffusion at the semiconductor/high-k interface and/or crystallization of the relatively thick HfO 2 . Especially for the PDA anneals both the mobility and SS degrades quickly for higher temperatures, and above 250 • C the PDA data shows very scattered R on versus L g which makes it impossible to reliably extract an effective mobility. At 250 • C the PMA AHA sample has comparable SS to the RTP annealed sample but even higher effective mobility. In the case of the mobility we only have one data point and no strong conclusion can be drawn, but this indicates that AHA could be a feasible route for passivation of interface defects at reduced temperatures.
To explore lower temperature budgets, in figure 4 even lower temperatures are investigated and the annealing time is kept constant at 20 min. The effective mobility and SS are shown as a function of annealing temperature. The device performance of the AHA samples are increasing with increasing annealing temperature up to 250 • C, giving SS down to ∼100 mV/decade and µ n ∼ 2900 cm 2 V −1 s −1 . But even at much lower temperature, T = 150 • C, there is a great improvement compared to before annealing which reduces SS ∼120 to ∼125 mV/decade and µ n to ∼2600 cm 2 V −1 s −1 . The best values for SS at T = 250 • C is comparable to the RTP annealed samples while the maximum effective mobility is lower, but as we can see in figure 5 the maximum effective mobility for the AHA samples is after 30 min annealing. In figure 5 SS and effective mobility is plotted against annealing time for samples annealed at 250 • C. For AHA samples the performance improves until 30 min annealing and then starts to degrade, which again could be explained by diffusion at the semiconductor/high-k interface. After 30 min the performance is comparable to the RTP annealed sample but with higher effective mobility. Figure 6 shows annealing in different atmospheres. Blue data points correspond to annealing at 250 • C for 20 min, while red data points correspond to RTP annealing for 5 min in forming gas, and black data points are measured before any annealing. It is clear that the performance is not improved as much if the annealing is performed in Ar compared to H 2 or H·. This can be explained by the lack of hydrogen passivation of defects in the oxide and interface, and thus giving a smaller improvement of D it , most likely originating from reduction of disorder in the oxide. Annealing in H 2 or H· gives comparable SS but the effective mobility is slightly higher if the annealing is performed in H 2 . The hydrogen radicals are extremely reactive and are expected to react with the first atom they hit. Even though there is a directed flux of H· towards the sample surface most of the H· will probably not reach the contact area as H· but rather as H 2 , which could explain the similar device performance. On the other hand the gate metal may act as a catalyst for splitting of H 2 molecules into H· [12,17]. Therefore regardless if it is H· or H 2 reaching the contact area H· will be formed and effectively passivate defects close to the semiconductor/high-k interface. This explanation is in line with the worse performance of the PDA samples, where the lack of a gate metal leads to less H· at the semiconductor/highk interface.
In figure 7 V T for samples annealed in atomic hydrogen for 30 min at different temperatures is plotted and compared to samples annealed in RTP at 350 • C for 5 min in forming Minimum SS (a) and effective mobility (b) for samples annealed in atomic hydrogen for 30 min. A comparison to samples annealed in RTP for 5 min in forming gas as well as a comparison between PMA and PDA is also included. It is clear that PMA gives better results than PDA both in terms of SS and effective mobility. Above 250 • C Ron versus Lg is just scattered data for PDA samples which makes it impossible to extract any effective mobility. PMA for 30 min at 250 • C in atomic hydrogen gives comparable performance to RTP annealing in forming gas at 350 • C for 5 min. Above 250 • C the performance decreases with increasing annealing temperature, which could be related to diffusion at the semiconductor/high-k interface and/or crystallization of the relatively thick HfO 2 . gas. Note that the RTP samples correspond to three separate process runs clearly showing different V T , where the encircled data corresponds to the same process run as the AHA samples. A comparison between PMA and PDA is also included. For PMA samples annealed in H·, V T seems to decrease with decreasing annealing temperature, and in figure 8 even lower temperatures are investigated, showing a further decrease in V T until ∼100 • C for AHA devices. Before annealing there is For AHA samples the performance improves until 30 min annealing and then starts to degrade, which could be explained by diffusion at the semiconductor/high-k interface. After 30 min AHA the performance is comparable to RTP annealing but with even higher effective mobility. a big spread between devices which is reduced after annealing in H·. From figure 7 it is also evident that V T does not increase as much for the RTP samples which could be because of the short annealing time and insufficient time for diffusion, which is in line with our investigation of different annealing times, see figure 9. Also in figure 9 the RTP samples correspond to Figure 6. SS (circles) and effective mobility (stars) for different annealing atmospheres. It is clear that the performance is not improved as much if the annealing is performed in Ar compared to H 2 or H·. Which is because Ar is inert and will not passivate defects in the oxide and semiconductor/high-k interface. Annealing in H 2 or H· gives comparable SS but the effective mobility is higher if the annealing is performed in H 2 . three different process runs, where the encircled data is from the same process run as the AHA samples annealed for 30 and 60 min.
In figure 10 the reliability as obtained from positive bias temperature instability measurements before and after annealing is compared. The obtained V T shifts can be well fitted with a standard power law expression. The reliability Before annealing there is a big spread between devices which is reduced after annealing. The RTP data corresponds to samples from three separate process runs, where the encircled data is from the same process run as the AHA samples annealed for 30 and 60 min. measurement is performed by holding a specific V ov for 300 s and then measure the V T shift. From the power law fits, we obtain a reduction in traps by a factor 2 after AHA at 250 • C for 20 min. Both RTP and H 2 annealing gives worse reliability, whereas the exponent is close to 2 for all anneals, indicating no major change in the defect distribution. The slightly higher exponent for the AHA sample can indicate a more peaked defect distribution.
Another indication of the quality of the oxide is the gate current, which is plotted as a function of annealing temperature in figure 11. Here the gate current is plotted as a function of annealing temperature. As long as the AHA Figure 10. Reliability before and after annealing. The solid lines correspond to power law fits to the data points. The V T shift is measured after stressing at a specific Vov for 300 s. The smaller V T shift of the AHA annealed sample indicates a 50% reduction in the defect density at the oxide and semiconductor/high-k interface. The other two annealing procedures gives slightly higher V T shifts after annealing. Figure 11. Gate current versus annealing temperature. The gate current is low for AHA samples annealed at 250 • C but then increases, which could be due to crystallization of the gate oxide. However, the RTP annealed samples do not show any increased gate current, which could be due to the short annealing time and the oxide will thus not have time to crystalize. temperature is below 250 • C the gate current overlaps with the gate current measured before annealing, but above 250 • C the gate current starts to increase. This can be explained by crystallization of the gate oxide and current leakage between the crystals. The RTP annealed samples on the other hand do not show any increased gate current even though the annealing temperature is 350 • C, which could be due to the short annealing time and the oxide will thus not have time to crystalize.

Conclusion
We have investigated the potential of AHA as a low temperature annealing process for InGaAs MOSFETs. The device performance is greatly improved by AHA and comparable to the performance obtained after RTP annealing in forming gas. We have also confirmed that the reliability is improved and the gate current is kept low if the AHA is performed at 250 • C for 20-30 min. The performance is highest when AHA is performed at 250 • C for 30 min. If the annealing time is shortened or the annealing temperature lowered there is not sufficient time and energy for fully hydrogen passivation of defects in the oxide and semiconductor/high-k interface leading to less improvement of effective mobility and SS. If the temperature is above 250 • C or annealing time longer than 30 min it instead leads to a degraded interface, probably originating from diffusion at the semiconductor/high-k interface and/or crystallization of the HfO 2 leading to degraded device performance. The peak performance is obtained after AHA at 250 • C, which is 100 • C lower than if RTP annealing is performed. Thus, the use of AHA indeed results in a significant reduction of the annealing temperature while maintaining comparable device performance. This in addition to the improved reliability makes AHA an interesting treatment for future III-V integration in Si CMOS BEOL.

Data availability statement
The data that support the findings of this study are openly available at the following URL/DOI: https://doi.org/10.5281/ zenodo.7590357 [18].