CMOS-compatible manufacturability of sub-15 nm Si/SiO₂/Si nanopillars containing single Si nanodots for single electron transistor applications

Driven by the tremendous broadening of mobile and 'Internet-of-Things' applications, the development of low-power logic and memory circuits remains a main task for the next generation of energy-efficient electronic devices [1, 2]. Structures based on spintronics [3], two-dimensional (2D) materials [4] and tunnelling field-effect transistors made of compound semiconductors [5, 6] are among the favoured approaches for future low-power circuits. With respect to classical Si-based complementary metal-oxide-semiconductor (CMOS) transistor technology, down-scaling of device dimensions is the key for further power reduction [7, 8]. Presently, lateral fin field-effect-transistors (FinFETs) in the sub-8 nm node represent state-of-the-art technology, whereas stacked FinFET, ribbon or vertical nanowire (NW) transistor architectures enable real 3D-integration in the foreseeable future [9]. In 2013, Larrieu and Han [10] presented a silicon vertical NW transistor with gate-all-around (GAA) configuration fabricated in standard CMOS technology. These transistors with NW diameters of 20–80 nm offer excellent parameters with an 'on/off' ratio > 10⁵ and a drain-source current of 10–100 nA [11, 12].

Another device type with extremely low energy dissipation is the dot-based single-electron transistor (SET) [13]. In this device, electrons tunnel from the drain to the source region via a quantum dot (QD). The blocking/non-blocking states of SET are controlled by the potential of the QD which can be tuned by a third electrode (gate) capacitively coupled to this dot [14]. Typically, SETs work only at cryogenic temperatures (<100 K) [15–17]. However, for many SET applications room-temperature (RT) operation is mandatory which requires a QD size of only a few nanometres to fulfil the Coulomb blockade condition [14]. SET structures operating at RT has already been realized, mainly based on lateral Si NWs [18–20], nanocrystalline Si [21] or metallic nanodots [22]. Numerous SET applications were proposed making use of its high charge sensitivity and low power consumption, see review papers [23, 24] and references therein. Examples are electrometers, DC current or temperature standards, microwave or infrared sensors, non-volatile memories or programmable logic circuits.

SETs are often considered as 'beyond-CMOS' devices, particularly when metallic or III–V semiconductor QDs are used. The novel SET device architecture considered in this work promises RT operation, CMOS-compatible fabrication and high-density integration. This concept is based on a Si nanodot (ND) embedded in the oxide of a vertically stacked Si/SiO₂/Si nanopillar (NP). The capability for CMOS-compatible, monolithic integration of FETs and SETs is essential because SETs have intrinsic drawbacks, such as low gain, high output impedance or the disability to drive loads [24, 25]. Fortunately, SET and FET performances are complementary. Whereas SETs exhibit ultra-low power consumption, FETs offer advantages such as high speed, driving force, voltage gain and variable input impedance that compensate exactly for the SET limitations. As an example for an integrated SET/FET programmable logic device, logic functionality can be completely realized by the SET network by using QD based non-volatile memory structures, and only a limited number of FETs are required to drive the power-demanding components of the integrated circuit [26].

It has been proposed by Mahapatra and Ionescu [27] that hybrid SET/FET circuits with the FET operating at sub-threshold regime provide a way to preserve low power consumption. By on-chip SET/FET integration one can boost the Coulomb Blockade oscillation phenomenon of SET and the high drive current of FET. Thus, high performance and low energy dissipation are expected for such integrated SET/FET-CMOS architectures. They are able to address functionalities such as neuromorphic or multiple valued logic circuits which are very difficult to implement by classical FET-CMOS circuits alone [27]. Another application field is sensing, either as a single charge sensor for semiconductor-based quantum computing or as a biosensor system [28].

In this study, we describe a CMOS-compatible fabrication process to realize stacked sub-15 nm Si/SiO₂/Si NPs with embedded silicon (Si) NDs as key building blocks for SET fabrication. The envisaged SETs have a vertical transistor topology with GAA electrode, similar to vertical NW FETs, what entails for high-density and monolithic FET/SET integration capability. The process flow combines top-down technologies, such as NP fabrication by electron-beam lithography (EBL) and reactive ion etching (RIE), with the bottom-up approach of Si ND self-assembly. Single (or a few) ND(s) in an oxide with small tunnelling distances to adjacent source/drain electrodes form by phase separation of a strongly confined, metastable Si-rich oxide (SiO_x → SiO₂ + Si) and Ostwald ripening during subsequent annealing. The SiO_x (x < 2) is produced by ion-beam mixing of Si into the oxide from the two Si/SiO₂ interfaces, whereas the spatial confinement required for single Si ND formation is defined by the small oxide volume within the NP.

The paper is organized as follows: at first, physical process and device simulations are presented in order to derive the required dimensions for the NP/ND as well as the basic parameters for ion-beam mixing. Then, the technology for NP/ND fabrication is described in detail, and the realized structures with nanometre dimensions are characterized using state-of-the-art electron and ion microscopy. It is shown that the applied technology is able to realize stacked Si/SiO₂/Si NPs at diameters close to 10 nm with embedded single Si NDs of ⩽3 nm size, what will be suitable for SET operation at RT. For structures of only a few nanometres, variability of critical dimensions (CDs) represents a relevant device reliability aspect [29]. Thus, the impact of tunnelling distance differences or the variation of ND size and its position in the oxide disc on the performance of SETs is discussed in a separate section.

The integration of the NP/ND structures into the complex technology of SET/FET circuit fabrication is published in a separate paper [30]. The technologies introduced in both publications offer a unique path for the manufacturability of RT operating SETs and integrated SET/FET circuits.

Figure 1 shows the basic scheme of a GAA NP SET. The QD, realized by the silicon ND, is separated by two symmetric tunnel junctions from the adjacent drain/source regions. The tunnelling current I_D is a function of the drain-source voltage V_D and the widths of the tunnelling barriers, while the 'on/off' state of the transistor is controlled by the potential V_G of the outer circular gate electrode surrounding the ND region at the NP rim. The silicon ND size and tunnelling distances must be sufficiently small to drive a controllable and stable electron current at low voltages V_D and V_G.

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To enable RT operation of the SET, the Coulomb blockade [14] condition must be fulfilled, which means that the silicon ND electrostatic energy E_C considerably exceeds the thermal energy kT to suppress the influence of thermal fluctuations. The electrostatic energy of the dot is calculated as

$$\begin{equation}{E_C} = \frac{{{e^2}}}{{2{C_D}}} = \frac{{{e^2}}}{{4\pi {\varepsilon _0}{\varepsilon _{{\text{Si}}}}{d_{{\text{ND}}}}}}\end{equation} \tag{ 1 }$$

where C_D and d_ND denote the self-capacitance and diameter of the spherical Si ND, respectively; ₀ is the permittivity, _Si = 11.8 (Si dielectric number); e, k are the elementary charge and Boltzmann constant, respectively. According to equation (1), a ND diameter of d_ND ⩽ 3.5 nm is required to realize a barrier exceeding the common precondition E_c > 10 kT ≈ 0.3 eV for RT operation of a quantum device.

Based on the nextnano++ program package [31], a simulation framework was developed to calculate the current–voltage (I–V) characteristics of such a stacked NP SET (as shown in figure 2) and to derive the main geometrical constraints as targeted values for NP/ND fabrication [32].

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Two results of these simulations are illustrated in figures 3(a) and (b) which show the dependencies of the drain-source current I_D on the tunnel oxide thickness d_T and the NP diameter d_NP, respectively. The current oscillations are a direct consequence of the Coulomb blockade for an increasing number of charges in the Si ND.

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From these simulations it became clear that

• Tunnelling thicknesses close to 1 nm (d_T ⩽ 1.2 nm) on both sides are necessary to achieve a tunnelling current I_D of at least a few pA.
• The diameter of the NP should be d_NP ⩽ 12 nm to enable a tunnelling current I_D of about 1 pA at a reasonable gate-source voltage V_G.

Under these conditions, a thickness of d_ox ⩽ 5.5 nm was targeted for the oxide sandwiched between the Si source and drain electrodes. The outer oxide isolates the pillar from the gate electrode, its thickness should be 3 nm ⩽ d_SO ⩽ 5 nm to avoid gate-drain and gate-source short circuits for gate voltages V_G up to 3 V.

The Si ND represents a QD that is characterized by energy-level-splitting in the conductance band. The discretization of the energy levels is determined by

$$\begin{align}\Delta {E_{Q,n}} = \frac{{{\hbar ^2}{\pi ^2}{n^2}}}{{2{m^*}d_{{\text{ND}}}^2}}\end{align} \tag{ 2 }$$

where n ⩾ 1 is the ordering number of the discrete level, m* the Si effective carrier mass, T the temperature; $\hbar = h/2\pi$ the reduced Planck constant. To maintain the equidistant Coulomb oscillations as shown in figure 3, the energy difference between the ground state and the first level should exceed the value of the Coulomb blockade, that is

$$\begin{align}\Delta {E_{Q,2}} - \Delta {E_{Q,1}} > {\text{ }}{E_C} > 10{\text{kT}}.\end{align} \tag{ 3 }$$

For Si NDs of approximately 3 nm in diameter (and even more for smaller ones), this condition is fulfilled as the bandgap widening for such QDs exceeds 0.5 eV [33].

In order to address the SET limitations, mainly the low current level (see figure 3(a)), its co-integration with a FET is favourable. The I–V characteristics of a hybrid SET/FET circuit (see figure 4(a)) proposed by [27] was simulated for a ND-SET/vNW-based FET configuration using BSIM-CMG models [34].

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As shown in figure 4(b), the SET current is significantly amplified by six orders of magnitude by the FET operating at sub-threshold level.

The simulation tools and models also allow to study the influence of variations of CDs, such as tunnelling distances, the ND size or its lateral position, on the device characteristics. Results of such simulations were published in [35, 36]; some aspects with respect to experimentally observed deviations to targeted values are separately discussed in section 5.5 of this paper.

The formation of Si NDs in Si rich oxides by thermally stimulated phase separation and Ostwald ripening has been demonstrated in numerous studies, for example [37–40] and references therein, a recent review paper [41] or also summarized in chapters 9–13 of the textbook 'Silicon Nanocrystals' [42] edited by Pavesi and Turan. The new aspect addressed in this work is to realize a single, self-assembled Si ND or only very few ones in the oxide of a vertically stacked Si/SiO₂/Si pillar for SET applications. The basic approach to achieve this goal is to limit the volume of phase separation to a few hundreds of cubic nanometres, which corresponds well with the targeted volume of the oxide disc within the NP, as derived in the previous section.

Several techniques, including reactive magnetron sputtering, chemical vapour deposition and SiO evaporation, can be used to fabricate thin Si-rich oxide layers as matrices for subsequent phase separation. Here, we apply the method of ion-beam mixing at Si/SiO₂ interfaces [43, 44] to enrich the initial stoichiometric SiO₂ with Si. The excess Si content and its profile could be easily controlled by varying the irradiation fluence. Mixing of the Si/SiO₂/Si stack is carried out by using chemically neutral Si ions at sufficiently high energy so that the ion penetration depth significantly exceeds the stack thickness.

For the synthesis of Si NDs within the oxide of a NP, two basic scenarios were considered. One option is to perform ion-beam mixing and subsequent annealing in pre-structured NPs. However, recent experiments revealed that RT ion irradiation at the required fluence deteriorates the stacked NPs by amorphization, leading to substantial NP shape changes during ion irradiation due to viscous flow of silicon [45]. This effect can be suppressed by performing ion irradiation at elevated temperatures (>400 °C), which preserves the crystalline morphology of the Si regions in the stacked NP. We discarded this option because most implantation tools in standard wafer process lines do not allow ion irradiation at temperatures above 400 °C. Alternatively, we decided to apply ion-beam mixing to a planar layer stack prior to electron-beam patterning and pillar etching. In this case, the volume of the mixed oxide disc is determined by the NP dimension after etching. Phase separation and ND formation are accomplished during subsequent annealing at temperatures up to 1100 °C which is viable owing to the high thermal and mechanical stability of the NPs.

The modelling of this process sequence is accomplished in two steps, with dynamic collisional computer simulations of ion-induced atomic mixing using TRIDYN [46, 47] and subsequent kinetic Monte Carlo (kMC) simulations of the phase separation and ND formation. The accumulation of Si in the oxide interlayer during ion-beam mixing is illustrated in figure 5 which shows the depth profiles of excess Si in the oxide that develops under 50 keV Si⁺ irradiation. The Si excess atomic fraction is defined as [48]

$$\begin{align}q_{{\text{Si}}}^{{\text{exc}}}(x) = \frac{{{n_{{\text{tot }}}\left( x \right)}}}{{2n_{{\text{Si}}}^0}} \cdot \left( {3{q_{{\text{Si}}}}\left( x \right) - 1} \right)\end{align} \tag{ 4 }$$

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where n_tot(x), n_Si, q_Si(x) denote the total (Si + O) atomic density, atomic density of crystalline Si (= 5 × 10²² at/cm³), and Si atomic fraction, respectively. For SiO₂, SiO and pure Si, $q_{{\text{Si}}}^{{\text{exc}}}$ amount to 0, 0.43 and 1, respectively. The profiles demonstrate significant ion-induced atomic mixing in the regions of both interfaces. The almost symmetric excess Si profiles in the oxide indicate a similar mixing efficiency at both interfaces, which is assured by the choice of the ion energy. In addition, there is a minor shift in the profile towards the surface which increases with increasing fluence. This is attributed to the deposition of implanted Si ions behind the oxide interlayer. (Note that the depth scales of figure 5 have already been corrected for surface erosion due to sputtering.)

The excess Si in the oxide continuously increases with the irradiation fluence, converting the initial SiO₂ into an SiO_x layer with a depth-dependent x value. As concluded from the subsequent kMC simulations, a stoichiometry of x ≈ 1 at the centre of the oxide layer optimizes the formation of well-separated Si NDs. This is achieved for a fluence of ∼1 × 10¹⁶ cm⁻² which is a reasonable value with respect to the sputter loss of the upper Si layer (∼1 nm/10¹⁶ ions × cm⁻²) as well as the irradiation time (a few minutes). The maximum excess Si close to the oxide centre is beneficial for phase separation and Si ND formation. However, a recent study by Prüfer et al [49] showed that TRIDYN overestimates the interface broadening of the mixed Si profile, in particular for higher implantation fluences. This deviation is attributed to the neglect of chemical driving forces in connection with thermal-spike-induced diffusion during ion irradiation, which tends to reconstitute the Si/SiO₂ interfaces. Accordingly, it is proposed to increase the fluence of the TRIDYN simulation by a scaling factor of ∼1.5 in the fluence range of interest [49]. Thus, an irradiation fluence of ∼1.5 × 10¹⁶ cm⁻² appears to be appropriate for our purposes.

The excess Si depth profiles in the oxide (figure 5) were used as inputs for 3D kinetic Monte-Carlo simulations of phase separation and Si ND formation [50, 51]. Figure 6 shows a set of kMC simulations of Si ND formation after thermally driven SiO_x → Si + SiO₂ phase separation for stacked NPs of different diameters. It is evident that the number of precipitated Si NDs successively decreases towards lower pillar diameters. A single Si ND is formed for a strongly confined SiO_x volume of approximately 500 nm³. For an oxide layer of 6 nm thickness, this volume corresponds to a NP diameter of about 10 nm.

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The vertical ND self-alignment almost at the oxide centre results from the symmetrical mixing effect at the upper and lower Si/SiO₂ interfaces. The final Si NDs form with a size of 2–3 nm which agrees well with the preconditions for quantum confinement and RT operation of the SET, as set out in section 2. The very low diffusion coefficient of Si or SiO in the oxide enables small tunnelling distances and a sufficiently large thermal budget process window for the stable existence of Si NDs (see sections 5.1 and 5.5). The kMC simulations also reveal the recovery of smooth Si/SiO₂ interfaces and a remarkable rounding of Si/SiO₂ rims. The latter effect improves the electrostatic control of the ND and increases the drain-gate or source-gate breakdown stability.

4.1. Process flow of NP/ND fabrication

Industrial, silicon wafer-level processes were employed on a front-end 200 mm CMOS line to ensure a high throughput and reproducibility of NP fabrication. The basic process flow is illustrated in figure 7 and mainly consists of the preparation of the planar layer stack, ion-beam mixing for SiO_x formation, EBL for sub-100 nm patterning, multistep RIE using a hard mask for pillar fabrication and thermal processing for SiO_x phase separation and Si ND formation. The final plasma oxidation step was used for NP shrinkage and gate oxide growth.

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For the experiments described here, mainly low-resistivity, n-type bulk-Si material was used. In parallel silicon-on-insulator (SOI) wafers with 200 nm top-Si and 400 nm buried oxide (BOX) necessary for the fabrication of integrated SET/FET devices were processed, too. The thickness of the thermal oxide was varied between 5 nm and 8 nm to optimize the Si ND size and tunnelling distances. As the top layer, undoped amorphous Si of 30 nm thickness was deposited by low-pressure chemical vapour deposition, and subsequently doped by low-energy phosphorous implantation. For ion-beam mixing, RT irradiations were performed using 50 keV Si⁺ ions at a fluence of 1.5 × 10¹⁶ cm⁻² (i.e. with parameters as described in section 3) and at an angle of incidence of 7° with respect to the surface normal. For the subsequent dry RIE step the SOC/SiARC ⁵ layer stack acted as a hard mask. Isotropic resist trimming was additionally applied before etching to reduce the NP diameter. Details of this lithography/etching scheme were recently published by Pourteau et al [52]. The subsequent annealing step was performed using a rapid thermal processing (RTP) tool. A two-step sequence at 800 °C for 10 s followed by 1050 °C for 60 s or 120 s was applied. The intermediate annealing step at 800 °C was included to transform the amorphous top Si cap into poly-crystalline Si and to recrystallize the amorphous region in the bulk Si caused by ion-beam mixing. Generally, the heating rate was fixed at 25 K s⁻¹, whereas the temperature profile during cooling followed an exponential decay as the wafers were not actively cooled. The necessity and details of the final plasma oxidation step are described in section 5.3.

To enable a systematic study of ND/NP fabrication and the reliability of lithography and etching steps, NPs of various size and with different distances were arranged in pillar arrays of 5 × 5 µm² size each. Stand-alone NPs—so called isolated pillars—were processed in parallel. The nominal NP diameter (denoted as CD) was varied between 30 nm and 100 nm, whereas inter-pillar pitch distances between 60 nm and 1 µm (i.e. from 2× CD to 10× CD) were chosen. Several hundreds of such pillar arrays are regularly distributed across a wafer, enabling conclusions about the scalability of the technology and statistical variation of the CDs. More information regarding the lithography wafer layout is provided in the supplemental material S1 of this paper.

4.2. Structural characterization

5.1. Ion-beam mixing and SiO_x phase separation

As derived in section 2, high-dose Si⁺ ion irradiation with a fluence of 1.5 × 10¹⁶ cm⁻² is required to transform the initial SiO₂ layer within the stack into SiO_x (x ≈ 1). This fluence leads to the amorphization of the Si bulk below the oxide up to a depth of about 120 nm. Generally, this amorphization is uncritical as the substrate fully recrystallizes by epitaxial regrowth during subsequent RTP. When using SOI wafers, the top Si thickness must be larger than the amorphization depth to maintain a mono-crystalline seeding layer above the BOX for solid phase epitaxial regrowth.

An important issue for SET functionality is the quality of SiO₂/Si interfaces which is influenced by the ion-beam mixing process. Figures 8(a)–(c) depicts a sequence of EFTEM micrographs showing the Si/oxide interfaces before and after irradiation and after annealing, respectively. As expected from the TRIDYN simulations (see figure 5), ion irradiation leads to blurring of the Si/oxide interfaces and an Si accumulation in the oxide from both sides. This is caused by the continuous mixing of Si into the oxide and oxygen into the adjacent Si regions. The subsequent annealing step (T > 1000 °C) provokes Si and SiO diffusion as well as phase separation, leading to Si ND formation and the recovery of Si/SiO₂ interfaces [54, 55]. The relative Si depth profiles derived from line-scans of the Si-plasmon-loss-filtered TEM micrographs are shown in figure 8(d). They clearly reveal the mixing effect: the Si content in the oxide after mixing is significantly increased, and the still existing Si excess after annealing is caused by the presence of Si NDs which is indicated by the slight profile bump in the centre of the oxide. NDs are also seen as bright spots in figure 8(c). The strong recovery of the Si profile after annealing indicates that most of the excess Si condensates at Si/SiO₂ interfaces during thermal treatment. The almost identical profile slopes of the as-deposited and annealed samples in figure 7(d) confirm the reconstitution of smooth interfaces after annealing.

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The parameters for the annealing step, required for phase separation and Si ND growth were investigated in detail by Xu et al [56] defining a thermal budget parameter TB

$$\begin{equation}{\text{TB}} = {D_0}{\mathop \int \nolimits }\exp \left( { - \frac{{{E_a}}}{{kT\left( t \right)}}} \right){\text{d}}t \cong {D_0}t \cdot {\text{exp}}\left( { - \frac{{{E_a}}}{{kT}}} \right)\end{equation} \tag{ 5 }$$

where D₀ and E_a denote the diffusion coefficient and activation energy of the relevant SiO diffusion in SiO₂, respectively (D₀ = 4 × 10⁴ cm² s⁻¹ and E_a = 6.2 eV) [54]. In the case of a negligible thermal budget during heating/cooling this equation has a simple exponential form, as shown on the right side of equation (5). Xu et al [56] determined a suitable process window of TB = (0.7–2.1) × 10⁻¹⁷ cm² for the generation of Si NDs with a size of 2–3 nm. Although this study was performed for an unpatterned 2D layer stack, this TB value should also be a reasonable choice for the case of phase separation within the stacked NP considered here. The reason is the distinctly smaller distance of diffusing excess Si (or SiO) for condensation at both Si/SiO₂ interfaces compared to the distance to the outer pillar rim. For the excess Si fraction close to the rim the situation might be different, but this finally only favours the formation of NDs in the NP centre which is a beneficial effect for single Si ND formation. Consequently, for the experiments described in this paper, RTP was usually carried out at 1050 °C and with times of 60 s or 120 s corresponding to TB = 0.6 × 10⁻¹⁷ cm² or 1.1 × 10⁻¹⁷ cm², respectively.

A critical issue is the proper choice of the annealing ambient. After annealing in pure nitrogen (grade 6.0) at 1050 °C, pitting at the pillar walls and pillar cap as well as at the bottom Si substrate bottom besides the NPs was observed (figure 9). These defects were not present directly after the NP etching before annealing. As a result of detailed investigations, excluding reasons such as thermally activated etching by halogen residuals from RIE, these defects are most probably caused by the formation of volatile SiO(g) from traces of humidity or oxygen in the annealing environment [57]. Options to circumvent this artefact are to use either an mixed N₂/O₂ atmosphere (oxygen content 1–2 vol.%) to favour sacrificial SiO₂ layer formation or to protect the NP by a thin SiO₂ film deposited prior to the RTP anneal, e.g. by low-temperature plasma-enhanced atomic-layer-deposition. In the latter case, post-annealing can be carried out in pure N₂ atmosphere.

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Both methods were successfully applied, yielding almost defect-free NP arrays, as shown in figure 10 for the case of annealing in N₂/O₂ mixed ambient. The oxide grown around the pillar with a thickness of (3 ± 1) nm (see figure 10(c)) is acceptable for further processing. The use of N₂/1%O₂ annealing is not detrimental to the formation of Si NDs in the centre of the oxide, as proven by EFTEM imaging (see figure 10(b)).

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A second advantage of using mixed N₂/O₂ atmosphere for RTP is the prevention of silicon-oxynitride formation at the outer Si NP rim which was confirmed by analytical TEM ⁶ after annealing at 1050 °C in pure N₂. The Si_x O_y N_z films can only be removed by plasma or RIE dry etching with limited selectivity for other materials which is a critical issue for subsequent SET gate oxide formation and drain metallization.

5.2. NP morphology control

The device simulations in section 2 show that SET operation requires a final NP diameter of <12 nm. Therefore, NP arrays of various dimensions were investigated to determine the limits of the lithography/etching/annealing processes applied for the fabrication of defect-free NPs. Pillar arrays with CD = 30 nm and 60–300 nm pitch were of particular interest to elucidate pillar topology and the Si ND formation within the smallest NPs.

A first observation revealed that the NP diameter after RIE became a function of the NP pitch, as shown in figure 11(a). Note that resist trimming generally led to NP diameters smaller than the EBL designed CD values [52]. Starting from an NP diameter of about 28 nm, obtained for an array pitch of 60 nm, it shrinks with increasing pitch down to a diameter of 17 nm. Above 200 nm pitch, the shrinkage saturation represents the situation of stand-alone pillars. This shrinkage effect was caused by the simplified lithographic workflow at which electron-beam proximity correction was not applied before exposure of negative EBL resist. This results in overexposed patterns at small pitch values due to locally scattered electrons. As a second effect, a reduction in the oxide layer thickness for decreasing NP diameters was observed (figure 11(b)). The thickness reduction can be explained by the charging of the NP cap during the final phase of pillar etching, leaving the upper Si-cap electrically isolated. This charging leads to local breakdowns and SiO emanation at the rim of the oxide [58]. The easiest option to compensate for this oxide shrinkage is to increase the initial oxide thickness within the stack. Another technical option is the isolation of the entire wafer during RIE.

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The investigations described so far show that sub-30 nm NPs can be realized by direct EBL and RIE etching. However, the yield of defect-free pillars rapidly decreased to <50% for stand-alone NPs less than 20 nm in diameter. Main artefacts are the removal of the top Si cap, NP bending, or a strong trapezoidal shape of the stacked pillars.

5.3. NP shrinkage technology

As a consequence of the yield drop of sub-20 nm diameter NPs after RIE, an additional process step is necessary to shrink the NP size from ∼20 nm to the targeted diameter of <12 nm. A common technique for reducing the size of Si nanostructures is sacrificial oxidation [59, 60]. Usually by thermal oxidation, the surface of the Si nanostructure is oxidized with consumes a Si layer of d_Si = 0.44⋅d_ox thickness by conversion into SiO₂. This oxide layer can be selectively removed by hydrofluoric acid (HF), resulting in a reduction of the initial nanostructure dimension. Accordingly, the NP diameter reduction was tested using rapid thermal oxidation at temperatures between 850 °C and 1050 °C. However, a closer look at NPs with an initial diameter of <20 nm by EFTEM showed the dissolution of the existing Si NDs during this treatment, which is attributed to Si ND oxidation ⁷ . This can be avoided using the microwave-based plasma oxidation technique operating at temperatures <400 °C [61, 62]. Plasma oxidation provides oxides of up to ∼8 nm in thickness and high electrical quality [63, 64] at reasonable oxidation times of some minutes. In collaboration with the company HQ Dielectrics GmbH (HQ-D), experiments were carried out with the HQ-D Hyperion^LT tool [65] (suitable for processing up to ⊘ 300 mm wafers) to qualify the plasma process for the oxidation of NPs. The oxidation was performed in a microwave plasma (2.45 GHz) using O₂/He gas ratio of 85/15 vol.%, a working pressure of about 35 Pa and a power density of 2 W cm⁻².

Figure 12 shows the uniform oxidation of NPs and the preservation of the Si NDs after plasma oxidation. Remarkably, the thickness of the intermediate oxide layer in the Si/SiO₂/Si sandwich did not change. Limiting the processing temperature to <350 °C and staying within the linear oxidation regime, an oxide layer up to 6 nm thickness around the NP can be realized. This corresponds to an NP diameter shrinkage of approximately 5 nm per oxidation cycle. As the procedure can be repeated after removing the oxide by HF, NPs with a final diameter of <12 nm can be obtained by single or multiple plasma oxidation, depending on the initial NP diameter. Plasma oxidation technology provides another advantage: it can also be used to grow the gate oxide required for a GAA SET (see figures 2 and 7). A breakdown field >10 MV cm⁻¹ was measured at planar MOS structures for a gate oxide of 3 nm thickness produced by plasma oxidation.

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5.4. Towards a single Si ND

Figure 13 depicts a sequence of EFTEM images of isolated NPs with diameters varying between 35 nm and 18 nm, which were fabricated from the same layer stack of Si (30 nm)/SiO₂ (6 nm)/Si under identical ion-beam mixing, pillar etching and annealing conditions. The corresponding NP/ND features are summarized in table 1.

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Table 1. Values for the effective NP diameter d_NP, the oxide thickness d_ox and number of NDs in the pillars of figure 13 including also the cases IP45 and IP35 not shown there.

Parameter	Unit	IP50	IP45	IP40	IP35	IP30	IP30,oe
dNP	nm	37,0	33,0	27,5	21,7	18,6	10,5
dox	nm	5,6	5,4	4,8	4,2	3,8	3,0
# NDs (min)		3–4	3	3	2	1–2	0
Figure 11		(a), (d)		(b), (e)		(d), (f)	(g)

The number of Si NDs decreases with decreasing NP diameter, which is in close agreement with kMC simulations (see figure 6). In most pillars Si precipitates could be detected, except for an oxide thickness of ⩽3 nm. In this case the oxide is too thin to generate a Si ND of 2–3 nm as it immediately dissolves by de-wetting if touching the Si/SiO₂ interface.

Considering all aspects described before, we successfully produced stacked Si/SiO₂/Si NPs <12 nm in diameter with a single Si ND embedded in the oxide. This is illustrated in figure 14, which shows the EFTEM image of a NP of (11 ± 1) nm diameter with a single Si ND in the centre of the 3.7 nm thin SiO₂ disc formed by the self-organization and self-alignment mechanisms discussed in section 3. The ND has a diameter of 2.5 nm, the tunnelling widths on both sides are ⩽1.2 nm which suggests the ability for SET operation at RT.

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The widening of the oxide layer at the pillar rim is in agreement with the targeted layout and predictions by kMC simulations (see figure 6), which is advantageous for the reduction of the electrical field strength at the gate region. The results provide a proof of the manufacturability of vertically stacked NPs with embedded Si NDs and reveal that tunnelling distances close to 1 nm can be achieved.

5.5. Impact of NP/ND parameter variations

The NP/ND manufacturing process at sub-20 nm level described in previous sections and the statistical nature of SiO_x phase separation and Si ND formation results in some variations of the number of Si NDs as well as their size and lateral position in the oxide. Because of the strong geometrical constraints in the NP, these variations are generally small. It is outside the scope of this paper to discuss this matter in detail here (see [35, 36]), but let us briefly consider four experimentally observed situations with their consequences for SET or SET/FET operation and possible options to balance such variations.

• i.  
  The tunnelling transmission coefficient exponentially depends on the tunnelling distance. Thus, the most critical parameter is a very thin tunnel distance d_T of about 1 nm to achieve SET currents in the pA range (see figure 3). A variation of 10% in the tunnelling thickness will change the SET current by one order of magnitude [35]. For the hybride SET/FET circuit such a variation modifies the FET drain-source current by 20% [35, 36]. Any asymmetry of the upper/lower tunnelling distances will also considerably lower the SET current, as shown in figure 15(a). It is an essential issue to reduce and to unify the tunnelling distances. The very low diffusion coefficient of Si or SiO in SiO₂ (D ≈ 10⁻²¹ cm² s⁻¹ @ 1050 °C, see [54, 66]) implies a low diffusional screening length which is essential to enable tunnelling distances of about 1 nm or even slightly below (see figure 14). Thus, for a reduced oxide thickness one can expect a stronger localization of Si NDs with respect to both Si/SiO₂ interfaces and the unification of tunnelling distances.
• ii.  
  Simulations reveal that the ND shape (spherical, elliptical or elongated) has only a minor influence on the SET current as shown in figure 15(b). Flattened NDs, which is the most observed variation in the ND shape due the vertical confinement, requires lower V_G voltages. The SET current is almost constant as long as the tunnelling distances remain small enough and as long the conditions of equations (1) and (3) are still fulfilled.
• iii.  
  Furthermore, the lateral position of a single Si ND may deviate from the oxide centre. This increases the gate-dot capacitance C_GD and slightly lowers V_G which is beneficial for SET operation.
• iv.  
  It is also observed that more than one (typically 2–3) NDs form, particularly for larger NPs of >15 nm diameter. Within a small ensemble of NDs the tunnelling distances will not exactly be identical which has a strong impact on the SET current. Consequently, a self-selection of a specific ND characterized by the lowest tunnel barrier will happen. Moreover, there is also a technological way to favour a single, centred Si ND. It has been experimentally shown (see supplemental material S3) that annealing in a strongly diluted N₂/O₂ ambient dissolves Si NDs close to the rim of the NP while preserving near-centred NDs. Optimization of the oxygen content in the annealing ambient and the thermal budget will favour the formation of single NDs in cases that the NP dimension exceeds the 10 nm diameter level.

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In addition to process developments mentioned before, there is also another option to balance NP/ND topological variations. Both, SET and FET devices present a vertical topology with high integration capability. This entails the possibility to implement SET arrays connected in parallel that can suppress the variability impact [67]. However, further efforts are necessary to reduce the variations in order to achieve a higher technology readiness level.

This paper describes the CMOS-compatible fabrication of Si/SiO₂/Si NPs with embedded Si NDs suitable as key functional elements for a quantum-dot-based, GAA SET. Remarkably, all process steps were carried out using industrial equipment on ⊘ 200 mm bulk Si or SOI wafers, which confirms the manufacturability of the NP/ND structures in a complex wafer flow at a large wafer level.

To realize the ND/NP structures, a novel process flow that combines bottom-up and top-down technologies has been developed. Geometrical constraints and technological process parameters have been derived partly from predictive physical processes and device simulations, partly by using our experimental experience related to the formation of near-interface Si NDs. Finally, the reliable formation of Si NDs < 3 nm in the oxide of a stacked Si/SiO₂/Si NP ⩽ 12 nm in diameter with tunnelling distances of approximately 1 nm between the Si ND and the adjacent Si regions could be demonstrated. The impact of CD variations on the SET properties has been analysed by device simulations. Well defined, symmetric and ultra-thin tunnelling distances (∼1 nm) have the strongest influence on the SET current. Deviations in the shape of the NDs or their lateral position in the pillar are of less importance. Layout and technological options were discussed to suppress deviations for further improvements.

The work gained at physico-chemical understanding of the self-organization and patterning of nanostructures. This involves processes like ion-beam mixing, phase separation, reactive ion etching or plasma oxidation which might be helpful for future processing in nanoelectronics in general. In particular, the experimental verification of the predicted self-assembly of single Si NDs by phase separation within a confined SiO_x volume of <500 nm³ and the ability to locate such self-assembled QDs within a direct tunnelling distance to a Si electrode is highly relevant for nanoelectronics.

This study limits on the fabrication and structural characterization of NPs/NDs as key functional elements for the SET. In the Ions4SET project [68] further work was carried out to fabricate and electrically characterize NPs with Si NDs and single SETs [69]. Moreover, the entire integration schema for a hybrid SET/FET device was elaborated and tested [30]. An important issue was to verify that the NPs/NDs could withstand the thermal, mechanical and chemical stresses of a complex SET/FET fabrication flow. These investigations reveal that the NPs/NDs maintained their stability during the entire process, if they are embedded in sacrificial Si₃N₄ dielectrics and if the thermal budget during FET processing is limited to 900 °C/3 h, which are acceptable preconditions for state-of-the-art transistor technology.

This work received funding from the European Union's Horizon 2020 Research and Innovation Program under Grant Agreement No. 688072 (Project acronym: Ions4SET), which is gratefully acknowledged. The authors thank the Ions4SET Industry Endorsement Board for their continuous support during the project. In particular, the valuable inputs of K-H Stegemann (XFAB Dresden GmbH) was very helpful in developing the process flow for ND/NP fabrication and in solving several critical issues related to the processing of nanostructures. The authors thank W Lerch and J Niess from HQ Dielectrics GmbH (HQ-D) for providing and performing plasma oxidation at the HQD Hyperion^LT tool and their efforts to qualify this technique for the shrinkage of NPs. Numerous test preparations and extensive analytical work were carried out at the Ion Beam Center (IBC) and the Nanofabrication Facilities Rossendorf (NanoFaRo) at HZDR which is gratefully acknowledged.

The data that support the findings of this study are available upon reasonable request from the authors.

The authors declare no conflicts of interest. We certify that the paper is an original work, approved by all co-authors, and not published elsewhere. The study is in agreement with the 'DFG rules for good scientific practice' which complies ethics in science.