Superjunction MOSFET with a trench contact on partly relatively lightly doped P-pillar for excellent reverse recovery

The superjunction metal-oxide-semiconductor field-effect transistor (SJ-MOSFET) is an important switching device in power applications [1, 2]. By utilizing the multi-epi process [3] or trench filling process [4], charge balanced n/p-pillars can be formed in the SJ-MOSFET to obtain an excellent tradeoff between specific on-resistance (R_on,sp) and breakdown voltage (V_B) [5]. However, the poor reverse recovery performances, especially reverse recovery oscillations caused by the rapid depletion of the n/p-pillars, greatly restrict SJ-MOSFET's applications in many fields [6–10]. In order to suppress reverse recovery oscillations, the current recovery rate from the peak reverse current (I_rrm) to zero (di_r/dt) should be reduced, which can be realized by reducing the reverse recovery charge (Q_rr) and/or increasing the recovery time from the peak reverse current to zero (t_r). Some ways to reduce Q_rr of the SJ-MOSFET have been proposed. Carrier lifetime control technologies have been adopted, such as electron, proton, helium ion irradiation, and heavy metal doping [11, 12], but they also increase leakage current. Integrating the Schottky barrier diode (SBD) has been suggested to suppress the minority carrier injection of the body diode [13–16], but the integrated SBD also brings high leakage current. Introducing the MOS channel diode can reduce the hole injection by providing an electron reverse conduction path [17–20], but fabrication difficulties can be increased. Besides, some ways to increase t_r have been proposed, e.g. using a deep p-pillar embedding in the n⁺ substrate [21], applying the 3 C-SiC p-pillar [22], forming a high-resistance p-pillar by the multi-epi process [23], etc, where two ideas can be concluded, i.e. increasing storage carriers during t_r [21] and slowing down the extraction of holes in the p-pillar [22, 23].

For fabricating the SJ-MOSFET, the multi-epi process and trench filling process are two main technologies. Based on our previous work on the multi-epi SJ-MOSFET that is suitable for the multi-epi process [23], this paper proposes an SJ-MOSFET with a trench contact on partly relatively lightly doped p-pillar, which provides a new way to reduce Q_rr and increase reverse recovery softness to suppress reverse recovery oscillations for the SJ-MOSFET that is suitable for the trench filling process.

Figures 1(a) and (b) show schematic diagrams of the proposed SJ-MOSFET and the conventional SJ-MOSFET. In figure 1(a), the p-pillar is connected to source (S) via a trench contact on the p⁺ region. In figure 1(b), the p-pillar is connected to source (S) via a trench contact on the p-type field stop (p-fs) layer, where the p-fs layer has a higher doping than the p-pillar to avoid the punch-through breakdown of the p-pillar. The sidewall of the trench contact connects to the p⁺ region and p-base region. The ohmic contact on a p-type silicon can be achieved with a wide doping range of 10¹⁵ ∼ 10²¹ cm⁻³ [24]. As for the Schottky contact, the doping range is about 10¹⁵ ∼ 10¹⁷ cm⁻³ [25–27]. So, the contact on the p-base region and p-fs layer can be a Schottky contact or ohmic contact. In the proposed SJ-MOSFET, contact types of the trench contact only have a small influence on electrical characteristics, which will be discussed below. Furthermore, the proposed SJ-MOSFET has a partly relatively lightly doped p-pillar, where a relatively lightly doped p-pillar (p-pillar2) is embedded in the p-pillar1. Such a p-pillar structure can be formed by the double trench filling process with controlled epitaxial speeds of the bottom and the top of the trench [28].

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At reverse conduction state, since the p-fs layer is thin and has a relatively low doping dose compared to the p-base and p⁺ regions, electrons can easily inject from the n-pillar into the p-fs layer and be collected by the trench contact, which lowers the hole injection efficiency of the body diode to reduce Q_rr. During the reverse recovery stage of current recovering from the peak recovery current (I_rrm) to zero, majority carriers in the n/p-pillars are extracted out and the n/p-pillars deplete rapidly in both lateral and vertical directions [22]. As the reason that the p-pillar2 increases the resistance of the hole path, so the extraction of holes in the p-pillar (p-pillar1 and p-pillar2) can be slowed down, which increases the reverse recovery softness and suppresses reverse recovery oscillations.

In Sentaurus TCAD simulations, carrier lifetimes of 1 μs are set. Recombination models of SRH (DopingDependence) and Auger, mobility models of DopingDependent and HighFieldSaturation, impact ionization model of Avalanche (Lackner), bandgap narrowing model of Slotboom, tunneling models of eBarrierTunneling and hBarrierTunneling, and thermionic model are all considered. Table 1 lists key parameters of the conventional SJ-MOSFET and the proposed SJ-MOSFET, where symbols of parameters are given in figure 1. In order to avoid the punch-through of the p-fs layer, D_fs is set to be 1.7 × 10¹² cm⁻². The contact on the p-base region and p-fs layer is set as a Schottky contact with a barrier height of 0.5 eV.

Figure 2 shows forward conducting IVs of the conventional SJ-MOSFET, and two proposed SJ-MOSFETs with a trench Schottky contact and a trench ohmic contact. It can be found that there is almost no difference in the forward conducting IVs of the two proposed SJ-MOSFETs with a trench Schottky contact and with a trench ohmic contact. V_B of the proposed SJ-MOSFET (707 V) is a little lower than that of the conventional SJ-MOSFET (727 V). Furthermore, R_on,sp (at J_DS = 100 A cm⁻² and V_GS = 10 V) of the proposed SJ-MOSFET and the conventional SJ-MOSFET are both 12.5 mΩ cm².

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Figure 3(a) shows reverse conducting IVs and current flowlines distributions at J_SD = 100 A cm⁻² of the conventional SJ-MOSFET, and two proposed SJ-MOSFETs with a trench Schottky contact and a trench ohmic contact. Figure 3(b) shows hole distributions along x = 4 μm at 100 A cm⁻² of SJ-MOSFETs. It can be learned from current flowlines distributions that electron current is almost equal to hole current in the conventional SJ-MOSFET, but the conduction current is mainly composed of electron current in the proposed SJ-MOSFET with a trench Schottky contact. This means the hole injection efficiency of the source side of the proposed SJ-MOSFET with a trench Schottky contact is lower than the conventional SJ-MOSFET. Therefore, it can be found in figure 3(b) that the carrier-storage in the p-pillars of the proposed SJ-MOSFET is much lower than the conventional SJ-MOSFET, especially at the top part. Besides, it can be found in figure 3 that the reverse conducting IVs and carrier distributions of the two proposed SJ-MOSFETs with a trench Schottky contact and with a trench ohmic contact are very close. Note that, when electrons inject from the n-pillar into the p-fs layer, electrons flow into the trench contact by diffusing and the electron current mainly depends on the electron concentration gradient in the p-fs layer. Whether the trench contact type is Schottky or ohmic, electron concentrations at the trench contact of these two cases are both negligible. So the effects of the trench contact type on the body diode's electrical characteristics are small, which indicates that the process control of the contact type of the trench contact is not important in the proposed SJ-MOSFET. The small effect is mainly originated from that the built-in potential of the Schottky contact depletes a width of p-fs layer to slightly reduce the effective doping dose of the p-fs layer, which leads to a slightly reduction in carrier-storage in the p-pillars. So, in the discussions below, the proposed SJ-MOSFET with a trench Schottky contact is used to compare with the conventional SJ-MOSFET.

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Figure 4 shows reverse recovery waveforms of body diodes of SJ-MOSFETs under di/dt = 175 A μs⁻¹, where the proposed SJ-MOSFET with N_A1/N_A2= 1 is the case with uniform doped p-pillar. The devices under test have a same area of 0.2 cm². The Q_rr of the conventional SJ-MOSFET is 2.69 μC and reverse recovery oscillations are particularly significant. The Q_rr of the proposed SJ-MOSFET is 1.46 μC, which is reduced by 46%. The t_r (the time from t₂ to t₃) and di_r/dt of the conventional SJ-MOSFET are 6 ns and 4887 A μs⁻¹, respectively. The t_r and di_r/dt of the proposed SJ-MOSFET are 25 ns and 839 A μs⁻¹, respectively. It can be seen that reverse recovery oscillations can be significantly suppressed by using partly relatively lightly doped p-pillar to replace the uniform doped p-pillar.

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In order to understand the mechanism of suppressing reverse recovery oscillations for the proposed SJ-MOSFETs, figure 5 picks reverse recovery current waveforms of the proposed SJ-MOSFETs during t₂− t₃ from figure 4. Five points in time (t_a1− t_a5) for the case with N_A1/N_A2 = 1 and six points in time (t_b1− t_b6) for the case with N_A1/N_A2 = 3 are selected for comparison in figure 5.

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Figures 6(a) and (b) show distributions of hole density and current flowlines for the cases with N_A1/N_A2 = 1 and N_A1/N_A2 = 3 during t₂− t₃, respectively. In figure 6(a), the n-pillar and p-pillar of the conventional SJ-MOSFET begin to laterally deplete at t_a1, and then only very few holes store in the p-pillar at t_a3, which leads to a rapid current recovery during t_a3− t_a5. In the conventional SJ-MOSFET, extraction of holes in the p-pillar is almost unobstructed in the hole path. However, the hole path of the proposed SJ-MOSFET can be obstructed during t₂− t₃. For the case with N_A1/N_A2 = 3, the process of the reverse recovery stage of current recovering from I_rrm to zero can be divided into two stages. During the first stage (t_b1 − t_b3), part of holes stored in the p-pillar will be extracted quickly via both the p-pillar1 and p-pillar2. At t_b3, the p-pillar2 has been depleted due to its relatively low doping concentration, whereas a part of the p-pillar1 has not been almost depleted, storing some holes in the p-pillar1. So, during the second stage (t_b3 − t_b6), these holes must pass through the almost depleted p-pillar2, which is high-resistance or obstructed for the holes extraction. Therefore, the second state is slower than the first stage and has a positive impact on decreasing di_r/dt.

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Figure 7 shows effects of T_p2/T_p1 on V_B and di_r/dt for the proposed SJ-MOSFET, where the total impurities in the whole p-pillar (p-pillar1 and p-pillar2) and T_p1 are unchanged when values of T_p2/T_p1 and N_A1/N_A2 vary. As shown in figure 7(a), a high N_A1/N_A2 will significantly reduce V_B. When T_p2/T_p1 is about 0.75 (T_p2 = 26.5 μm), V_B drops to a minimum valve. Because the electric field distribution is the most uneven in this case due to the non-uniformity of impurity distribution in the whole p-pillar, and the electric field at the bottom of p-pillar1 is higher than other cases. When N_A1/N_A2 = 3 and T_p2/T_p1 ≈ 0.5 (T_p2 = 17.5 μm), V_B = 707 V is acceptable, which is a little lower than that of the conventional SJ-MOSFET (727 V). In figure 7(b), when T_p2/T_p1 increases from 0 to 0.6, di_r/dt decreases due to the increase of the resistance of p-pillar2. However, when T_p2/T_p1 increases from 0.6 to 1, the number of remaining holes which stored in the bottom part of the p-pillar1 at the second stage (t_b3− t_b6 in figure 6) is also reduced. Therefore the extraction of these holes at the second stage will become faster, which causes di_r/dt to increase. When T_p2/T_p1 is about 0.6 (T_p2 = 22 μm), the optimal trade-off between the resistance of p-pillar2 and the number of remaining holes can be obtained, which leads to the lowest di_r/dt. Considering both V_B and di_r/dt, it can be found by figure 7 that the optimal design can be obtained when T_p2/T_p1 = 0.5 ∼ 0.6 and N_A1/N_A2 = 3.

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Figure 8 shows effects of di/dt on di_r/dt and V_rrm. In figure 8(a), di_r/dt and di/dt show a positive correlation trend. When T_p2/T_p1 increases from 0 to 0.5, di_r/dt decreases by about 70% under di/dt = 175 A μs⁻¹. In figure 8(b), V_rrm at T_p2/T_p1 = 0.5 is significantly lower than the other two. When T_p2/T_p1 increases from 0 to 0.5, V_rrm decreases by 64 V under di/dt = 350 A μs⁻¹.

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Figure 9 shows effects of D_fs on V_B and J_leak (leakage current density at 600 V), where peak doping concentrations of p-fs layer (N_fs) corresponding to values of D_fs have been given out. In order to avoid the punch-through of the p-fs layer, D_fs ⩾ ε_s E/q should be satisfied, where E is the maximum electric field at the p-fs/p-pillar interface under V_B. Simulation results show that E is about 2.25 × 10⁵ V cm⁻¹. Thus, D_fs should be ⩾1.5 × 10¹² cm⁻². With the decrease of D_fs, V_B is not sensitive, but J_leak increases significantly. When D_fs > 1.5 × 10¹² cm⁻², the p-fs layer is not completely depleted under high blocking voltage. Holes generated in the depleted n-pillar and p-pillar can flow into the source via p-fs layer, p-base region and p⁺ region in turn. However, when D_fs ⩽ 1.5 × 10¹² cm⁻², the p-fs layer can be completely depleted, namely, the base region of the n-pillar/p-fs/Schottky contact transistor can be punched through, which results in the increase of J_leak.

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Figure 10 shows effects of D_fs and W_fs on Q_rr and peak reverse recovery voltage (V_rrm) for the two proposed SJ-MOSFETs with a trench Schottky contact and a trench ohmic contact. It can be found that the type of the trench contact has only a small effect on Q_rr and V_rrm, where the differences in Q_rr and V_rrm between two types of the trench contact are less than 5%. In figure 10(a), when D_fs decreases from 5 × 10¹² cm⁻² to 1.7 × 10¹² cm⁻², Q_rr is decreased by about 16% under di/dt = 175 and 280 A μs⁻¹, and V_rrm is decreased by about 24 V under di/dt = 280 A μs⁻¹. In figure 10(b), when W_fs is increased from 0.5–2.0 μm, the hole injection efficiency of the body diode can be reduced, which makes Q_rr be decreased by about 21% under di/dt = 175 and 280 A μs⁻¹, and makes V_rrm be decreased by about 35 V under di/dt = 280 A μs⁻¹. As for a half cell of the proposed SJ-MOSFET, the widths of the p⁺ region and the n⁺ region are both 0.5 μm when W_fs = 2.5 μm, which are relatively extreme values in actual fabrication process for power semiconductor devices. Besides, as mentioned above, D_fs should be ⩾1.5 ×10¹² cm⁻² to avoid the punch-through of the p-fs layer. Therefore, the device can obtain the optimum performance when D_fs = 1.5 × 10¹² cm⁻² and W_fs = 2.5 μm.

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Table 2 compares performances of the conventional SJ-MOSFET, the proposed SJ-MOSFET, and the SJ-MOSFETs in [16] and [23]. The figure of merit of V_B ²/R_on.sp [29] of the proposed SJ-MOSFET is a little lower than the SJ-MOSFET with nine multi-epi layers in [23] but a little higher than that of the SJ-MOSFET with a p-type Schottky contact and a n-type Schottky contact in [16] and the SJ-MOSFET with six multi-epi layers in [23]. Besides, V_RC (reverse conduction voltage at J_SD = 100 A cm⁻²) of these SJ-MOSFETs is similar. The SJ-MOSFETs in [16, 23] have a lower Q_rr than the proposed SJ-MOSFET. However, the MOS controlled diode in [23] needs extra fabrication steps, and the leakage current of the SJ-MOSFET in [16] is sensitive to temperature since its n-type Schottky contact is reverse biased in the blocking state. As for the proposed SJ-MOSFET, its structure is simpler than the SJ-MOSFET in [23], and its p-type Schottky contact is zero biased or slightly forward biased in the blocking state, which do not affect the leakage current.

Figure 11 shows feasible process flows of the proposed SJ-MOSFET with N_A1/N_A2 = 3 and T_p2 = 17.5 μm. The process simulation is as follows.

• (a)  
  Grow a 44 μm n-epi layer with doping concentration of 4 × 10¹⁵ cm⁻³ on an n⁺-sub.
• (b)  
  Form the p-base doping by boron implantation with dose of 4 × 10¹³ cm⁻² and energy of 100 keV, and diffuse under 1150 °C for 50 min. Then, form the p-pillar1 by etching 38 μm silicon and filling p-type silicon with doping concentration of 4.8 × 10¹⁵ cm⁻³, form the p-pillar2 by etching 20 μm silicon and filling p-type silicon with doping concentration of 1.6 × 10¹⁵ cm⁻³.
• (c)  
  Form the trench gate by etching trench, growing under 1000 °C for 75 min etching sacrifice oxide, growing 100 nm gate oxide (under 1000 °C for 125 min), filling polysilicon and etching polysilicon.
• (d)  
  Form the n⁺ doping by arisen implantation, and form the p⁺ doping by boron implantation.
• (e)  
  Form the p-fs layer by etching 2 μm silicon and vertical boron implantations with dose of 2 × 10¹² cm⁻² and energy of 20 keV.
• (f)  
  Finish metallization.

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An SJ-MOSFET with a trench contact on partly relatively lightly doped p-pillar is proposed and demonstrated by TCAD simulations. At reverse conduction state, the hole injection efficiency of the body diode can be lowered by employed trench contact, which helps to obtain an ultralow Q_rr. Besides, the resistance of partly relatively lightly doped p-pillar is larger than a uniformly doped p-pillar, which contributes to suppressing reverse recovery oscillations of the body diode. Simulation results show that Q_rr of the proposed SJ-MOSFET is 46% lower than the conventional SJ-MOSFET and reverse recovery oscillations can be significantly suppressed. In addition, there is a trade-off between V_B and di_r/dt and the optimal design can be obtained by adjusting values of T_p2 and N_A1/N_A2.

This work was supported in part by the National Natural Science Foundation of China under Grant 61804101, and in part by the Science and Technology Plan Project of Sichuan Province under Grant 2020YJ0005.

The data that support the findings of this study are available upon reasonable request from the authors.