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AlGaN/GaN HEMT channel temperature determination utilizing external heater

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Published 6 January 2020 © 2020 IOP Publishing Ltd
, , Citation M Florovič et al 2020 Semicond. Sci. Technol. 35 025006 DOI 10.1088/1361-6641/ab5d85

0268-1242/35/2/025006

Abstract

An improved method of average channel temperature and channel temperature profile determination is introduced in this paper applied to AlGaN/GaN HEMT using quasi-static IV characterization and external heater. Particular HEMT resistances and threshold voltage were experimentally determined at different ambient temperatures from TLM measurements, HEMT output and transfer IV characteristics. Negligible pinch-off area and leakage current dependence on drain voltage allows to obtain average temperature ∼77 °C for dissipated power 1.5 W using simple recurrent differential calculations. The HEMT channel temperature profile exhibiting maximum peripheral temperature ∼130 °C for dissipated power 1.5 W was simulated and verified utilizing the device electrical parameters variation.

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1. Introduction

The advanced GaN-based devices are promising to use in high temperature, frequency, power and microwave applications. However, the high potential of these devices is deteriorated by self-heating during the operation. This influences the electrical characteristics as well as device reliability [13], the temperature is a key factor here. High thermal conductance of particular materials, especially substrates, plays a significant role in the heat distribution. Power devices prepared on SiC and Si substrates exhibit better heat distribution than the ones grown on sapphire substrate [4].

Various experimental methods essential for complex characterization were developed to determine the channel temperature of power GaN-based the high electron mobility transistor (HEMT), e.g. Raman spectroscopy or interferometric mapping [57]. These techniques are widely applied though some measurements require advanced setup or assemblies to obtain accurate results. Thermal simulations explain thermally induced effects inside the structure in symbiosis with experimental data.

In this work an alternative method to [8] is described in the theoretical part and subsequently utilized for quasi-static IV characterization with the consecutive analysis to determine the HEMT channel temperature coming out from field-effect transistor (FET) behavioral model. The experimental part of this work is focused on AlGaN/GaN HEMT average temperature and thermal profile determination.

2. Theory

2.1. Differential FET behavioural model

Lateral FET consists of the gated core FET area, ungated and ohmic contact source/drain area as shown in figure 1. The total FET resistance is the sum of the core FET channel resistance RCH in the length dG, source to gate channel resistance RS in the length dS, drain to gate channel resistance RD in the length dD and source/drain ohmic contact resistances RCS, RCD in the transfer length dCS, dCD. In saturation regime pinch-off area of voltage drop VPO is formed nearby the drain-side gate edge at x ∈ (–dPO, 0) under the gate as well as at x ∈ (0, dPD) in the drain to gate gap. For quasi-static operation the difference between investigated FET gate voltage VGS, drain voltage VDS and core FET gate voltage VGO, drain voltage VDO, respectively, is given by the voltage drop caused by resistances RS, RD, RCS, RCD at drain current ID:

Equation (1)

Equation (2)

Figure 1.

Figure 1. A cross-sectional view of lateral FET. Reprinted from [8]. The origin is positioned in the middle of the drain-side gate edge.

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Core FET behavioural model [8] coming out from core FET functional approximation ${I}_{D}\sim f\left({V}_{GO}-{V}_{TH}\right)$ [9] results in core FET transconductance gGO = $d{I}_{D}/\left(d{V}_{GO}-d{V}_{TH}\right).$ Further substitution $d{I}_{A}=d{I}_{D}-{g}_{GO}\left(d{V}_{GO}-d{V}_{TH}\right)$ and ${R}_{SX}={R}_{S}+{R}_{CS},$ ${R}_{DX}={R}_{D}+{R}_{CD}$ leads to:

Equation (3)

Utilizing [8] dIA involves output conductance gDOdID/dVDO and thermal coefficient determined partially by threshold voltage VTH change, channel concentration n shift, carrier velocity v and carrier mobility μ = v/EX change caused by temperature T change having an impact on horizontal and vertical electric field (EX and EZ).

External heater utilization causes small temperature increase dT*(x) across the structure resulting in current change dID* and dIA* addicted to dRSX* and dVTH*:

Equation (4)

If both (3) and (4) are linearly independent and constant VGS, VGS* are supposed then (4) divided by (3) results in:

Equation (5)

Leakage current path allocation with respect to thermal gradient is requisite for proper calculations mentioned in [8].

2.2. Threshold voltage and source/drain/contact resistance determination

Temperature dependence of threshold voltage VTH and particular resistances RS, RD, RCS, RCD are crucial for FET channel temperature determination [10]. RS(0), RD(0), RCS(0), RCD(0) at low ID are lower than RS(ID), RD(ID), RCS(ID), RCD(ID) used in (1), (2) or (5) due to finite current saturation level [11]. Therefore particular correction factors rSRS(ID)/RS(0), rDRD(ID)/RD(0), rCSRCS(ID)/RCS(0), rCDRCD(ID)/RCD(0) at ID and T are requisite.

Relative small rS, rD, rCS, rCD change allows correction of RS, RD, RCS, RCD and dRS, dRD, dRCS, dRCD in simple multiplication way and usually rS ≈ rD, rCS ≈ rCD. In general RS(ID), RD(ID), RCS(ID), RCD(ID) and ID change cause relative resistance drop demonstrated for RS(ID):

Equation (6)

whereas rS depends on both ID and T and RS(0) on T only dRS(ID) is a linear combination of dID and dT.

Thermal dependence of VTH(0) and particular thermal coefficient kVTH(0) = dVTH(0)/dT are typically acquired from transfer low power IV characteristics [1214]. Under quasi-static condition dVTH(ID) = rVTHdVTH(0) is supposed ID dependent only using correction factor rVTH in core FET functional approximation ${I}_{D}\sim f\left({V}_{GO}-{V}_{TH}\right).$

Low power output IV characteristics at defined T allow to determine RS(0), RD(0), RCS(0), RCD(0) temperature dependencies and calculate particular thermal coefficients kRS(0) = dRS(0)/dT, kRD(0) = dRD(0)/dT, kRCS(0) = dRCS(0)/dT, kRCD(0) = dRCD(0)/dT [8]. In the case of channel thermal gradient those coefficients in symbiosis with correction factors determine the temperature dependence of channel resistance per length.

2.3. Average channel temperature evaluation

Under the quasi-static condition an average temperature TA along the whole channel is assumed. This hypothetic situation is demonstrated by infinite channel thermal conductance in the FET of width w and length dSdGdD. Therefore power density distribution in the channel plays no role. Differential FET behavioral model offers TA determination utilizing core FET thermal coefficient ${k}_{GC}=d{I}_{A}/d{T}_{A}$ and substitution $d{I}_{A}={k}_{GC}d{T}_{GO}+{g}_{DO}d{V}_{DO}.$ Dissipated power change $dP={V}_{DS}d{I}_{D}+{I}_{D}d{V}_{DS}$ results in dTA. Ambient temperature T0 increase dT0* caused by the external heater is set before measurement. Therefore active area temperature increase $d{T}_{A}^{* }\approx d{T}_{A}^{T}+d{T}_{A}^{P}$ at the device operation consists of the active area temperature change $d{T}_{A}^{T}$ at constant dissipated power and $d{T}_{A}^{P}$ caused by dissipated power difference $d{P}^{* }={V}_{DS}d{I}_{D}^{* }$ at constant VDS utilizing differential thermal resistance ${r}_{TH}\,\approx d{T}_{A}/dP\approx d{T}_{A}^{P}/dP* .$ Substitution ${k}_{A}=d{T}_{A}/d{T}_{A}^{* }$ yields:

Equation (7)

It is advisable to calculate dTA for each operating point, however $d{T}_{A}^{T}$ invoked by dT0* depends on TA. Therefore dTA caused by defined dP is possible to be obtained for varying T0 across the operating TA range assuming $d{T}_{A}^{T}$ ≈ dT0* [13].

Dissipated power change and thermal parameters are used in (7) whereas electrical parameters utilizing ID and TA dependence of RSX and VTH substituted in (5) lead to kA determination and the following solutions:

  • (1)  
    If $d{I}_{A}\approx {k}_{GC}d{T}_{A}$ and $d{I}_{A}^{* }\approx {k}_{GC}d{T}_{A}^{* }$ are thermally dependent only then ${k}_{A}=d{I}_{D}/d{I}_{D}^{* }$ in (7) yields:
    Equation (8)
    This approximation is suitable for small gDO when dPO and leakage current modulation with VDO are negligible. Moreover rS, rD, rCS, rCD, rVTH variation with ID and TA has no influence on (8) if low gDO condition is satisfied.
  • (2)  
    Thermal coefficients kRSX(ID) = rSkRS(0) + rCSkRCS(0), kRDX(ID) = rDkRD(0) + rCDkRCD(0) are possible to be obtained at operating ID and TA for relatively small rS, rD, rCS, rCD, rVTH variation. Considering gDO determined by pinch-off area and leakage current modulation caused by dVDO, substitution $a={I}_{D}{k}_{RSX}\left({I}_{D}\right)\,+{k}_{VTH}\left({I}_{D}\right)$ in (5) yields:

Equation (9)

Recurrent calculations coming out from (7) and (9) allow to obtain dTA incrementing TA and utilizing ${r}_{TH}\approx d{T}_{A}/dP$ from the previous operating point. Zero a and RSX causing zero dVGO result in solution similar to (8) where the term $d{I}_{D}/d{I}_{D}^{* }$ is replaced by $\left(d{I}_{D}-{g}_{DO}d{V}_{DO}\right)/d{I}_{D}^{* }.$ Substitution of dVDO by dVPO and dVDS using a differential form of (2) and leakage current are recommended to be incorporated in (9).

Negligible leakage current and dVTH ≪ dVPO yields dVPO ≈ dVDO and ${g}_{DO}={I}_{D}{\left({d}_{G}-{d}_{PO}\right)}^{-1}d{d}_{PO}/d{V}_{PO}$ where ddPO is dPO change with VPO whereas thermal dPO change is included in kGC [8]. If $d[{R}_{SX}({I}_{D}){I}_{D}]+d[{R}_{DX}({I}_{D}){I}_{D}]\langle \langle d{V}_{DS}$ then condition dVPO ≈ dVDO ≈ dVDS is satisfied. The condition ${r}_{TH}\approx \left({T}_{A}-{T}_{0}\right)/P\approx d{T}_{A}/dP$ for TA close to T0 is used for the temperature assumption in the linear regime area [8].

2.4. Channel temperature profile evaluation

Temperature profile evaluation for a device under quasi-static condition takes thermal gradient along the channel and temperature dependent thermal conductance into account. An uniform power dissipation density is assumed along z ∈ (dCH–hCH/2, dCH + hCH/2) using average channel depth dCH and vertical width hCH. Constant power density and temperature consideration along y ∈ (–w/2, +w/2) for x-position are requisite to define channel temperature T(x) and resistance element per length Ri(x) [8]. Power density per length Pi(x) = Ri(x)ID2IDEX(x) = IDdVCH(x)/dx where EX(x) and VCH(x) = EX(x)dx are the channel electric field and potential, respectively. In the ungated source and drain area EX(x) is distorted by Ri(x) modulation due to self-heating. Because of thermal gradient in the structure RS and RD at ID are declared in a way shown for RS:

Equation (10)

Equation (11)

Assuming small dCS and dCD both dRCS and dRCD at ID are defined in a way shown for dRCD:

Equation (12)

The core FET acts as the sum of elementary FETs of transconductance gGO(x) and length dx. Current continuity equation is partially satisfied for ID change caused by dVTH(x) and ddPO resulting in VCH(x) bending. Similarly kGC(x) is advised to be calculated at appropriate x ∈ (–dG, –dPO) using Poisson and current continuity equation and taking n, v, EX and EZ variation into account. Those calculations specific for each FET type allow to obtain core FET average dVTH. Although simple dVTH approximation is advised to be applied for short channel FET or for ${k}_{VTH}({I}_{D})\langle \langle {I}_{D}{k}_{RSX}({I}_{D}):$

Equation (13)

Temperature profile evaluation based on simple iterations is described in [8]. For simple temperature estimation in the saturation regime to avoid the iteration process total dissipated power increase $dP\approx d\left({V}_{PO}{I}_{D}\right)$ is supposed as uniform pinch-off area power dissipation contribution with respect to rising dPO and dPD. Pinch-off area dimensions dPO, dPD, hCH affect T(x) significantly inside this area whereas farther those parameters become less dominant.

Temperature change $d{T}_{A}^{T}\left(x\right)$ caused by dT0* such as $d{T}_{A}^{P}\left(x\right)$ invoked by uniform dissipated power change along the active area $d{P}^{* }={V}_{DS}d{I}_{D}^{* }$ are possible to be acquired by thermal simulations giving opportunity to assume dT*(x) in a simple way:

Equation (14)

Differential correction factor kT as ratio between simulated and calculated dT(x) gives opportunity to compare results obtained by simulations and calculated from experimentally acquired electrical FET attributes using differential FET behavioral model. Inaccurate assumption of particular thermal conductance, leakage current paths or power density cause kT deviation from one. In that case self-heating in entire channel area is advised to be considered or more proper electrical and thermal model to be employed. Differential equations are suitable to be replaced by difference formulas in numerical recurrent calculations.

Mentioned procedure is allowed to be used for for multi-gated FET as well. In the case of symmetric double gated structure drain current under each gate is ~ID/2. Self-heating plays role in a different non-uniform ID distribution for multi-gated FET, VCH(x) boundary conditions are useful here.

3. Experimental

3.1. Structure design and experimental setup

The investigated Al0.29Ga0.71N/GaN HEMT structure including 1.5 nm GaN/14.5 nm Al0.29Ga0.71N/50 nm undoped GaN/1650 nm GaN heterostructure was grown by MOVPE on 500 μm thick 4H-SiC substrate. The backside Au contact is soldered to 1 mm thick CuMo leadframe by 60 μm thick AuSn solder. Top ohmic drain/source and gate contacts were prepared by standard Au-based metallization. Horizontal view of investigated GTLM HEMT of w ≈ 125 μm, dG ≈ 1 μm, dS ≈ dD ≈ 5 μm and source/drain ohmic contact length ∼100 μm is shown in figure 2. The device is set in the package open from top, placed on the Al thermal chuck preserved at a constant temperature.

Figure 2.

Figure 2. Horizontal view of GTLM HEMT structure.

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The output and transfer IV characteristics were measured using semiconductor parameter analyzer Agilent 4155C and controlled thermal chuck. To obtain ID dependence zero gate voltage VGS was kept while drain voltage VDS varied from 0 up to 40 V. The parameters RS and VTH were acquired from the output and transfer IV characteristics measured in low power regime at temperature range 25 °C–120 °C, respectively. The device was recovered by one minute white LED illumination between measurements. 3D thermal finite element method (FEM) simulations of the device were performed by Synopsys TCAD Sentaurus coming out from thermal conductivity values shown in table 1 [15, 16].

Table 1.  Temperature dependence of thermal conductivity values utilized in 3D thermal FEM simulations.

Material Thermal conductivity (W m−1 K−1)
Au 310
AlGaN 40 × (T/298)−1.37
GaN (C doped) 190 × (T/298)−1.37
4H-SiC xy-axis 370 × (T/298)−1.5
  z-axis 430 × (T/298)−1.5
AuSn 57
CuMo 160

3.2. Average channel temperature and temperature profile determination

Linearization of RS(0) and VTH(0) temperature dependence depicted in figure 3 results in RiS(0) ≈ RiD(0) ≈ 4.14 Ω μm−1 at 25 °C, kRS(0) ≈ kRD(0) ≈ 29.4 mΩ K−1 μm−1, kVTH(0) ≈ 1.46 mV K−1 assuming rVTH ≈ 1. From transmission line measurements (TLM) correction coefficients rS ≈ rD ≈ 1+kDID, kD ≈ 6 A−1 for RiS, RiD at operating temperature and the current range was obtained using FEM simulations to eliminate self-heating part. Constant RCS ≈ RCD ≈1.2 Ω and rCS ≈ rCD ≈ 1 were verified. Transfer IV characteristics point on low leakage current.

Figure 3.

Figure 3. Measured RiS(0) and VTH temperature dependence.

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The measured ID dependence on VDS for VGS = 0 V at T0 = 25 °C and 35 °C exhibiting ΔT* = 10 °C and ΔID* are shown in figure 4. Additionally, nearly constant dPO/VPO ≈ 0.6 nm V−1 and dPD/VPO ≈ 3 nm V−1 were obtained from electro-thermal model. HEMT channel temperature profile shown in figure 5 was obtained using heat flow injector [8] in 3D thermal FEM simulations. Utilizing An ≈ 0.15 the relative saturation velocity change ${v}_{SAT}(T)/{v}_{SAT}\,=-T/[T+1700\,{\rm{K}}]$ was assumed.

Figure 4.

Figure 4. Output IV characteristics at VGS = 0 V for various temperature.

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Figure 5.

Figure 5. Channel temperature profile for various dissipated power.

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Simulated average temperature of the ungated source area, gate area and peripheral temperature of the pinch-off area exhibit linear dependence on dissipated power therefore the condition ${\rm{\Delta }}{T}_{A}^{T}\approx {\rm{\Delta }}{T}_{0}^{\ast }$ is satisfied reducing the external heater requirements on the small temperature increase only utilizing ΔT0* stabilization unaffected by ΔP and ΔP*.

An average temperature TA shown in figure 6 was calculated using (8) neglecting dPO. Considering dPO slightly higher TA was obtained solving (7) and (9) incorporating ${g}_{DO}={I}_{D}{\left({d}_{G}-{d}_{PO}\right)}^{-1}{\rm{\Delta }}{d}_{PO}/{\rm{\Delta }}{V}_{PO}$ and ${k}_{GC}\,=\left({I}_{D}/{v}_{SAT}\right)\left({\rm{\Delta }}{v}_{SAT}/{\rm{\Delta }}{T}_{A}\right)$ and. Calculated TA is close to simulated average temperature of ungated source area pointing on major thermal RS and minor VTH and vSAT change.

Figure 6.

Figure 6. Calculated TA and FEM simulated particular average temperature dependence on dissipated power P.

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Finite small ΔID* and ΔT0* caused by external heater takes effect on finite point differential analysis deviation resulting in correct TA determination.

Simulated channel temperature profile TSIM(x) at T0 and ${T}_{0}+{\rm{\Delta }}{T}_{0}^{* }$ for various dissipated power was obtained. In the case of temperature independent kVTH(0), kRS(0) ≈ kRD(0) and zero kRCS(0) ≈ kRCD(0) average temperature difference values of ungated source area ΔTARS and gated area ΔTACH are requisite for ΔRS determination and for simple ΔVTH approximation (13):

Equation (15)

Equation (16)

Utilization of (14), (15) and (16) leads to ΔT*ARS, ΔT*ACH and ΔT*(–dPO) acquisition. Polynomial approximation of ΔTARS, ΔTACH, ΔT(dPO) and ΔT*ARS, ΔT*ACH, ΔT*(–dPO) allows to acquire those parameters for each operating point.

Accurate kGC(x) and gDO(x) determination requires calculations based on Poisson and current continuity equation taking channel thermal gradient into account. To avoid this VCH(x) bending caused by ΔdPO and ${\rm{\Delta }}{V}_{DO}\approx {\rm{\Delta }}{V}_{PO}$ due to ${\rm{\Delta }}{V}_{DO}\gg {\rm{\Delta }}{V}_{TH}$ are supposed resulting in ${g}_{DO}\,={I}_{D}{\left({d}_{G}-{d}_{PO}\right)}^{-1}{\rm{\Delta }}{d}_{PO}/{\rm{\Delta }}{V}_{PO}.$ Because of negligible thermal 2DEG concentration change in AlGaN/GaN channel carrier velocity variation is the determining factor. For small VCH(x) thermal bending excluding VTH(x) thermal change current continuity equation results in ${\rm{\Delta }}{I}_{A}=qn\left(x\right){\rm{\Delta }}v\left(x\right)$ for x ∈ (–dG, –dPO), n(x) includes built-in such as EZ induced carrier concentration, gate boundaries exhibit ΔT(dPO) > ΔT(dG), EX(–dPO) ≫ EX(–dG), ΔT(dPO) > ΔT(dG). Assuming acceptable deviation in $n\left(-{d}_{PO}\right){\rm{\Delta }}{v}_{SAT}\left(-{d}_{PO}\right)\approx n\left(-{d}_{G}\right){E}_{X}\left(-{d}_{G}\right){\rm{\Delta }}\mu \left(-{d}_{G}\right)$ and ΔvSAT minor impact on ΔID in comparison with ΔRSX the formula ${k}_{GC}\left(-{d}_{PO}\right)=\left({I}_{D}/{v}_{SAT}\right)\left({\rm{\Delta }}{v}_{SAT}/{\rm{\Delta }}T\left(-{d}_{PO}\right)\right)$ is found to be sufficient approximation [8].

The ratio between calculated ΔT(x) and simulated ΔTSIM(x) temperature change ${k}_{T}={\rm{\Delta }}T\left(x\right)/{\rm{\Delta }}{T}_{SIM}\left(x\right)$ applied in (5) allows to compare simulated and calculated thermal profile in a multiplication way for ΔP applied for simulated ΔTARS, ΔTACH, ΔT(dPO). Values ΔT*ARS, ΔT**ACH, ΔT*(–dPO) are supposed as simulated using (14). Preliminarily calculated parameters RSX(ID), gDO, kRS(ID), kRD(ID), kVTH(ID), kGC(–dPO) for defined operating point and relatively small rS, rD, rVTH variation allow (5) to be transformed into the following difference equation to calculate kT:

Equation (17)

Channel temperature TSAT(x) obtained from simulations at saturation voltage is used as initial parameter for recurrent calculations. Therefore the resultant temperature in the saturation regime is yielded as:

Equation (18)

Obtained kT is shown in figure 7, particular simulated and calculated average temperature TARS, TACH such as T(−dPO) are compared in figure 8.

Figure 7.

Figure 7. Correction factor versus dissipated power.

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Figure 8.

Figure 8. Particular average temperature versus dissipated power (calculated and FEM simulated).

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Maximal peripheral temperature T ≈ 130 °C was reached for P = 1.5 W, however channel temperature is higher inside pinch-off area depending on dPO, dPD, and hCH. Although kT deviation is ∼12% a good correspondence between thermal simulations and calculations using (17) was achieved.

4. Conclusions

The aim of this work was to determine the average HEMT channel temperature and to verify the simulated channel profile utilizing an external heater together with electrical parameters acquired from quasi-static measurements. Lateral FET behavioral model was employed in recurrent differential calculations. Average channel temperature TA ≈ 77 °C was calculated for dissipated power P = 1.5 W in power Al0.29Ga0.71N/GaN HEMT structure grown on SiC substrate. Calculated TA close to the average temperature of ungated source area hints the significant thermal RS change. Moreover, simulated channel temperature profile exhibiting maximum peripheral temperature T ≈ 130 °C for dissipated power P = 1.5 W was verified using experimentally achieved electrical parameters.

Acknowledgments

The research leading to these results has received funding from the Electronic Component Systems for European Leadership Joint Undertaking under grant agreement No. 662322, project OSIRIS. This Joint Undertaking receives support from the European Union's Horizon 2020 research and innovation program, France, Norway, Slovakia and Sweden. This publication reflects only the author's view and the JU is not responsible for any use that may be made of the information it contains. The work was also supported by Grant VEGA 1/0739/16 through the Ministry of Education, Science, Research and Sport of Slovakia.

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10.1088/1361-6641/ab5d85