The implementation of thermal and UV nanoimprint lithography for selective area epitaxy

Semiconductor nanowires ( NWs ) in horizontal con ﬁ guration could provide a path for scalable NW-based devices. Bottom – up large-scale manufacturing of these nanostructures by selective area epitaxy ( SAE ) relies on precise nanopatterning of various shapes on the growth masks. Electron beam lithography offers an extraordinary accuracy suited for the purpose. However, this technique is not economically viable for large production as it has a low throughput and requires high investment and operational costs. Nanoimprint lithography ( NIL ) has the potential to reduce fabrication time and costs signi ﬁ cantly while requiring less sophisticated equipment. In this work, we utilize both thermal and UV NIL for patterning substrates for SAE, elucidating the advantages and disadvantages of each lithography technique. We demonstrate the epitaxial growth of Ge and GaAs NWs on these substrates, where we observe high-quality mono-crystalline structures. Even though both processes can produce small uniform structures suitable for SAE, our results show that UV NIL proves to be superior and enables reliable and ef ﬁ cient patterning of sub-100 nm mask features at the wafer scale. Supplementary material for this article is available online


Introduction
Lithography is an ever-changing technique that constitutes the backbone of the modern semiconductor industry. Carving out the desired pattern in a sensitive resist enables to devise semiconductor structures with defined morphology at known locations. There are several lithography techniques that enable patterning on a resist layer [1]. The most common ones are photolithography (PhL) and electron-beam lithography (EBL). In PhL, the entire substrate surface, or a small repeating subset of it, is patterned at once by illuminating it through a photomask. The wavelength of the light source determines the minimum size of the features or resolution, which is typically a few hundred nm for classical PhL [2], less than 100 nm for deep-UV lithography (DUV) [3], and 20-40 nm for extreme UV [4] and x-ray lithography [5]. On the other hand, EBL uses electrons instead of photons to achieve a higher resolution, down to 5 nm [6]. It is a versatile technique that allows the definition of arbitrary shapes. This direct writing technique has the disadvantage of long processing times; each pixel is exposed sequentially, so the exposure time is directly proportional to the density and resolution of the pattern. Nanoimprint lithography (NIL) steps into combine the advantages of both techniques: high resolution, short processing time, and applicability over large areas [7][8][9][10]. In NIL, an entire surface is patterned at once by pressing a nanostructured stamp onto a viscous resist layer without the need for expensive equipment. This renders NIL an attractive and cost-efficient patterning technique. After its first demonstration in 1995 [11], NIL has proven its ability to replicate patterns at extremely high resolution [12,13] and has since been extended to a wide range of materials and applications [9,[14][15][16][17][18]. NIL processed with thermoplastic polymers has been complemented by the development of processes with photo-curable resists (UV NIL) [19]. Especially in combination with flexible polymer molds [20] the patterning has become reliable and processing times have been significantly reduced. Today, NIL is an established technological process in the electronic and optoelectronic industry [21,22]. Figure 1 summarizes our comparison of how PhL, EBL, and NIL handle the typical requirements for lithography, i.e. resolution, scalability, cost, fabrication speed, and accessibility. NIL puts wafer-scale throughput efficiencies comparable to PhL within reach while achieving feature sizes comparable to EBL [12,13]. Even though wafer-scale processing with NIL is still challenging, its appeal lies in the fact that it does not necessarily require advanced equipment.
PhL, EBL, and NIL have all been used to pattern masks for top-down and bottom-up approaches. In this work, we will focus on NIL patterning of growth masks for positioncontrolled bottom-up epitaxy or so-called selective area epitaxy (SAE). SAE is known to produce high crystal-quality semiconductor structures with outstanding properties. It utilizes a patterned growth mask, which is typically an oxide. Within a certain growth parameter window, the mask layer impedes the deposition of the material, resulting in selective growth only inside the lithographically-patterned features where the substrate surface is exposed [24]. This growth technique allows one to grow ordered arrays of zero-dimensional quantum dots, one-dimensional free-standing and horizontal nanowires (NWs), two-dimensional nanofins, and thin films [25].
Previously, we demonstrated the growth of in-plane (horizontal) NWs, as well as NW junctions by SAE using EBL to define the nanoscale patterns [26][27][28][29]. Moreover, SAE of vertical NWs has been performed on the NIL patterned substrates [30][31][32]. In this study, we show how NIL can replace EBL for SAE substrate preparation with the intention of growing horizontal NWs and networks. Ideally, SAE features on the oxide mask should have sharp slit sidewalls, clean and uniform substrate surface, and a minimum number of defects. We first adopt a thermal NIL process that utilizes a simple press. Even though we show a proof-ofconcept pattern transfer, we are limited by our tool, which leads to uniformity and reproducibility problems. Its limitations prompted us to explore a UV NIL process. In this case, besides the stamp fabrication, no special equipment is used which makes this process even more appealing due to its simplicity. We evaluate and compare the potential of the two NIL processes focusing on their implementation, scalability, and reliability to produce defect-free patterns. After characterizing the quality of the patterned substrates, we demonstrate the growth of Ge and GaAs horizontal NWs and their networks using metal-organic vapor phase epitaxy (MOVPE) and assess their crystal quality. Based on our experimental results, we believe that NIL is a promising patterning platform for selective area growth reaching sub-100 nm features.

Experimental results
The NIL processes employed in this study are shown schematically in figure 2. Figure 2(a) displays the steps for thermal NIL. Briefly, thermal NIL is performed by pressing silicon stamps patterned by DUV lithography into heated PMMA resist. Imprinting time is at least 3 min, then we let the sample cool down below the glass transition temperature of the resist and remove the stamp from the substrate. Figure 2(b) shows the UV NIL procedure. We produce our polymer stamps from an EBL-patterned Si master template. To pattern our substrates, we use a photocurable resist and press the stamps by hand. The UV resist has a low viscosity at room temperature. Therefore, when brought into contact with the stamp, it conforms to features on the stamp due to capillary forces and does not require high imprinting pressures [33]. Once complete contact is made between the stamp and the substrate, we place the stack in a UV chamber for 10 s. After curing, the stamp is carefully removed from the sample. Following both imprinting techniques, the substrate fabrication steps are common, in which we transfer the imprinted pattern onto the oxide mask layer by dry and wet etching (figure 2(c)). Then, the samples are loaded into the MOVPE reactor, and the NWs are grown inside the patterned features. All experimental procedures and parameters are described in detail in the methods section.

Thermal NIL
With thermal-NIL, the rectangular features have been well transferred to the resist (figures S1 and S2). The nominal size of our imprinted structures varies between 200 and 300 nm, having pitches, i.e. feature-to-feature distances, ranging between 1 and 4 μm. As a rule of thumb, the feature size in NIL is limited by the stamp feature size since there is only a physical displacement of the resist with respect to applied pressure. Thus this process should allow for even smaller features with an appropriate stamp. In our case, the silicon stamp is produced by DUV lithography and dry etching (see figure S3). Due to the widening of the features towards the top, slit widths are wider than their nominally-defined size. There is a slight inclination at the feature side walls, which is inherited from the stamp shape ( figure 3(a)). A PMMA residue is left at the bottom of the slit, which is typical for NIL and is removed by the dry etching step [34,35].
In figure 3(b), we see the camera image of the imprinted Si chip. Although we achieved locally uniform regions, one can immediately realize the macroscopic defects present on the surface. Most of these defects originate from the nonuniform pressure distribution. When both the substrate and the stamp are rigid, uniform application of high pressure necessary for PMMA (30-50 bar) is challenging ( figure S4). Microscopically, these defects originated from the capillary forces between the resist and the stamp (see figure S5). Under low local pressure, the stamp and the substrate are not fully in contact. Then, the resist is pulled toward the walls of the stamp features, moving upwards from the substrate surface. This material displacement leads to a locally increased resist thickness and, complementary to this, a dewetting of resist from the substrate, creating bubble-shaped defects (see figure  S5(a)) [36]. As a result, the unevenness of the resist thickness made it impossible to achieve uniform etching on the Si substrates; we always observed some over or under-etched regions. Another source of local pressure variation is a change in the pattern density on the stamp [37]; having slit arrays and empty regions close together leads to uneven resist flow and large-scale defective areas (see figures S4-S6).
While pressure variations due to pattern density can be remedied by modeling the stamp design [38,39], another non-negligible effect came from the nanoimprinting tool. Any roughness present on the printer plates resulted in defects in the imprinted regions. We attempted the NIL process using different tools: an EHN-3250 Nanoimprinter, an EVG wafer bonder (using graphite sheets as compensation layers), and NIL Technology's CNi benchtop membrane pressing tool. Each tool gave different results having defective regions to some extent (see figures S4(a), (d)-(f)).
Once we achieved high-quality, uniform regions, we demonstrated the general applicability of the method by growing in-plane NWs. Following the pattern transfer to the SiO 2 layer, the substrate is loaded to the MOVPE reactor, and Ge NWs are grown as explained in detail in [28]. SEM micrograph in figure 3(c) confirms the uniformity of the structures (see also figure S7). There are some triangular defects indicated with white arrows, which have been correlated with stacking faults that nucleate at the bottom of the slit [28]. We can see the presence of stacking faults in the HR-TEM micrograph given in figure 3(d). These defects seemingly nucleate at the bottom of the slits and penetrate through the NW (figures 3(c) and (f)). When we check the top surface of the NW, we found it defect-free (see figure S8).
EDX analysis of the cross-section confirmed the absence of native oxide between the NW and the substrate, thus highlighting the epitaxial relationship (see figure S9). We see that the NW accommodates the slightly asymmetric shape from the side walls of the mask, which is prominent on structures with larger widths (∼300 nm). This probably stems from the fact that side walls collect more precursor molecules than the middle.
Given the results of our growth, we can confirm that horizontal NW growth on substrates patterned with our thermal NIL process is feasible. Due to some reproducibility issues, which are already present at the chip scale, we found that wafer-scale patterning was out of reach with our thermal NIL process and our current equipment. Thus, we decided to explore an alternative process: UV NIL.

UV NIL
We used a UV NIL process to pattern 2 inch Si and GaAs wafers ( figure 4(a)). We fabricated our polymer stamps from an EBL-patterned Si master template having a variety of features: arrays of lines with different widths (between 80 and 240 nm) and pitches (between 500 and 4000 nm), arrays of circular holes (diameters between 80 and 160 nm), and isolated junctions and their networks along high symmetry directions. Figures 4(b)-(f) show SEM micrographs of some imprinted features, including junctions, holes as well as grids. Compared to the resist used in thermal NIL, UV curable resist has a lower viscosity. This makes the resist level out more homogeneously while pressing the polymer stamp onto the substrate. As a result, patterning appears to be more uniform over the entire wafer surface [40]. Arrays of horizontal slits are imprinted without any defects (see figure S11). We did not observe any significant variation with respect to width and pitch. However, we had some defective regions around enclosed slit networks (see figures 4(f) and S12). Since the process is performed under atmospheric pressure, air may be trapped inside the shapes, preventing the resist displacement. The occurrence of this type of defect seems random, we did not find any correlation with any process parameter. In some regions, such structures were transferred almost defect-free (figures 4(e) and S12), whereas other regions with the same pattern had many defects (figure 4(f)). A reason behind this air inclusion could be the manual pressing of the stamp as we do not use any tool for the process (see the methods section 4). One can address this air inclusion issue by introducing a roller to achieve a more controlled process instead of pressing it by hand. Another solution could be optimizing the design of the pattern. A study comparing the number of gas inclusions in closed structures or networks of varying sizes and pitches may help to understand their appearance better and provide information towards using the process for other For thermal NIL, we patterned our stamps with DUV lithography, and for UV-NIL, we used a UV transparent polymer stamp (OrmoStamp ® ) which we replicated from an EBL-patterned master template.
Step 2 is nanoimprinting: thermal NIL was done using a hydraulic press with two heated metal plates, and UV NIL was done manually by hand.
Step 3 is substrate fabrication after lithography and the following NW growth, which is common for both thermal and UV-NIL.
arbitrarily-shaped structures. Another challenge we faced was the difficulty of demolding the GaAs substrates after patterning. GaAs substrates are more brittle than Si and thus carry a higher fracture risk. One could possibly reduce this risk by using a flexible glass backbone for the polymer stamp instead of a rigid glass plate or a flexible polymer stamp (e.g. made of h-PDMS or x-PDMS) in combination with a suitable resist.
Overall, wafer-scale patterning with UV NIL worked for both Si and GaAs substrates. The mask openings have the same quality as on EBL-patterned substrates on the entire wafer surface (see figures S17(a)-(c) and (e)-(g)).
Next, we demonstrate the heteroepitaxy of Ge and homoepitaxy of GaAs NWs on the UV NIL patterned substrates. We first show the growth of Ge NWs on Si (100) substrates (figure 5). One challenge in manual imprinting might be the correct angular alignment of the stamp with respect to the substrate. Any significant misalignment of the pattern with respect to the high symmetry crystalline directions will result in steps or non-uniformity in the grown structures [28,41]. By looking at the SEM micrographs in figures 5(a) and (b), we see that NWs grown along 〈110〉 and 〈100〉 indeed have the highest uniformity, as expected when the patterns are correctly aligned with the substrate. This confirms that the manual alignment was precise enough to match the template orientation with the crystal orientation of the substrate for epitaxial growth.
Top view SEM micrograph of NWs grown along the 〈100〉 and 〈110〉 directions are given in figures 5(c) and (d), respectively. NWs along the 〈110〉 direction exhibited a more pronounced flat top facet compared to ones along the 〈100〉 direction, which have a more triangular cross-section. The relative size of the facets that develop is a direct result of differences in growth rate along different crystal directions under our growth conditions. The Ge NW junctions along high symmetry directions have the same symmetrical shape and smoothness as junctions grown on EBL-patterned substrates [28]. We did not observe any discernible differences between the NWs merging along different directions (see figure S14). Some amount of parasitic growth was present on the mask (as in figures 5(a) and (b)) related to the quality of the PECVD oxide mask used in the first batch of samples. By using thermally grown oxide, we achieved better selectivity and reduced parasitic Ge growth, thus confirming that the appearance of parasitic growth is not related to the lithography.
Next, we share our results on the homoepitaxial GaAs growth on UV NIL-patterned (100) substrates. Figures 6(a), (b) shows SEM micrographs of NW structures grown along different crystal orientations. NWs along 〈100〉 direction grow much wider than NWs along 〈110〉 for the same slit width due to the polarity of the facets, and it is expected from the crystal growth perspective. SEM micrograph figure 6(c) shows an array of NWs with widths increasing from top to bottom. This particular pattern shows the ability to have structures of varying widths and distances in direct proximity without any issues. Figures 6(d), (e) show the cross-sectional analysis of 180 nm wide GaAs NW by HAADF-STEM and HR-TEM, respectively. The round shape of the top of the NW is a result of amorphization during the FIB lamella preparation. EDX analysis of the cross-section (see figure S16) confirms the elemental composition of the NW and the symmetrical, welldefined shape of the growth mask. A high-resolution micrograph of the interface between the substrate and the NW is given in figure 6(e). The cross-section micrograph as well as the FFT shown in the inset indicate the structure is singlecrystalline.
Both Ge and GaAs NW growth on UV NIL-patterned masks worked very similarly as on EBL-patterned substrates  (see figure S17). Our results indicate that UV-NIL is a robust and fast lithography technique to pattern various shapes and networks, and this method could be easily optimized to obtain reproducible and cost-effectively nanometric patterns at the wafer scale.

Conclusion
We have demonstrated how thermal and UV-NIL can be implemented to pattern substrates for SAE of horizontal NWs and their networks. We discussed the challenges of both processes including pressure distribution and demolding as well as the origins of defects, suggesting possible enhancements for both techniques. In thermal NIL, as a proof of concept, we were able to show its applicability at chip scale. On the other hand, the UV process allowed for wafer-scale patterning of a variety of sub-wavelength features. We found the UV process is superior to thermal NIL not only in patterning quality over larger areas but especially in terms of high throughput since the UV exposure step to polymerize the resist is faster and more controllable than cooling down a thermal NIL resist from its processing temperature. Additionally, we utilize no tool for the imprinting itself, making the process extremely accessible. After the NIL patterning step, we performed growths on substrates patterned with both techniques. In each case, the resulting Ge and GaAs horizontal structures showed no additional defects compared to what was observed in structures grown on EBL-patterned substrates. Taking the advantages of our UV NIL over our thermal NIL process into account, substituting EBL patterning with UV NIL can therefore provide cost-and resource-efficient fabrication of semiconductor nanodevices on a large scale.

Methods
Mask oxide deposition: SiO 2 deposition on GaAs and Si substrates was done using a PlasmaLab system 100 PECVD by Oxford Instruments.
Film thickness measurements: resist and oxide layer thicknesses were measured with a Filmetrics F54 automated thickness mapping spectral reflectance system, a Sopra GES 5E spectroscopic ellipsometer, or by checking a cleaved cross-section with SEM.
Anti-sticking treatment: for both thermal and UV NIL, all stamps were treated with an anti-sticking agent to reduce their surface energy and allow for damage-free demolding. Trichlor-(1H,1H,2H,2H-perfluoroctyl)-silane (PFOCTS) was deposited by chemical vapor deposition, leaving the stamps and a few drops of PFOCTS contained in a small container in a vacuum desiccator for 6 h. The evaporated PFOCTS binds to the native surface oxide and forms a self-assembled monolayer. Any excess deposition was removed by sonication in IPA for 5 min.
Thermal NIL: we used patterned silicon stamps to imprint on substrates with a PMMA resist layer for thermal NIL.
Si stamps: stamps for thermal NIL were prepared from 380 μm thin double-side polished 4-in silicon wafers by DUV lithography in an ASML PAS 5500/350C DUV stepper system using a 248 nm KrF laser source. A 65 nm BARC (bottom anti-reflection coating) layer followed by a 400 nm layer of the positive-tone photoresist JSR M108Y were spincoated on the wafer, and the exposure dose was 21 mJ cm −2 . This was followed by a short development step. The process was optimized for line patterns of 200, 250, and 300 nm width and pitches from 1 to 4 μm. The pattern was etched by a twostep process (see figure S3) using an SPTS APS high-density plasma source for BARC etching (CHF 3 /O 2 chemistry) and Alcatel AMS 200 SE for etching 100-150 nm into silicon. The resist was removed by O 2 plasma and a 1 min dip in HF 50% cleaned off any BARC residuals. After the anti-sticking treatment, the stamps were cut in 1 × 1 cm 2 and 2 × 2 cm 2 square chips for imprinting.
Substrate patterning: a PMMA resist with a low molecular weight optimized for thermal NIL (mr-I PMMA35k, micro resist technologies) was spun onto 525 μm thin 4 in Si wafers with a 100 nm thermal oxide layer or 325-375 μm thin 2 inch GaAs wafers with a 25 nm layer of PECVD oxide. Resist thickness was varied between 100 and 150 nm according to the respective stamp depth by changing the spin coating speed. The substrates were baked for 2 min at 140°C and cut into 1 × 1 cm 2 and 2 × 2 cm 2 square chips according to the respective stamp size.
Imprinting was done with an EHN-3250 nanoimprinter consisting of two metal plates that are pressed on each other by a hydraulic system (and can reach a maximal pressing force of 3600 N). Different supports (aluminum foil, dummy wafer) were used between the plates and the sample stack. The plates were heated to 170°C (the glass transition temperature T g of PMMA35k is 105°C) and a pressure of 50 bar was applied for at least 3 min. We mapped the pressure distribution in the tool with pressure-sensitive paper to determine its impact on the patterning (see figure S4(b)). A watercooling system then lowered the temperature to 90°C within 5 min while pressure was still applied. When the pressure was released, the stack was removed from the press and demolded using tweezers. Pressure, time, and temperature were varied to verify the optimal process window. We also tested a second resist for thermal NIL (mr-I 8000R by micro resist technologies) that did not show any advantages for us.
UV NIL: the silicon master template was fabricated from a 525 μm thin single-side polished 4-in silicon wafer. It was spin-coated with a 35 nm film of 20% ZEP (positive resist) and electron beam exposure was done at a dose of 1100 μC cm −2 (Raith EBPG5000 EBL tool) with low-temperature development using n-amyl acetate. After the antisticking treatment of the master with PFOCTS (analogous to the treatment of the stamps for thermal NIL), polymer stamps were molded from it using OrmoStamp ® polymer (micro resist technology). 550 μm thick 4-in Float glass wafers were used as a solid carrier material. They were coated with a thin layer of OrmoPrime (microresist technology) to promote polymer adhesion. After carefully pipetting an approx. 1 ml droplet of the highly viscous OrmoStamp ® prepolymer, avoiding the creation of air bubbles, the glass wafer was slowly brought in contact with the droplet and released on the master. Once the droplet had spread entirely between the two wafers within a couple of minutes, the stack was cured for 10 s in a Beltron UV LED chamber emitting at 405 nm with a power density of 4 W cm −2 . The curing time of 10 s makes up 40× the minimum recommended exposure dose for material curing, whereby an overdose does not affect the material's properties. The polymer stamp was demolded from the Si master with a razor blade and baked at 130°C for 30 min to increase its thermal and environmental stability. On the polymer stamps we also deposited a PFOCTS anti-sticking layer. Atomic force microscopy (AFM) and SEM micrographs of the polymer stamps can be found in figure S10 in the supporting information.
Substrate patterning: we spun a 100 nm layer of mr-I 200NIL resist on 250-300 μm thin 2 inch Si wafers with 110-130 nm of thermal oxide and 325-375 μm thin GaAs (100) wafers with 25 nm PECVD oxide after a dehydration step on a hotplate at 200°C for 5 min. The resist was annealed on a hotplate at 60°C for 3 min. Imprinting was done manually by aligning the polymer stamp on top of the substrate and using two fingers to start pressing on one edge of the wafer lightly, then slowly moving over to the opposite edge bringing the entire sample in lubricated contact with the stamp. Capillary forces keep the sample glued to the stamp while transferring it to the UV chamber. A 10 s UV exposure cured the resist, and the sample was demolded from the stamp using a razor blade.
Pattern transfer by dry etching: the oxygen plasma source was a PVA Tepla GiGAbatch. Descum of resist layers to remove residuals at the bottom of imprinted features was done at 200 W, 200 sccm O 2 flow, and p = 0.5 mbar for 10 s. The descum step is optional. Reactive ion etching (RIE) of SiO 2 layers was done with the SPTS APS using CHF 3 /SF 6 chemistry. Resist stripping after RIE by oxygen plasma was done at 600 W, 400 sccm O 2 flow and p = 0.8 mbar for at least 5 min).
NW growth by MOVPE: the epitaxial growths of Ge and GaAs were done using an AIX 200 horizontal metalorganic vapor phase epitaxy (MOVPE) system from Aixtron.
Ge NWs on Si(100) substrates: the samples were dipped in 10% HF for 10 s immediately before growth to remove native oxide and smooth the surface. Prior to the NW growth, the substrates were thermally cleaned in AsH 3 flow at 780°C for 15 min. For the thermal cleaning step, the AsH 3 flow rate was maintained at 60 sccm. The thermal cleaning step is important to remove any native oxide of Si formed during transfer to the reactor and to ensure high-quality epitaxial growth. After the thermal cleaning step, AsH 3 flow was turned off and the substrates were cooled down to the growth temperature under N 2 flow. SAE of Ge NWs was conducted at a reactor temperature of 700°C using isobutylgermane as the precursor molecule and N 2 as the carrier gas. The precursor flow rate was kept at 1 sccm and the pressure was kept at 30 mbar. The equivalent Ge 2D growth rate was 2 nm min −1 .
GaAs NWs on GaAs(100) substrates: the substrates were dipped in buffered oxide etch diluted with deionized water in a 1:39 volume ratio for 10 s for surface smoothing before putting them into the reactor. In the reactor, substrates were first thermally cleaned in AsH 3 flow (83 sccm) and nitrogen at 820°C for 2 min. For GaAs growth, the reactor was cooled to a temperature of 650°C while maintaining AsH 3 flow to avoid decomposition of the GaAs substrate. The AsH 3 flow was then lowered to 40 sccm and TEGa (Triethylgallium, Ga(C 2 H 5 ) 3 ) was introduced at an effective flow rate of 67 sccm, using N 2 as the carrier gas. The nominal GaAs 2D growth rate was 0.017 nm s −1 . The NW growth time was 294 s at a nominal pressure of 20 mbar.
Characterization: imprinted patterns and NWs were imaged with scanning electron microscopes (Zeiss Gemini 300, Zeiss Merlin and Zeiss LEO 1550). Roughness, pattern depth, and topological analysis were done by AFM (Bruker FastScan AFM with ScanAsyst-Fluid+ cantilevers in tapping mode). NW morphology and crystallinity were characterized by cutting thin (50-100 nm) lamella (perpendicular crosssection) from the NWs with a focused ion beam using a Zeiss NVision 40 and inspecting them with a high-resolution transmission electron microscope (TEM FEI Talos F200S) using HAADF-STEM and EDX.
Werder from Fachhochschule Nordwestschweiz (FHNW) for sharing his CNi-tool, Helmut Schift, Marc Verschuuren, and Yorick Bleiji for helpful discussions on the basics of nanoimprinting, and Alexandru Mereuta for sharing his expertise on wafer bonder.

Data availability statement
All data that support the findings of this study are included within the article (and any supplementary files).