Interface resistance-switching with reduced cyclic variations for reliable neuromorphic computing

As a synaptic device candidate for artificial neural networks (ANNs), memristors hold great promise for efficient neuromorphic computing. However, commonly used filamentary memristors normally exhibit large cyclic variations due to the stochastic nature of filament formation and ablation, which will inevitably degrade the computing accuracy. Here we demonstrate, in nanoscale Ag2S-based memristors that resistance-switching (RS) at the contact interface can be a promising solution to reduce cyclic variations. When the Ag2S memristor is operated with a filament-free interface RS via Schottky barrier height modification at the contact interface, it shows an ultra-small cycle-to-cycle variation of 1.4% during 104 switching cycles. This is in direct contrast to the variation of (28.9%) of the RS filament extracted from the same device. Interface RS can also emulate synaptic functions and psychological behavior. Its improved learning ability over a filament RS, with a higher saturated accuracy approaching 99.6%, is finally demonstrated in a simplified ANN.


Introduction
The human brain is adept at processing intensive data through its highly interconnected neural networks while consuming only a femto joule per synaptic event [1].Inspired by the efficient computing of the brain, artificial neural networks (ANNs) have made great strides in artificial intelligence tasks, * Authors to whom any correspondence should be addressed.
Original content from this work may be used under the terms of the Creative Commons Attribution 4.0 licence.Any further distribution of this work must maintain attribution to the author(s) and the title of the work, journal citation and DOI.e.g.image/voice recognition, real-time big data analysis [2][3][4].However, with the increasing demand for computing capacity, conventional von Neumann computers that support neural network algorithms exhibit severe time latency and high energy consumption [5,6].A novel hardware implementation with improved computing efficiency has to be developed.
In-memory computing systems consisting of artificial neurons and synaptic devices, has been considered as promising candidates.The synaptic device that modulates the connection strength between neurons, enables the parallel data storage and processing in the in-memory computing system [7,8].In past decades, dedicated efforts have been devoted to developing electronic synapses with nonvolatile memory devices.The two-terminal memristor has gained extensive attention thanks to its ability to modulate conductance under electric fields and its highly scalable device structure [9,10].ANNs consisting of flexible memristor arrays can realize complex artificial intelligent tasks with reduced power consumption and data latency, which is greatly desired in wearable applications [11].As the key synaptic device in advanced neural networks (e.g.spiking neural network (SNN)), memristors are also required to emulate biological synaptic plasticity such as short-term/long-term plasticity, spike-timing dependent plasticity (STDP), etc [3].Currently, various memristors, including resistive random-access memories and conductive bridging memories, mostly operate with a filamentary resistance switching (RS) mechanism [12].However, forming conductive filaments requires a high-energy electrical pulse, which generates a large overshoot current in nanoseconds [9].It is therefore challenging to precisely control the filament size, thus degrading the conductance tunability.Besides, the joule heating generated by the overshoot current has been proven to severely degrade the device retention, and thus the supplementary overload protection (such as current compliance by peripheral circuits) has to be carefully considered in ANN hardware design [9].Most importantly, the disordered defects and grain boundaries in amorphous or polycrystalline electrolytes predispose the formation of multiple tiny filaments.Setting/resetting such devices would therefore inevitably generate large cycle-to-cycle variations in consequence of the abundant filament residuals [13,14].The stochastic nature of the RS filament has been reported to severely degrade the computing accuracy of neural networks under frequent weight update processes [15].Although filamentary memristors with improved tunability have been demonstrated by utilizing current limiters or developing complex multi-layer electrolytes [16], they significantly increase the complexity of device fabrication and circuit integration.
Recently, memristors based on interface RS have been drawing intensive research attention.Many interface-type memristors have been reported to operate with Schottky barrier height (SBH) modification at the interface, without the requirement of forming conductive filaments.The SBH modification in these memristors is mainly based on trapping/detrapping of charged carriers in the interface states, or field induced oxygen vacancy migration [17][18][19][20].However, trapping/detrapping of charged carriers is metastable, which leads to severe conductance decay.However, the field induced oxygen vacancy migration demands a high energy cost, most probably due to the limited mobility of oxygen vacancy in oxides electrolytes.In our previous work, we demonstrated an Ag 2 Sbased flexible memristor operating with Ag + ion migrationinduced SBH modification [21].The accumulation (or depletion) of Ag + ions at the Ag 2 S/Ag contact interface under an electric field can form a strong interfacial dipole, which modulates the SBH of contact to set (or reset) the memristor.Thanks to the high Ag + mobility in the Ag 2 S electrolyte, a stable interface RS could be achieved in the Ag 2 S memristor with an ultralow switching energy of ∼0.2 fJ (a comparable value to that of biological synapses) [22].In this work, we further demonstrate that the filament-free interface RS in our Ag 2 S memristors could significantly reduce cyclic variations.In addition, with interface RS, synaptic functions such as short-term and long-term plasticity can be realized in a single Ag 2 S memristor, and psychological behavior can be emulated in an Ag 2 S memristor array.Finally, the neural network simulation shows improved image learning ability of interface RS over filament RS in the same Ag 2 S devices, with a higher saturated accuracy approaching 99.6%.

Device fabrication
The fabrication of Ag 2 S-based memristors could be referred to as the reported method [21].The Ag 2 S ingot obtained from solid-state reactions was roller-pressed into films with a certain thickness (e.g. 100 µm).After surface cleaning with buffered hydrofluoric acid and deionized water, a 100 nm-thick silver bottom electrode was deposited by thermal-evaporation.On the top side of the Ag 2 S film, a 5 nm-thick HfO 2 was grown using atomic layer deposition.Afterwards, nanoholes with a 100 nm diameter were patterned using electron beam lithography.The contact hole was formed by reactive ion etching, followed by the deposition of 100 nm-thick top silver electrodes.

Device characterization 2.2.1. Fitting STP behavior.
In the leaky integrate-and-fire model, the membrane potential (u) of neurons is governed by where τ is the time constant, u rest is the rest potential and V is the external electrical bias.Solving this linear differential equation under the absence of an external electric field gives an exponential memory decay function where δ is the conductance and C 0 , C 1 are constants.Fitting the recorded conductance evolution with equation ( 2) gives the characteristic time constant for a certain stimulus, which evaluates the strength of memory by inputs.

Paired-pulse facilitation (PPF).
A paired pulse with the same amplitude and duration, was applied to the device to evoke two current spikes.The PPF ratio was calculated as where I 0 is the peak of the first current spike and ∆I is the difference between the first and the second current peaks.By changing the interval between the applied pair pulses, different PPF ratios can be obtained, which can be fitted with the widely used decay function where A = 34.1,B = 17.6, y 0 = 100.9are stimulus-dependent constants and τ 1 = 1.1 × 10 −4 , τ 2 = 3.7 × 10 −3 are characteristic timescales.

Fitting of long-term potentiation (LTP) and long-term depression (LTD).
The increasement of the normalized synaptic weights under non-identical pulses are fitted following where dw p and dw d are the weight change after potentiation or depression in each learning cycle.w max and w min are the maximum and minimum values of synaptic weights.A p = 0.018, B p = 0.035, C p = −0.5,A d = 0.001 63, B d = −0.05,and C d = 0.05 are fitting parameters.Randn is the standard normal distribution between −1 and 1, and its product with C v describes the cycle-to-cycle variations of synaptic weight update.

Non-linearity of LTP and LTD.
The relative nonlinearity of the weight update can be extracted by using a behavioral model described below: (7) G LTP and G LTD are the conductance for LTP and LTD, respectively.G max , G min , and P max are the maximum conductance, minimum conductance and the maximum pulse number in LTP/LTD processes.The parameter A evaluates the nonlinearity of the weight update process [23].

The calculation of learning accuracy.
The conductance of the interface RS and the filament RS is normalized and the accuracy is calculated by (10) where n = 28 × 28 is the number of pixels of the image, W t (i) and W l (i) are the target weight and learned weight, respectively.

Interface resistance-switching with reduced cyclic variations
Analogous to synapses, the top and bottom Ag electrodes of our Ag 2 S-based memristor can be treated as the pre-synaptic and post-synaptic neurons, and the Ag 2 S electrolyte (100 µm thick) acts as the synaptic cleft (see figure 1(a)).In contrast with conventional symmetric metal-insulator-metal structure, the Ag 2 S-based memristor has two asymmetric Ag contacts.The nanoscale top contact formed via a 100 nm nano-hole dominates the total resistance of the device and plays an essential role for the interface RS [21,22].Herein, cycle-tocycle variations of the interface RS are benchmarked directly with the filament RS in the same Ag 2 S device.As shown in figure 1(b), the device current at the forward scanning (from 0 to −0.4 V) exhibits exponential increase.This is induced by the Ag + ions accumulation at the top nano-contact, which forms a strong interfacial dipole and reduces the SBH of the Ag 2 S/Ag interface.Such an interface RS at the top of the nanocontact turns on the Ag 2 S memristor.The Ag filament grows and bridges the top and bottom electrodes at about −0.5 V, which is indicated by an abrupt current jump in the plot.Please note that the interface RS and the filament RS operate in two different conductance ranges demarcated by ∼10 −4 S. As experimentally proved by our previous work [21]: the resistance of the device under interface RS demonstrates an exponential dependence on temperature, which is the character of the thermal emission process over a Schottky junction.In contrast, when operating with filament RS, the device resistance exhibits a typical linear dependence on temperature for a metallic conductor, due to the fully formed silver filaments connecting the top and bottom electrodes.Under repetitive d.c.±0.5 V setting/resetting biases, the residual filament effect becomes notable.The threshold voltage for filament formation in different cycles varies between −0.1 to −0.5 V, and this stochasticity leads to a wide ON state conductance distribution.When the setting/resetting biases are reduced to ±0.2 V bias to realize the sole interface RS without forming any filament, the switching uniformity can be significantly improved, as shown in figure 1(c).To quantitatively evaluate the cycleto-cycle variation in RS, endurance test with 10 4 cycles were conducted for both interface and filament RS, as summarized in figure S1 of the supplementary material (SM).Statistical analysis of the ON state conductance (see figure 1(d)) clearly shows much narrower conductance distribution from interface RS than filament RS.The ultra-small coefficient of variation (C v at 1.4%, calculated by dividing the standard deviation with population mean to evaluate the data dispersion) extracted from the interface RS data is in direct contrast to the filament RS (with C v at 28.9%).

Neuromorphic behavior of interface resistance-switching
Biological synapses release neurotransmitters to regulate the communication between neurons, and this process can be emulated by artificial devices employing mobile ions to control synaptic weight [24].The synaptic behavior of interface RS in the Ag 2 S-based memristor is further studied.Shortterm potentiation (STP) is the temporary response of a postsynaptic neuron to pre-synaptic activity, which helps the neural network extract useful information.We show that the STP can be mimicked in the Ag 2 S device.The short presynaptic spikes (−0.3 V, 10 µs) shown in figure 2(a) induce the temporary increase of the post-synaptic current (PSC, representing the synaptic weights), which rapidly decays to the initial value in a few microseconds.By fitting the recorded PSC trace with the commonly used decay function (see the formula in figure 2(a)), an increase in relaxation time (τ ) from 2.5 µs to 7.6 µs is observed under four continuous spikes.Such STP can be further demonstrated in PPF process.As shown in figure S2, two identical spikes applied with variable time intervals (∆t) trigger different excitatory PSCs.The PPF ratio decays exponentially with the pulse interval, which plays an important role in the coding/decoding of temporal stimulus [25].
Longer pulses could extend the relaxation time from milliseconds to seconds time scales, forming LTP.In figure 2(b), a 10 ms pulse at −0.3 V triggers a typical LTP behavior, with the elevated postsynaptic current well retained after the pulse.The enhanced potentiation should be related to the formation of robust Ag + clusters under strong pulses, which are resistive to the incompatible tension and energy at the interface between the electrolyte and the cluster (as also observed in other metal chalcogenides) [26,27].Long-term plasticity with multiple levels of synaptic weights is the key function of artificial synapses to realize memory and learning process.Figure S3 shows the potentiation and depression processes of an Ag 2 S synapse under successive identical pulses.The recorded PSC demonstrates different responses to the stimuli, indicating the spike-amplitude-dependent plasticity of the Ag 2 S synapse.However, the device shows a typical nonlinear LTP/LTD behavior in figures S3 and S4 as reported for most artificial synapses.This nonlinear LTP/LTD behavior is normally caused by saturated ion migration under electric fields.The ion migration/redox promoted by the subsequent identical pulses is weaker than that of previous pulses, leading to inefficient weight update as pulse number increased.In figure 2(c), we show that the nonlinearity can be improved using a non-identical pulse train (with the pulse amplitude linearly varied from ±0.1 V to ±0.4 V, see pulse scheme in figure S5).The ±0.1 V pulses slow down the accumulation/depletion of Ag + ions for LTP/LTD, and ±0.4 V biases prevent the saturation effect and results in a significantly improved linearity.The increasement of synaptic weights of LTP/LTD under non-identical pulses are fitted to quantitatively describe the weight update process in figure S6 and method section.
As an important form of long-term plasticity, STDP is essential in the learning process of SNNs.Under the STDP rule, the two neurons tune their connection strength according to the timing of pre-and post-synaptic spikes.To demonstrate STDP in the Ag 2 S-based synapse, we carefully designed the presynaptic and postsynaptic spike trains.As depicted in figure S7, both pre-and post-synaptic spikes consist of a positive and a negative pulse, with different voltage peaks (±0.1 V for presynaptic spikes and ±0.2 V for postsynaptic spikes).When firing the two spikes with a certain time interval (∆t), the integrated pulse becomes asymmetric.Specifically, if the postsynaptic spike fires before the presynaptic spike (∆t < 0), the integrated negative setting bias exhibits higher amplitude than that of the positive resetting bias to facilitate the LTP process, and vice versa when ∆t > 0. Under such spike trains, the synaptic weight updates exponentially against the pulse interval (with different relaxation times fitted for potentiation and depression as shown in figure 2(d)), successfully demonstrating the STDP behavior of the Ag 2 S synapse.

Transition from STP to LTP
The synaptic device in SNN is expected to respond differently to the external stimulus to realize the learning process.For the Ag 2 S synapse, we show that the transition of plasticity under interface RS can be achieved by controlling the spike train.We show in figure 3(a), seven consecutive weak pulses (−0.3 V amplitude, 100 µs duration and 100 µs pulse interval) lead to transient conductance increments and cause a typical STP process.LTP can be achieved by increasing the pulse duration to 1 ms, as shown in figure 3(b).The PSC exhibits a multi-step increase under consecutive strong pulses, and stabilizes over tens of seconds.The transition from STP to LTP can also be achieved by increasing the amplitude or reducing the pulse interval, as evidenced in figures 3(c) and (d), respectively.The STP is attributed to the transient SBH modulation.Under weak pulses, localized accumulation of Ag + ions results in the formation of small clusters that can subsequently diffuse back into the Ag 2 S electrolyte to restore equilibrium at the interface.In contrast, strong pulses form robust Ag + /Ag clusters, which are resistive to the incompatible tension and energy at the interface between the electrolyte and the cluster [26].The SHB modulation by strong pulses can thus form stable conductive states.With controllable synaptic plasticity, psychological 'memory and forgetting' behavior could be demonstrated on an Ag 2 S artificial synaptic device array.As shown in figure 3(e), the letter 'I' and 'L' were encoded into the Ag 2 S memristor array, by applying −0.3 V pulses in the patterns with duration of 10 ms and 0.5 ms, respectively.The conductance of each pixel was recorded, with the memristor array bent under a 3 mm curvature radius.The letter 'L' fades soon after the input pulse and almost loses the stored information in 30 s.By contrast, the letter 'I' is well maintained in LTP mode.

Image learning demonstration
To further evaluate the computing performance of the interface RS, we conducted an image learning simulation of a 28 × 28 memristor-based neural network.As shown in figure 4(a), the simplified perceptron neural network, first reported by Sun et al [28], consists of image sensors and two layers of synaptic neurons.It learns the features of the input data via a synaptic weight update between the pre-synaptic layer and the post-synaptic layer.The image sensor detects the pixel value of the input image and linearly maps the greyscale value to the target conductance.The presynaptic neurons are fully connected to the postsynaptic neurons via 28 × 28 synaptic devices, with the learnt synaptic weights updated towards the target conductance value.In each learning cycle, if the learned synaptic weight (w l (i)) is smaller than the target value (w t (i)), a presynaptic spike is sent ahead of the postsynaptic spike, and vice versa.According to the STDP rule, the synaptic weight potentiates or depresses following the experimental results of the LTP/LTD processes, during which the accuracy of weight update can be evaluated by comparing the target and the learned weights in the neural network (see the flowchart of learning in figure S8).
In this simulation, the initial states of 28 × 28 memristors were randomly distributed between 0 and 1.During each learning cycle, one integrated pulse containing pre-synaptic and post-synaptic spikes is sent to the memristors, and the synaptic weights of the memristors evolve towards the corresponding target values to improve the learning accuracy.Different cycleto-cycle variations in interface and filament RS, which were extracted from endurance characterization (see figure 1(d)), were introduced into the weight update process in the simulation.Figure 4(b) shows the calculated accuracy against the learning cycles (see accuracy calculation in method section).
The neural network operated with interface RS exhibits rapidly improved accuracy in the first 30 cycles, and reaches a saturated value of 99.6%.By contrast, the one operated with the filament RS shows a smaller slope in the accuracy curve and a reduced saturation value of 94%, indicating the degradation of learning ability caused by the large cycle-to-cycle variation.The visualization of the updated synaptic weights shown in figure 4(c) provides the direct comparison of the learning ability between interface and filament RS.The pattern gradually becomes recognizable and remains stable after 50 learning cycles, with more dead pixels observed in the filament RS.Please note that the accuracy calculated here considers only the effect of cycle-to-cycle variation on the weight update process.In practical memristor-based hardware, other nonideal properties (such as device-to-device variation and conductance loss, which are beyond the scope of this work) of synaptic devices would inevitably degrade the computing performance as well.

Conclusion
In this work, we demonstrate that the interface RS can significantly reduce cycle-to-cycle variations in nanoscale Ag 2 S memristors, by avoiding the stochastic process of filament formation/ablation.Synaptic functions such as STP and LTP can be realized and psychological 'memory and forget' behavior can be emulated, using the interface RS in Ag 2 S memristors.The image learning simulation on an ANN further confirms the improved learning ability of the interface RS over filament RS, due to the reduce cycle-to-cycle variations.

Figure 1 .
Figure 1.Comparison of cycle-to-cycle variations between interface and filament RS in the same Ag 2 S memristor.(a) Schematic illustration of a Ag 2 S synaptic device, which is composed of Ag top electrode (Ag TE, as a pre-neuron), HfO 2 layer (for the formation of top nano-contact holes), Ag 2 S electrolyte (as an active electrolyte and a flexible substrate) and Ag bottom electrode (Ag BE, as a post-neuron).(b) Current (I)-voltage (V) characteristics of the filament RS in the Ag 2 S memristor under 10 repetitive 0 → −0.5 → 0.5 → 0 V d.c.pulses.The filament RS leads to a wide distribution of forming voltage and ON state conductance.(c) I-V characteristics of the interface RS in the Ag 2 S memristor under 10 repetitive 0 → −0.2 → 0.2 → 0 V d.c.pulses.The interface RS shows significantly improved switching uniformity.(d) The cumulative probability of the ON state conductance of the interface and filament RS during 10 4 switching cycles.The coefficient of variation (Cv) is calculated to evaluate the dispersion of conductance.

Figure 2 .
Figure 2. Neuromorphic behavior of a Ag 2 S synaptic device under interface RS.(a) The device current trace during the application of 4 pulses (−0.3 V, 10 µs).By fitting the PSC using the decay function, the relaxation time (τ ) after each pulse is extracted, as shown in the figure.The result indicates a typical STP behavior under continuous inputs.(b) The recorded device current (read at 5 mV) after applying a −0.3 V, 10 ms pulses, indicating a typical LTP behavior.(c) The LTP/LTD under setting/resetting pulses with non-identical amplitude (±0.1 V to ±0.4 V, 0.5 ms).The post-synaptic current (PSC) is read at 5 mV.(d) The STDP behavior demonstrated by the Ag 2 S-based memristor.The time interval between pre-and post-spikes (∆t) is defined as tpost − tpre.The increasement of synaptic weight (∆W) is defined as (Wpost − Wpre)/Wpre, where Wpost and Wpre represent the weights before and after spikes.By fitting ∆W with different ∆t using the decay function, the STDP behavior can be quantitatively characterized as shown in the figure.

Figure 3 .
Figure 3. Transition from STP to LTP under interface RS.(a) The recorded post-synaptic current during the application of pulses with −0.3 V amplitude, 100 µs duration and 100 µs interval, showing STP behavior.(b) The recorded post-synaptic current during the application of pulses with −0.3 V amplitude, 1 ms duration and 1 ms interval, showing LTP behavior.(c) The recorded post-synaptic current during the application of pulses with −0.5 V amplitude, 100 µs duration and 100 µs interval, showing LTP behavior.Please note that although the voltage used here is −0.5 V, the pulse duration is too short for filament formation.The device is still in the interface RS, as evidenced by <10 −4 S conductance.(d) The recorded post-synaptic current during the application of pulses with −0.3 V amplitude, 100 µs duration and 30 µs interval, showing LTP behavior.(e) Demonstration of 'memory and forgetting' behavior on Ag 2 S device array.The enclosed optical photograph shows a bended device array.The letters 'I' and 'L' were encoded into a 7 × 7 Ag 2 S device array by applying a 10 ms or 0.5 ms pulse (−0.3 V) respectively.The conductance evolution of each device against the elapsed time was recorded.

Figure 4 .
Figure 4.The image learning demonstration on the neural network simulation.(a) The schematic illustration of the network structure.(b) The learning accuracy of networks operating with interface-type and filament-type synaptic devices.(c) The visualization of learnt patterns in different learning cycles.The images containing other digitals can be found in figure S9.