International Workshop on Semiconductor Pixel Detectors for Particles and Imaging (Pixel 2016)

CMOS Monolithic Active Pixel Sensors (MAPS) are considered as an emerging technology in the field of charged particle tracking. They will be used in the vertex detectors of experiments like STAR, CBM and ALICE and are considered for the ILC and the tracker of ATLAS. In those applications, the sensors are exposed to sizeable radiation doses. While the tolerance of MAPS to ionizing radiation and fast hadrons is well known, the damage caused by low energy neutrons was not studied so far. Those slow neutrons may initiate nuclear fission of ¹⁰B dopants found in the B-doped silicon active medium of MAPS. This effect was expected to create an unknown amount of radiation damage beyond the predictions of the NIEL (Non Ionizing Energy Loss) model for pure silicon. We estimate the impact of this effect by calculating the additional NIEL created by this fission. Moreover, we show first measured data for CMOS sensors which were irradiated with cold neutrons. The empirical results contradict the prediction of the updated NIEL model both, qualitatively and quantitatively: the sensors irradiated with slow neutrons show an unexpected and strong acceptor removal, which is not observed in sensors irradiated with MeV neutrons.

This article presents the first measured results from the H35DEMO pixel demonstrator. The H35DEMO is a prototype ASIC in the 0.35 μm High Voltage-CMOS (HV-CMOS) process from ams aimed at proving that HV-CMOS sensor technologies are suitable as tracking detectors for the ATLAS High Luminosity-LHC (HL-LHC) upgrade. The prototype was fabricated in an engineering run, in which wafers with four different substrate resistivities, ranging from the standard value of 20 Ω ⋅ cm to a high value of 1 kΩ ⋅ cm, were used to increase the depletion region of the sensor. The prototype includes four large area matrices and a few test structures. New experimental set-ups have been developed to measure the ASIC with radioactive sources and laser beams. The experimental set-ups and the measured results obtained will be discussed in this article.

Silicon-On-Insulator (SOI) technology was used to develop a fine pixelated detector with high performance. The first beam test for a prototype pulse-counting-type SOI chip, CPIXTEG3b, was performed at beamline BL-14A of the Photon Factory, KEK. CPIXTEG3b was designed using double SOI technology for decreasing crosstalk and increasing radiation hardness. It has a 64 × 64 pixel array wherein each pixel size is 50 μm × 50 μm. The sensitivity to incident X-rays was measured for each pixel with an X-ray beam 10 μm in diameter. We used the X-ray energy of 16 keV. Because of its small size, the pixel response was sensitive to the charge-sharing effect. We also considered the point spread function of the sensor. The discriminator of each pixel circuit was calibrated using a pulse generator, and performance was checked using flat-field X-rays.

The read-out is one of the challenges in the design of a pixel detector for the High Luminosity upgrade of the Large Hadron Collider (HL-LHC), that is expected to operate from 2026 at a leveled luminosity of 5 × 10³⁴ cm⁻² s⁻¹. This is especially true if tracking information is needed in a low latency trigger system. The difficulties of a fast read-out will be reviewed, and possible strategies explained. The solutions that are being evaluated by the ATLAS and CMS collaborations for the upgrade of their trackers will be outlined and ideas on possible development beyond HL-LHC will be presented.

The new asymmetric electron positron collider SuperKEKB in Tsukuba, Japan, is currently being commissioned. With a design luminosity of 8 · 10³⁵ cm⁻² s⁻¹, leading ultimately to an integrated luminosity of about 50 ab⁻¹, it will overtake by almost two orders of magnitude the record integrated luminosity reached by its predecessor KEKB. With the upgrade, the beam energy asymmetry will be reduced resulting in a lower boost. Thus, the increase in luminosity and the reduction of the boost set stringent requirements on the performance of the Belle II detector, currently under construction, in order to cope with the expected large physics rates. Consisting of two layers mounted at 14 mm and 22 mm radius from the interaction point, the new Belle II pixel vertex detector based on DEPFET technology will provide the necessary three dimensional high precision position measurements of the trajectories of charged particles. This will allow the precise reconstruction of short lived particle vertices. The physics performance of the Belle II pixel vertex detector and its impact in the reduction of experimental uncertainties will be discussed focusing on the measurement of the CP-violating parameters in B-meson decay.

In this paper, an ASIC fabricated in 180 nm CMOS technology from AMS with the very front-end electronics used to readout LGAD sensors is presented as well as its experimental results. The front-end has the typical architecture for Si-strip readout, i.e., preamplification stage with a Charge Sensitive Amplifier (CSA) followed by a CR-RC shaper. Both amplifiers are based on a folded cascode structure with a PMOS input transistor and the shaper only uses passive elements for the feedback stage. The CSA has programmable gain and a configurable input stage in order to adapt to the different input capacitance of the LGAD sensors (pixelated, short and long strips) and to the different input signal (depending on the gain of the LGAD). The fabricated prototype has an area of 0.865 mm × 0.965 mm and includes the biasing circuit for the CSA and the shaper, 4 analog channels (CSA+shaper) and programmable charge injection circuits included for testing purposes. Noise and power analysis performed during simulation fixed the size of the input transistor to W/L = 860 μm/0.2 μm. The shaping time is fixed by design at 1 us and, in this ASIC version, the feedback elements of the shaper are passive, which means that the area of the shaper can be reduced using active elements in future versions. Finally, the different gains of the CSA have been selected to maintain an ENC below 400 electrons for a detector capacitor of 20 pF, with a power consumption of 150 μ W per channel.

The ATLAS Pixel detector has been equipped with an extra pixel layer in the space obtained by a smaller radius beam pipe. This new pixel layer called the Insertable B-Layer (IBL) was installed in 2014 and is operational in the current ATLAS data taking. The IBL detector is cooled with evaporative CO₂ and is the first of its kind in ATLAS. The ATLAS IBL CO₂ cooling system is designed for lower temperature operation (< −35^oC) than the previous developed CO₂ cooling systems in High Energy Physics experiments. The cold temperatures are required to protect the pixel sensors for the expected high radiation dose received at an integrated luminosity of 550 fb¹. This paper describes the design, development, construction and commissioning of the IBL CO₂ cooling system. It describes the challenges overcome and the important lessons learned for the development of future systems which are now under design for the Phase-II upgrade detectors.

IGZO-TFT (Indium Galium Zinc Oxide-Thin Film Transistor) is a promising technology for controlling large display areas and large area sensors because of its very low leakage current in the off state and relatively low cost. IGZO has been used as a switching gate for a large area flat-panel detector. The photon counting capability for X-ray medical imaging has been investigated and expected for low-dose exposure and material determination. Here the design and fabrication of a charge sensitive preamplifier and analog counter using IGZO-TFT processes and its performance are reported for the first time to be used for radiation photon counting applications.

This paper describes the status of the developments made by ATLAS HVCMOS and HVMAPS collaborations. We have proposed two HVCMOS sensor concepts for ATLAS pixels—the capacitive coupled pixel detector (CCPD) and the monolithic detector. The sensors have been implemented in three semiconductor processes AMS H18, AMS H35 and LFoundry LFA15. Efficiency of 99.7% after neutron irradiation to 10¹⁵ n_eq/cm²W has been measured with the small area CCPD prototype in AMS H18 technology. About 84% of the particles are detected with a time resolution better than 25 ns. The sensor was implemented on a low resistivity substrate. The large area demonstrator sensor in AMS H35 process has been designed, produced and successfully tested. The sensor has been produced on different high resistivity substrates ranging from 80 Ωcm to more than 1 kΩ. Monolithic- and hybrid readout are both possible. In August 2016, six different monolithic pixel matrices for ATLAS with a total area of 1 cm² have been submitted in LFoundry LFA15 process. The matrices implement column drain and triggered readout as well as waveform sampling capability on pixel level. Design details will be presented.

The ATLAS Inner Detector will be replaced for the High-Luminosity LHC (HL-LHC) running in 2026. The new Inner Detector is called the Inner Tracker (ITk). The ITk will cover an extended η-range: at least to |η|<3.2, and likely up to 0|η|<4.. The ITk will be an all-Silicon based detector, consisting of a Silicon strip detector outside of a radius of 362 mm, and a Silicon pixel detector inside of this radius. Several novel designs are being considered for the ITk pixel detector, to cope with high-eta charged particle tracks. These designs are grouped into `extended' and `inclined' design-types. Extended designs have long pixel staves with sensors parallel to the beamline, while inclined designs have sensors angled such that they point towards the interaction point. The relative advantages and challenges of these two classes of designs will be examined in this paper, along with the mechanical solutions being considered. Thermal management, radiation-length mapping, and electrical services will also be discussed.

The development of custom ultrasonic instrumentation was motivated by the need for continuous real-time monitoring of possible leaks and mass flow measurement in the evaporative cooling systems of the ATLAS silicon trackers. The instruments use pairs of ultrasonic transducers transmitting sound bursts and measuring transit times in opposite directions. The gas flow rate is calculated from the difference in transit times, while the sound velocity is deduced from their average. The gas composition is then evaluated by comparison with a molar composition vs. sound velocity database, based on the direct dependence between sound velocity and component molar concentration in a gas mixture at a known temperature and pressure. The instrumentation has been developed in several geometries, with five instruments now integrated and in continuous operation within the ATLAS Detector Control System (DCS) and its finite state machine. One instrument monitors C₃F₈ coolant leaks into the Pixel detector N₂ envelope with a molar resolution better than 2⋅ 10⁻⁵, and has indicated a level of 0.14 % when all the cooling loops of the recently re-installed Pixel detector are operational. Another instrument monitors air ingress into the C₃F₈ condenser of the new C₃F₈ thermosiphon coolant recirculator, with sub-percent precision. The recent effect of the introduction of a small quantity of N₂ volume into the 9.5 m³ total volume of the thermosiphon system was clearly seen with this instrument. Custom microcontroller-based readout has been developed for the instruments, allowing readout into the ATLAS DCS via Modbus TCP/IP on Ethernet. The instrumentation has many potential applications where continuous binary gas composition is required, including in hydrocarbon and anaesthetic gas mixtures.

The ATLAS Forward Proton (AFP) detector is designed to identify events in which one or two protons emerge intact from the LHC collisions. AFP will consist of a tracking detector, to measure the momentum of the protons, and a time of flight system to reduce the background from multiple proton-proton interactions. Following an extensive qualification period, 3D silicon pixel sensors were selected for the AFP tracker. The sensors were produced at CNM (Barcelona) during 2014. The tracker module assembly and quality control was performed at IFAE during 2015. The assembly of the first AFP arm and the following installation in the LHC tunnel took place in February 2016. This paper reviews the fabrication process of the AFP tracker focusing on the pixel modules.

We have developed flip-chip modules applicable to the pixel detector for the HL-LHC. New radiation-tolerant n⁺-in-p planar pixel sensors of a size of four FE-I4 application-specific integrated circuits (ASICs) are laid out in a 6-in wafer. Variation in readout connection for the pixels at the boundary of ASICs is implemented in the design of quadsensors. Bump bonding technology is developed for four ASICs onto one quadsensor. Both sensors and ASICs are thinned to 150 μm before bump bonding, and are held flat with vacuum chucks. Using lead-free SnAg solder bumps, we encounter deficiency with large areas of disconnected bumps after thermal stress treatment, including irradiation. Surface oxidation of the solder bumps is identified as a critical source of this deficiency after bump bonding trials, using SnAg bumps with solder flux, indium bumps, and SnAg bumps with a newly-introduced hydrogen-reflow process. With hydrogen-reflow, we establish flux-less bump bonding technology with SnAg bumps, appropriate for mass production of the flip-chip modules with thin sensors and thin ASICs.

The first layer of the CMS Phase 1 pixel detector will be located at a distance of 3 cm from the interaction point. Pixel hit rates up to 600 MHz/cm² are expected at the instantaneous luminosity of 2×10³⁴ cm⁻² s⁻¹ foreseen by LHC in the coming years. The CMS Phase 1 pixel detector will be in operation until 2024/25 and the total fluence received by the first layer in its lifetime will reach 2–3×10¹⁵ n_eq/cm² that corresponds to 0.8–1.2 MGy. A new readout chip, called PROC600, to be used for layer 1 modules has been designed at PSI. To validate robust and efficient operation of PROC600, it has been irradiated to doses ranging from 0.6 MGy up to 4.8 MGy. The chip performance before and after irradiation including the pixel hit efficiency will be presented.

Compton imaging is a useful method to localize gamma sources without using mechanical collimators. In conventional Compton imaging, the incident directions of gamma rays are estimated in a cone for each event by analyzing the sequence of interactions of each gamma ray followed by Compton kinematics. Since the information of the ejection directions of the recoil electrons is lost, many artifacts in the shape of cone traces are generated, which reduces signal-to-noise ratio (SNR) and angular resolution. We have developed an advanced Compton imaging system with the capability of tracking recoil electrons by using a combination of a trigger-mode silicon-on-insulator (SOI) pixel detector and a GAGG detector. This system covers the 660–1330 keV energy range for localization of contamination nuclides such as ¹³⁷Cs and ¹³⁴Cs inside the Fukushima Daiichi Nuclear Power Plant in Japan. The ejection directions of recoil electrons caused by Compton scattering are detected on the micro-pixelated SOI detector, which can theoretically be used to determine the incident directions of the gamma rays in a line for each event and can reduce the appearance of artifacts. We obtained 2-D reconstructed images from the first iteration of the proposed system for ¹³⁷Cs, and the SNR and angular resolution were enhanced compared with those of conventional Compton imaging systems.

We have been developing CdTe pixel detectors combined with a Schottky diode sensor and photon-counting ASICs. The hybrid pixel detector was designed with a pixel size of 200 μ m by 200 μm and an area of 19 mm by 20 mm or 38.2 mm by 40.2 mm. The photon-counting ASIC, SP8-04F10K, has a preamplifier, a shaper, 3-level window-type discriminators and a 24-bits counter in each pixel. The single-chip detector with 100 by 95 pixels successfully operated with a photon-counting mode selecting X-ray energy with the window comparator and stable operation was realized at 20 degrees C. We have performed a feasibility study for a white X-ray microbeam experiment. Laue diffraction patterns were measured during the scan of the irradiated position in a silicon steel sample. The grain boundaries were identified by using the differentials between adjacent images at each position.

We introduce a new method based on the transient-current technique (TCT) for the radiation tolerance assessment of an n-in-p junction with a deep n-well on a relatively low-resistivity p-type substrate commonly used for HV-CMOS pixel sensors. The transient-current method here employed uses a femtosecond laser to generate excess carriers via a two-photon-absorption (TPA) process. Special attention has been paid to overcome the limitations of the conventional transient-current method based on single-photon-absorption carrier generation when applied to the HV-CMOS sensors. Specifically, we tackle the precise determination of the depletion region boundaries, including the deep-n-well spatial location, needed to calculate the effective doping concentration of the substrate. As illustration, we have applied this new TPA-based method to both a fresh and a neutron irradiated single-pixel deep-n-well diode manufactured in a 180 nm high-voltage CMOS process. In the irradiated device, concurrent with the expected effective acceptor removal in the p-type substrate, an indication of an effective donor removal in the DNW implant was also observed.

Characterization of the monolithic pixel detector INPTIX6, designed at KEK and fabricated in Lapis 0.2 μ m Fully-Depleted, Low-Leakage Silicon-On-Insulator (SOI) CMOS technology, was performed. The INTPIX6 comprises a large area of 1408 × 896 integrating type squared pixels of 12 micron pitch. In this work the performance and measurement results of the prototypes produced on lower resistivity Czochralski type (CZ-n) and high resistivity floating zone (FZ-n) sensor wafers are presented. Using ²⁴¹Am radioactive source the noise of INTPIX6 was measured, showing the ENC (Equivalent Noise Charge) of about 70 e⁻. The resolution calculated from the FWHM of the Iron-55 X-ray peak was about 100 e⁻. The radiation hardness of the SOI pixel detector was also investigated. The CZ-n type INTPIX6 received a dose of 60 krad and its performance has been continuously monitored during the irradiation.

In preparation for LHC Run-2 the ATLAS detector introduced a new pixel detector, the Insertable B-Layer (IBL). This detector is located between the beampipe and what was the innermost pixel layer. The tracking and vertex reconstruction are significantly improved and good performance is expected in high level objects such a b-quark jet tagging. This in turn, leads to better physics results. This note summarizes the impact of the IBL detector on physics results, especially focusing on the analyses using b-quark jets throughout 2016 summer physics program.

The ATLAS experiment will undergo around the year 2025 a replacement of the tracker system in view of the high luminosity phase of the LHC (HL-LHC) with a new 5-layer pixel system. Thin planar pixel sensors are promising candidates to instrument the innermost region of the new pixel system, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. The sensors of 50-150 μm thickness, interconnected to FE-I4 read-out chips, have been characterized with radioactive sources and beam tests. In particular active edge sensors have been investigated. The performance of two different versions of edge designs are compared: the first with a bias ring, and the second one where only a floating guard ring has been implemented. The hit efficiency at the edge has also been studied after irradiation at a fluence of 10¹⁵ n_eq/cm². Highly segmented sensors will represent a challenge for the tracking in the forward region of the pixel system at HL-LHC. In order to reproduce the performance of 50x50 μm² pixels at high pseudo-rapidity values, FE-I4 compatible planar pixel sensors have been studied before and after irradiation in beam tests at high incidence angles with respect to the short pixel direction. Results on the hit efficiency in this configuration are discussed for different sensor thicknesses.

The entire ATLAS inner tracking system will be replaced for operation at the HL-LHC . This will include a significantly larger pixel detector of approximately 15 m². For this project, it is critical to reduce the mass of the hybrid pixel modules and this requires thinning both the sensor and readout chips to about 150 micrometres each. The thinning of the silicon chips leads to low bump yield for SnAg bumps due to bad co-planarity of the two chips at the solder reflow stage creating dead zones within the pixel array. In the case of the ATLAS FEI4 pixel readout chip thinned to 100 micrometres, the chip is concave, with the front side in compression, with a bow of +100 micrometres at room temperature which varies to a bow of −175 micrometres at the SnAg solder reflow temperature, caused by the CTE mismatch between the materials in the CMOS stack and the silicon substrate. A new wafer level process to address the issue of low bump yield be controlling the chip bow has been developed. A back-side dielectric and metal stack of SiN and Al:Si has been deposited on the readout chip wafer to dynamically compensate the stress of the front side stack. In keeping with a 3D process the materials used are compatible with Through Silicon Via (TSV) technology with a TSV last approach which is under development for this chip. It is demonstrated that the amplitude of the correction can be manipulated by the deposition conditions and thickness of the SiN/Al:Si stack. The bow magnitude over the temperature range for the best sample to date is reduced by almost a factor of 4 and the sign of the bow (shape of the die) remains constant. Further development of the backside deposition conditions is on-going with the target of close to zero bow at the solder reflow temperature and a minimal bow magnitude throughout the temperature range. Assemblies produced from FEI4 readout wafers thinned to 100 micrometres with the backside compensation layer have been made for the first time and demonstrate bond yields close to 100%.

The LHCb experiment is designed to perform high-precision measurements of CP violation and the decays of beauty and charm hadrons at the Large Hadron Collider (LHC) at CERN. There is a planned upgrade during Long Shutdown 2 (LS2), expected in 2019, which will allow the detector to run at higher luminosities by transforming the entire readout to a trigger-less system. This will include a substantial upgrade of the Vertex Locator (VELO), the silicon tracker that surrounds the LHCb interaction region. The VELO is moving from silicon strip technology to hybrid pixel sensors, where silicon sensors are bonded to VeloPix ASICs. Sensor prototypes have undergone rigorous testing using the Timepix3 Telescope at the SPS, CERN. The main components of the upgrade are summarised and testbeam results presented.

The Silicon Pixel Detector (SPD) constitutes the two innermost layers of the Inner Tracking System of the ALICE experiment and it is the closest detector to the interaction point. As a vertex detector, it has the unique feature of generating a trigger signal that contributes to the L0 trigger of the ALICE experiment. The SPD started collecting data since the very first pp collisions at LHC in 2009 and since then it has taken part in all pp, Pb-Pb and p-Pb data taking campaigns. This contribution will present the main features of the SPD, the detector performance and the operational experience, including calibration and optimization activities from Run 1 to Run 2.

During the 2024–2025 shut-down, the Large Hadron Collider (LHC) will be upgraded to reach an instantaneous luminosity up to 7×10³⁴ cm⁻²s⁻¹. This upgrade of the collider is called High-Luminosity LHC (HL-LHC). ATLAS and CMS detectors will be upgraded to meet the new challenges of HL−LHC: an average of 200 pile-up events in every bunch crossing and an integrated luminosity of 3000 fb⁻¹ over ten years. In particular, the current trackers will be completely replaced. In HL-LHC the trackers should operate under high fluences (up to 1.4 × 10¹⁶ n_eq cm⁻²), with a correlated high radiation damage. The pixel detectors, the innermost part of the trackers, needed a completely new design in the readout electronics, sensors and interconnections. A new 65 nm front-end (FE) electronics is being developed by the RD53 collaboration compatible with smaller pixel sizes than the actual ones to cope with the high track densities. Consequently the bump density will increase up to 4 ·10⁴ bumps/cm². Preliminary results of two hybridization technologies study are presented in this paper. In particular, the on-going bump-bonding qualification program at Leonardo−Finmeccanica is discussed, together with alternative hybridization techniques, as the capacitive coupling for HV-CMOS detectors.

A new pixel detector will be installed in the CMS experiment during the extended technical stop of the LHC at the beginning of 2017. The new pixel detector, built from four layers in the barrel region and three layers on each end of the forward region, is equipped with upgraded front-end readout electronics, specifically designed to handle the high particle hit rates created in the LHC environment. The DAQ back-end was entirely redesigned to handle the increased number of readout channels, the higher data rates per channel and the new digital data format. Based entirely on the microTCA standard, new front-end controller (FEC) and front-end driver (FED) cards have been developed, prototyped and produced with custom optical link mezzanines mounted on the FC7 AMC and custom firmware. At the same time as the new detector is being assembled, the DAQ system is set up and its integration into the CMS central DAQ system tested by running the pilot blade detector already installed in CMS. This work describes the DAQ system, integration tests and gives an outline for the activities up to commissioning the final system at CMS in 2017.

The PiXeL detector (PXL) of the STAR experiment at RHIC is the first application of the state-of-the-art thin Monolithic Active Pixel Sensors (MAPS) technology in a collider environment. Designed to extend the STAR measurement capabilities in the heavy flavor domain, it took data in Au+Au collisions, p+p and p+Au collisions at 0√s_NN=20 GeV at RHIC, during the period 2014–2016. The PXL detector is based on 50 μm-thin MAPS sensors with a pitch of 20.7 μm. Each sensor includes an array of nearly 1 million pixels, read out in rolling shutter mode in 185.6 μs. The 170 mW/cm² power dissipation allows for air cooling and contributes to reduce the global material budget to 0.4% radiation length on the innermost layer. Experience and lessons learned from construction and operations will be presented in this paper. Detector performance and results from 2014 Au+Au data analysis, demonstrating the STAR capabilities of charm reconstruction, will be shown.

The LHCb Experiment at the LHC is successfully performing precision measurements primarily in the area of flavour physics. The collaboration is preparing an upgrade that will start taking data in 2021 with a trigger-less readout at five times the current luminosity. The vertex locator has been crucial in the success of the experiment and will continue to be so for the upgrade. It will be replaced by a hybrid pixel detector and this paper discusses the performance benchmarks of the upgraded detector. Despite the challenging experimental environment, the vertex locator will maintain or improve upon its benchmark figures compared to the current detector. Finally the long term plans for LHCb, beyond those of the upgrade currently in preparation, are discussed.

Results from detectors of poly-crystalline chemical vapour deposited (pCVD) diamond are presented. These include the first analysis of data of the ATLAS Diamond Beam Monitor (DBM). The DBM module consists of pCVD diamond sensors instrumented with pixellated FE-I4 front-end electronics. Six diamond telescopes, each with three modules, are placed symmetrically around the ATLAS interaction point. The DBM tracking capabilities allow it to discriminate between particles coming from the interaction point and background particles passing through the ATLAS detector. Also, analysis of test beam data of pCVD DBM modules are presented. A new low threshold tuning algorithm based on noise occupancy was developed which increases the DBM module signal to noise ratio significantly. Finally first results from prototypes of a novel detector using pCVD diamond and resistive electrodes in the bulk, forming a 3D diamond device, are discussed. 3D devices based on pCVD diamond were successfully tested with test beams at CERN. The measured charge is compared to that of a strip detector mounted on the same pCVD diamond showing that the 3D device collects significantly more charge than the planar device.

The LHC machine is planning an upgrade program which will smoothly bring the luminosity to about 7.5×10³⁴cm⁻²s⁻¹ in 2028, to possibly reach an integrated luminosity of 3000 fb⁻¹ by the end of 2037. This High Luminosity scenario, HL-LHC, will present new challenges in higher data rates and increased radiation. In order to maintain its physics reach the CMS collaboration has undertaken a preparation program of the detector known as Phase-2 upgrade. The CMS Phase-2 Pixel upgrade will require a high bandwidth readout system and high radiation tolerance for sensors and on-detector ASICs. Several technologies for the upgrade sensors are being studied. Serial powering schemes are under consideration to accommodate significant constraints on the system. These prospective designs, as well as new layout geometries that include very forward pixel discs, will be presented together with performance estimation.

Efficient and precise reconstruction of the primary vertex in a LHC collision is essential for determining the full kinematic properties of a hard-scatter event and of soft interactions as a measure of the amount of pile-up. The reconstruction of primary vertices in the busy, high pile-up environment of Run-2 of the LHC is a challenging task. The algorithms developed by the ATLAS experiments to reconstruct multiple vertices with small spatial separation are presented.

This paper is a review of recent progress of RD53 Collaboration. Results obtained on the study of the radiation effects on 65 nm CMOS have matured enough to define first strategies to adopt in the design of analog and digital circuits. Critical building blocks and analog very front end chains have been designed, tested before and after 5–800 Mrad. Small prototypes of 64×64 pixels with complex digital architectures have been produced, and point to address the main issues of dealing with extremely high pixel rates, while operating at very small in-time thresholds in the analog front end. The collaboration is now proceeding at full speed towards the design of a large scale prototype, called RD53A, in 65 nm CMOS technology.

The CMS pixel detector was repaired successfully, calibrated and commissioned for the second run of Large Hadron Collider during the first long shutdown between 2013 and 2015. The replaced pixel modules were calibrated separately and show the expected behavior of an un-irradiated detector. In 2015, the system performed very well with an even improved spatial resolution compared to 2012. During this time, the operational team faced various challenges including the loss of a sector in one half shell which was only partially recovered. In 2016, the detector is expected to withstand instantaneous luminosities beyond the design limits and will need a combined effort of both online and offline teams in order to provide the high quality data that is required to reach the physics goals of CMS. We present the operational experience gained during the second run of the LHC and show the latest performance results of the CMS pixel detector.

The HV-CMOS (High Voltage - Complementary Metal-Oxide Semiconductor) pixel technology has recently risen interest for the upgrade of the pixel detector of the ATLAS experiment towards the High Luminosity phase of the Large Hadron Collider (LHC) . HV-CMOS sensors can be employed in the pixel outer layers (R >15 cm), where the radiation hardness requirements are less stringent, as they could instrument large areas at a relatively low cost. In addition, smaller pixel granularity can be achieved by exploiting sub-pixel encoding technology. Therefore, the largest impact on physics performance, tracking and flavour tagging, could be reached if exploited in the innermost layer (in place of the current IBL) or in the next-to-innermost layer. This proceeding will present studies on tracking and flavour-tagging performance in presence of HV-CMOS sensors in the innermost layer of the ATLAS detector.

Planar hybrid silicon sensors are a well proven technology for past and current particle tracking detectors in HEP experiments. However, the future high-luminosity upgrades of the inner trackers at the LHC experiments pose big challenges to the detectors. A first challenge is an expected radiation damage level of up to 2⋅ 10¹⁶ n_eq/cm². For planar sensors, one way to counteract the charge loss and thus increase the radiation hardness is to decrease the thickness of their active area. A second challenge is the large detector area which has to be built as cost-efficient as possible. The CiS research institute has accomplished a proof-of-principle run with n-in-p ATLAS-Pixel sensors in which a cavity is etched to the sensor's back side to reduce its thickness. One advantage of this technology is the fact that thick frames remain at the sensor edges and guarantee mechanical stability on wafer level while the sensor is left on the resulting thin membrane. For this cavity etching technique, no handling wafers are required which represents a benefit in terms of process effort and cost savings. The membranes with areas of up to ∼ 4 × 4 cm² and thicknesses of 100 and 150 μm feature a sufficiently good homogeneity across the whole wafer area. The processed pixel sensors show good electrical behaviour with an excellent yield for a suchlike prototype run. First sensors with electroless Ni- and Pt-UBM are already successfully assembled with read-out chips.

The present CMS pixel detector will be replaced with an upgraded pixel system during the LHC extended technical stop in winter 2016/2017. The CMS Phase I pixel upgrade combines a new pixel readout chip, which minimises detection inefficiencies, with several other design improvements to maintain the excellent tracking performance of CMS at the higher luminosity conditions foreseen for the coming years. The upgraded detector features new readout electronics which require detailed evaluation. For this purpose a test stand has been set up, including a slice of the CMS pixel DAQ system and all components of the upgraded readout chain together with a number of detector modules. The test stand allows for detailed evaluation and verification of all detector components, and is also crucial to develop tests and procedures to be used during the detector assembly and the commissioning and calibration of the detector. In this paper the system test and its functionalities will be described with a focus on the tests performed for the barrel pixel detector. Furthermore, the assembly and integration of the readout electronics for the final detector system will be presented.

This paper describes a readout ASIC prototype designed by CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64 × 64 matrix of 50 × 50 μ m² pixels is realised. A digital architecture has been developed, with particle efficiency above 99.9% at 3 GHz/cm² pixel rate, 1 MHz trigger rate with 12.5 μ s latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision and the analog dead-time is below 1%. IP-blocks (DAC, ADC, BandGap, SER, sLVS-TX/RX) and very front ends are silicon proven, irradiated to 600-800Mrad.

We have designed and fabricated a compact array-based optical engine for transmitting data at 10 Gb/s. The device consists of a 4-channel ASIC driving a VCSEL (Vertical Cavity Surface Emitting Laser) array in an optical package. The ASIC is designed using only core transistors in a 65 nm CMOS process to enhance the radiation-hardness. The ASIC contains an 8-bit DAC to control the bias and modulation currents of the individual channels in the VCSEL array. The DAC settings are stored in SEU (single event upset) tolerant registers. Several devices were irradiated with 24 GeV/c protons and the performance of the devices is satisfactory after the irradiation.

We present a measurement of the charged particle reconstruction inefficiency inside of jet cores, using data collected by the ATLAS experiment in 2015 of pp collisions produced at the LHC, at a center-of-mass energy of 13 TeV . The determination of this inefficiency is important for jet energy scale and mass calibration, as well as multiple other performance studies and analyses. A data driven method is used, where the fraction of lost particle tracks is determined from energy deposition dE/dx in the pixel detector. The fraction of lost tracks is found to be less than 5%, which is an improvement since the previous study, and agrees well within systematic uncertainties with a Monte Carlo simulation.

The ALICE experiment at the CERN LHC is designed to study the physics of strongly interacting matter, and in particular the properties of the Quark-Gluon Plasma, using proton-proton, proton-nucleus and nucleus-nucleus collisions. The ALICE collaboration is preparing a major upgrade of the experimental apparatus to be installed during the second long LHC shutdown in the years 2019–2020. A key element of the ALICE upgrade is the new, ultra-light, high-resolution Inner Tracking System. With respect to the current detector, the new Inner Tracking System will significantly enhance the pointing resolution, the tracking efficiency at low transverse momenta, and the read-out rate capabilities. This will be obtained by seven concentric detector layers based on a Monolithic Active Pixel Sensor with a pixel pitch of about 30×30 μm². A key feature of the new Inner Tracking System, which is optimised for high tracking accuracy at low transverse momenta, is the very low mass of the three innermost layers, which feature a material budget of 0.3% X₀ per layer. This contribution presents the design goals and layout of the upgraded ALICE Inner Tracking System, summarises the R&D activities focussing on the technical implementation of the main detector components, and the projected detector performance.

The ATLAS Insertable B-Layer (IBL) is the innermost layer of pixel detectors, and was installed in May 2014 at a radius of 3.3 cm from the beam axis, between the existing Pixel detector and a new smaller radius beam-pipe. The new detector, built to cope with high radiation and occupancy, is the first large scale application of 3D sensors and CMOS 130 nm technology. The IBL detector construction was completed within about two years (2012 – 2014), and the key features and challenges met during the IBL project are presented, as well as its commissioning and operational experience at the LHC.

Detailed studies of the resolution of a EUDET-type beam telescope are carried out using the DATURA beam telescope as an example. The EUDET-type beam telescopes make use of CMOS MIMOSA 26 pixel detectors for particle tracking allowing for precise characterisation of particle-sensing devices. A profound understanding of the performance of the beam telescope as a whole is obtained by a detailed characterisation of the sensors themselves. The differential intrinsic resolution as measured in a MIMOSA 26 sensor is extracted using an iterative pull method, and various quantities that depend on the size of the cluster produced by a traversing charged particle are discussed: the residual distribution, the intra-pixel residual-width distribution and the intra-pixel density distribution of track incident positions.

A number of new types of pixel detector systems have been pioneered in the last decade. These include new types of sensors as well as new electronics to allow much higher performance. At the same time new experiments are being planned or nearing completion covering a broad range of physics topics in flavour physics as well as large major upgrades at the LHC. These are planning to make use of the advances in pixel detectors in important ways. In this review both the pixel advances and how they enable the physics will be presented.

This project focuses on a hybrid silicon pixel detector for Computed Tomography. In order to improve the attenuation efficiency of silicon for high energies, the active volume per unit area is increased by using the detector in edge-on configuration. In this geometry the sensor is illuminated from the side, with the pixel matrix parallel to the X-ray beam direction. Our setup consists of a 500 μm thick silicon sensor, bump-bonded to a chip from the Medipix family. Aim of the project is to test the feasibility of this geometry, finding its benefits and limitations. In particular, in this paper we show an important advantage of this configuration: energy discrimination along the detector depth. We propose a method to exploit this information, by including the beam hardening model both in the forward and in the backprojector of an iterative reconstruction algorithm. The first results, obtained on simulated data, show convergence and prove the feasibility of such an approach.

Is it possible to design a detector able to concurrently measure time and position with high precision? This question is at the root of the research and development of silicon sensors presented in this contribution. Silicon sensors are the most common type of particle detectors used for charged particle tracking, however their rather poor time resolution limits their use as precise timing detectors. A few years ago we have picked up the gantlet of enhancing the remarkable position resolution of silicon sensors with precise timing capability. I will be presenting our results in the following pages.

The Ultra Fast Silicon Detectors (UFSD) are a novel concept of silicon detectors based on the Low Gain Avalanche Diode (LGAD) technology, which are able to obtain time resolution of the order of few tens of picoseconds. First prototypes with different geometries (pads/pixels/strips), thickness (300 and 50 μm) and gain (between 5 and 20) have been recently designed and manufactured by CNM (Centro Nacional de Microelectrónica, Barcelona) and FBK (Fondazione Bruno Kessler, Trento). Several measurements on these devices have been performed in laboratory and in beam test and a dependence of the gain on the temperature has been observed. Some of the first measurements will be shown (leakage current, breakdown voltage, gain and time resolution on the 300 μm from FBK and gain on the 50 μm-thick sensor from CNM) and a comparison with the theoretically predicted trend will be discussed.

The pixel detector of the CMS experiment will be replaced in an extended end-of-year shutdown during winter 2016/2017 with an upgraded one able to cope with peak instantaneous luminosities beyond the nominal LHC instantaneous luminosity of 1 × 10³⁴ cm⁻² s⁻¹. Under the conditions expected in the coming years, which will see an increase of a factor two in instantaneous luminosity, the present system would experience a dynamic inefficiency caused mainly by data losses due to buffer overflows. The Phase I upgrade of the CMS pixel detector, described in this paper, will operate at full efficiency at an instantaneous luminosity of 2 × 10³⁴ cm⁻² s⁻¹ and beyond, thanks to a new readout chip. The new detector will feature one additional tracking point both in the barrel and in the forward regions, while reducing the material budget as a result of a new CO₂ cooling system and optimised layout of the services. In this paper, the design and the technological choices of the Phase I detector will be reviewed and the status of the construction of the detector and the performance of its components will be discussed.

The upcoming Mu3e experiment will search for the charged lepton flavour violating decay of a muon at rest into three electrons. The maximal energy of the electrons is 53 MeV, hence a low material budget is a key performance requirement for the tracking detector. In this paper we summarize our approach to meet the requirement of about 1 ‰ of a radiation length per pixel detector layer. This includes the choice of thinned active monolithic pixel sensors in HV-CMOS technology, ultra-thin flexible printed circuits, and helium gas cooling.

The full exploitation of the physics potential of the high luminosity LHC is a big challenge that requires new instrumentation and innovative solutions. We present here a conceptual design and simulation studies of a fast timing pixel detector with embedded real-time tracking capabilities. The system is conceived to operate at 40 MHz event rate and to reconstruct tracks in real-time, using precise space and time 4D information of the hit, for fast trigger decisions. This work is part of an R&D project aimed at building an innovative tracking detector with superior time (10 ps) and position (10 μm) resolutions to be used in very harsh radiation environments, for the ultimate flavour physics experiment at the high luminosity phase of the LHC.

The physics aims at the future CLIC high-energy linear e+e- collider set very high precision requirements on the performance of the vertex and tracking detectors. Moreover, these detectors have to be well adapted to the experimental conditions, such as the time structure of the collisions and the presence of beam-induced backgrounds. The principal challenges are: a point resolution of a few μm, ultra-low mass (∼ 0.2%X₀ per layer for the vertex region and ∼ 1%X₀ per layer for the outer tracker), very low power dissipation (compatible with air-flow cooling in the inner vertex region) and pulsed power operation, complemented with ∼ 10 ns time stamping capabilities. A highly granular all-silicon vertex and tracking detector system is under development, following an integrated approach addressing simultaneously the physics requirements and engineering constraints. For the vertex-detector region, hybrid pixel detectors with small pitch (25 μm) and analog readout are explored. For the outer tracking region, both hybrid concepts and fully integrated CMOS sensors are under consideration. The feasibility of ultra-thin sensor layers is validated with Timepix3 readout ASICs bump bonded to active edge planar sensors with 50 μm to 150 μm thickness. Prototypes of CLICpix readout ASICs implemented in 6525 nm CMOS technology with 25 μm pixel pitch have been produced. Hybridisation concepts have been developed for interconnecting these chips either through capacitive coupling to active HV-CMOS sensors or through bump-bonding to planar sensors. Recent R&D achievements include results from beam tests with all types of hybrid assemblies. Simulations based on Geant4 and TCAD are used to validate the experimental results and to assess and optimise the performance of various detector designs.

This paper presents the first pixel detector realized using the BCD8 technology of STMicroelectronics. The BCD8 is a 160 nm process with bipolar, CMOS and DMOS devices; mainly targeted for an automotive application. The silicon particle detector is realized as a pixel sensor diode with a dimension of 250 × 50 μm². To support the signal sensitivity of pixel diode, the circuit simulations have been performed with a substrate voltage of 50 V. The analog signal processing circuitry and the digital operation of the circuit is designed with the supply voltage of 1.8 V. Moreover, an analog processing part of the pixel detector circuit is confined in a unit pixel (diode sensor) to achieve 100 % fill factor. As a first phase of the design, an array of 8 pixels and 4 passive diodes have been designed and measured experimentally. The entire analog circuitry including passive diodes is implemented in a single chip. This chip has been tested experimentally with 70 V voltage capability, to evaluate its suitability. The sensor on a 125 Ωcm resistivity substrate has been characterized in the laboratory. The CMOS sensor realizes a depleted region of several tens of micrometer. The characterization shows a uniform breakdown at 70 V before irradiation and an approximate capacitance of 80 fF at 50 V of reverse bias voltage. The response to ionizing radiation is tested using radioactive sources and an X-ray tube.

ATLAS is a multipurpose experiment at the LHC proton-proton collider. Its physics goals require an unbiased and high resolution measurement of the charged particle kinematic parameters. These critically depend on the layout and performance of the tracking system and the quality of the alignment of its components. For the LHC Run 2, the system has been upgraded with the installation of a new pixel layer, the Insertable B-layer (IBL) . ATLAS Inner Detector alignment framework has been adapted and upgraded to correct very short time scale movements of the sub-detectors. In particular, a mechanical distortion of the IBL staves up to 20 μm and a vertical displacement of the Pixel detector of ∼ 6 μm have been observed during data-taking. The techniques used to correct for these effects and to match the required Inner Detector performance will be presented.

This work is concerned with the design of a readout chip for application to experiments at the next generation X-ray Free Electron Lasers (FEL). The ASIC, named PixFEL Matrix (PFM2), has been designed in a 65 nm CMOS technology and consists of 32 × 32 pixels. Each cell covers an area of 110 × 110 μm² and includes a low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time-variant shaper used to process the preamplifier output signal, a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) and digital circuitry for channel control and data readout. Two different solutions for the readout channel, based on different versions of the time-variant filter, have been integrated in the chip. Both solutions can be operated in such a way to cope with the high frame rate (exceeding 1 MHz) foreseen for future X-ray FEL machines. The ASIC will be bump bonded to a slim/active edge pixel sensor to form the first demonstrator for the PixFEL X-ray imager. This work has been carried out in the frame of the PixFEL project funded by Istituto Nazionale di Fisica Nucleare (INFN), Italy.

With the ability to attribute signatures of ionising radiation to certain particle types, pixel detectors offer a unique advantage over the traditional use of Geiger-Müller tubes also in educational settings. We demonstrate in this work how a Timepix readout chip combined with a standard 300μm pixelated silicon sensor can be used to visualise radioactivity in real-time and by means of augmented reality. The chip family is the result of technology transfer from High Energy Physics at CERN and facilitated by the Medipix Collaboration. This article summarises the development of a prototype based on an iPad mini and open source software detailed in ref. [1]. Appropriate experimental activities that explore natural radioactivity and everyday objects are given to demonstrate the use of this new tool in educational settings.

The MuPix7 chip is a monolithic HV-CMOS pixel chip, thinned down to 50 μm. It provides continuous self-triggered, non-shuttered readout at rates up to 30,Mhits/chip of 3 × 3 mm² active area and a pixel size of 103 × 80 μm². The hit efficiency depends on the chosen working point. Settings with a power consumption of 300 mW/cm² allow for a hit efficiency > 99.5%. A time resolution of 14.2 ns (Gaussian sigma) is achieved. Latest results from 2016 test beam campaigns are shown.

The ATLAS Pixel Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of data taking, an increase of the low-voltage current of the FE-I4 chip was measured. This increase was traced back to radiation damage in the chip. The dependence of the current from the Total Ionising Dose (TID) and temperature has been tested with X-ray irradiations. This paper presents the measurement results and gives a parameterisation of the leakage current and detector operation guidelines.

The CMS-TOTEM Precision Proton Spectrometer (CT-PPS) detector will be installed in Roman pots (RP) positioned on either side of CMS, at about 210 m from the interaction point. This detector will measure leading protons, allowing detailed studies of diffractive physics and central exclusive production in standard LHC running conditions. An essential component of the CT-PPS apparatus is the tracking system, which consists of two detector stations per arm equipped with six 3D silicon pixel-sensor modules, each read out by six PSI46dig chips. The front-end electronics has been designed to fulfill the mechanical constraints of the RP and to be compatible as much as possible with the readout chain of the CMS pixel detector. The tracking system is currently under construction and will be installed by the end of 2016. In this contribution the final design and the expected performance of the CT-PPS tracking system is presented. A summary of the studies performed, before and after irradiation, on the 3D detectors produced for CT-PPS is given.

The upgrade of the ALICE vertex detector, the Inner Tracking System (ITS), is scheduled to be installed during the next long shutdown period (2019-2020) of the CERN Large Hadron Collider (LHC) . The current ITS will be replaced by seven concentric layers of Monolithic Active Pixel Sensors (MAPS) with total active surface of ∼10 m², thus making ALICE the first LHC experiment implementing MAPS detector technology on a large scale. The ALPIDE chip, based on TowerJazz 180 nm CMOS Imaging Process, is being developed for this purpose. A particular process feature, the deep p-well, is exploited so the full CMOS logic can be implemented over the active sensor area without impinging on the deposited charge collection. ALPIDE is implemented on silicon wafers with a high resistivity epitaxial layer. A single chip measures 15 mm by 30 mm and contains half a million pixels distributed in 512 rows and 1024 columns. In-pixel circuitry features amplification, shaping, discrimination and multi-event buffering. The readout is hit driven i.e. only addresses of hit pixels are sent to the periphery. The upgrade of the ITS presents two different sets of requirements for sensors of the inner and of the outer layers due to the significantly different track density, radiation level and active detector surface. The ALPIDE chip fulfils the stringent requirements in both cases. The detection efficiency is higher than 99%, fake-hit probability is orders of magnitude lower than the required 10⁻⁶ and spatial resolution within the required 5 μm. This performance is to be maintained even after a total ionising does (TID) of 2.7 Mrad and a non-ionising energy loss (NIEL) fluence of 1.7 × 10¹³ 1 MeV n_eq/cm², which is above what is expected during the detector lifetime. Readout rate of 100 kHz is provided and the power density of ALPIDE is less than 40 mW/cm². This contribution will provide a summary of the ALPIDE features and main test results.

3D silicon pixel detectors have been investigated as radiation-hard candidates for the innermost layers of the HL-LHC upgrade of the ATLAS pixel detector. 3D detectors are already in use today in the ATLAS IBL and AFP experiments. These are based on 50 × 250 μm² large pixels connected to the FE-I4 readout chip. Detectors of this generation were irradiated to HL-LHC fluences and demonstrated excellent radiation hardness with operational voltages as low as 180 V and power dissipation of 12–15 mW/cm² at a fluence of about 10¹⁶ n_eq/cm², measured at -25°C. Moreover, to cope with the higher occupancies expected at the HL-LHC, a first run of a new generation of 3D detectors designed for the HL-LHC was produced at CNM with small pixel sizes of 50 × 50 and 25 × 100 μm², matched to the FE-I4 chip. They demonstrated a good performance in the laboratory and in beam tests with hit efficiencies of about 97% at already 1–2 V before irradiation.

The upgrade of the LHC to the HL-LHC requires a new ITk detector. The innermost part of this new tracker is a pixel detector. The University of Wuppertal is developing a new DCS to monitor and control this new pixel detector. The current concept envisions three parallel paths of the DCS. The first path, called security path, is hardwired and provides an interlock system to guarantee the safety of the detector and human beings. The second path is a control path. This path is used to supervise the entire detector. The control path has its own communication lines independent from the regular data readout for reliable operation. The third path is for diagnostics and provides information on demand. It is merged with the regular data readout and provides the highest granularity and most detailed information. To reduce the material budget, a serial power scheme is the baseline for the pixel modules. A new ASIC used in the control path is in development at Wuppertal for this serial power chain. A prototype exists already and a proof of principle was demonstrated. Development and research is ongoing to guarantee the correct operation of the new ASIC in the harsh environment of the HL-LHC. The concept for the new DCS will be presented in this paper. A focus will be made on the development of the DCS chip, used for monitoring and control of pixel modules in a serial power chain.