Workshop on Intelligent Trackers (WIT2014)

We present a novel dual-source/dual energy (DSCT/DECT) micro-tomography system including results of high-resolution DSCT reconstruction. The DSCT micro-tomography setup was designed as a multi-purpose X-ray imaging device equipped with two pairs of X-ray tubes and detectors in orthogonal arrangement with independent control of beam parameters. Both pairs (tube-detector) are mounted on a computer numerical control positioning system and can be independently set up to different geometries (e.g. with different magnification of each pair). In this work the simultaneous scanning of the object by two tube-detector pairs was used for approximately half reduction of tomography scanning time. The developed imaging procedure was applied for scanning of a wooden sample locally damaged during a semi-destructive test for assessment of wood quality. Prior to the tomography measurements the setup geometry was precisely adjusted in terms of magnification, horizontal and vertical tube-specimen-detector alignment of both pairs. DSCT measurements were carried out in sequence (2 × 90° for each tube) with identical 100μm image resolution. It was proven that the presented experimental setup combined with appropriate control technique significantly reduces tomography scanning time of materials with complex micro-structure.

We present results of an R&D study for a specialized processor capable of precisely reconstructing, in pixel detectors, hundreds of charged-particle tracks from high-energy collisions at 40 MHz rate. We apply a highly parallel pattern-recognition algorithm, inspired by studies of the processing of visual images by the brain as it happens in nature, and describe in detail an efficient hardware implementation in high-speed, high-bandwidth FPGA devices. This is the first detailed demonstration of reconstruction of offline-quality tracks at 40 MHz and makes the device suitable for processing Large Hadron Collider events at the full crossing frequency.

We present the results of a detailed simulation of the artificial retina pattern-recognition algorithm, designed to reconstruct events with hundreds of charged-particle tracks in pixel and silicon detectors at LHCb with LHC crossing frequency of 40 MHz. Performances of the artificial retina algorithm are assessed using the official Monte Carlo samples of the LHCb experiment. We found performances for the retina pattern-recognition algorithm comparable with the full LHCb reconstruction algorithm.

The ABC 130 chip developed for the high luminosity LHC(HL-LHC) upgrade of the ATLAS silicon strip tracker implements a Fast Cluster Finder (FCF). The FCF is capable of reading out certain track cluster information serially with a clock rate up to 640 MHz, sufficient to output the location within the 40 MHz collision frequency. An external correlator circuit can be used to find the position coincidence of clusters at two adjacent layers of silicon sensor. The coincidence offset is related to the transverse momentum of the track, and therefore it provides information which may contribute to a Level-1 trigger decision. These circuit elements have been implemented in a sensor doublet configuration coupled to an FPGA which executes the correlator algorithm. Design and test results of this system are presented.

A new fast track reconstruction algorithm developed for the high track multiplicity environment of the Mu3e experiment where track uncertainties are dominated by multiple scattering is presented.

The goal of the Mu3e experiment is to search for the LFV decay μ⁺ → e⁺e⁻e⁺. To reach the sensitivity of 10^-16 the experiment will be performed at a future high intensity beam line (HiMB) at the Paul-Scherrer Institute (Switzerland) providing more than 10⁹ muons per second. Muons with a momentum of about 28 MeV/c are stopped on a target. Their decay at rest, in which mainly low momentum electrons with energies below 53 MeV are produced, is measured by the Mu3e tracking detector consisting of four cylindrical layers of thin silicon pixel sensors. The high granularity of the pixel detector with a pixel size of 80 × 80 μm² allows for precise track reconstruction in the high occupancy environment of the Mu3e experiment reaching up to 100 tracks per readout frame of 50 ns. These tracks will be reconstructed online using a trigger-less readout scheme. The implementation of a fast 3-dimensional multiple scattering fit based on hit triplets, where spatial uncertainties are ignored, is described and performance results in the context of Mu3e experiment are presented. Also the implementation on Graphics Processor Units (GPUs) for fast online reconstruction is discussed.

We present a set of links based on data-transmission IP in 130nm designed for rapid integration into ASIC designs. These links are designed for use in very high radiation environments as occur in high energy physics experiments. The designs are additionally low power and small area, easing integration with other electronic systems. These links are well suited to use in tracking detectors. Trackers, due to their close proximity to the collision, are subject to very high levels of radiation, and hence require such radiation hardened electronics. The portfolio of radiation hardened data transmission blocks consists of a 1Gbps serializer/deserializer with a very low power consumption ^~1mW for each. A differential transmitter and differential receiver rated at 3GHz, both designed to be much faster than needed, as insurance against radiation damage. Finally, the impact of a prototype low-latency, low-power ( < 60mW total link power) 5Gbps link is considered. Case analysis of the impacts of using lower powered, higher speed blocks in hypothetical trackers is studied, showing power improvements relative to alternative technologies.

One of the proposed solutions currently under study in Compact Muon Solenoid (CMS) collaboration [1] to reconstruct tracks at the first level trigger (L1) for the High Luminosity - Large Hadron Collider (HL-LHC) is based on the usage of Associative Memory [2] (AM) chips. The tracker information is first reduced to suppress low p_T tracks and sent to boards equipped with AM chips. Each AM compares the tracker information with pre-calculated expectations (pattern matching) in a very short time (order of a μs), therefore providing a solution to the challenging computational problem of pattern recognition in a very busy environment. Associated to fast track fit methods, like the Hough transform, the AM approach should be able to fulfil the very demanding requirements of L1 tracking. The proposed architecture for the AM-based L1 track reconstruction system will be presented, together with the latest results obtained using a complete software emulation of this system.

The CMS tracker at HL-LHC is required to provide prompt information on particles with high transverse momentum to the central Level 1 trigger. For this purpose, the innermost part of the outer tracker is based on a combination of a pixelated sensor with a short strip sensor, the so-called Pixel-Strip module (PS). The readout of these sensors is carried out by distinct ASICs, the Strip Sensor ASIC (SSA), for the strip layer, and the Macro Pixel ASIC (MPA) for the pixel layer. The processing of the data directly on the front-end module represents a design challenge due to the large data volume (30720 pixels and 1920 strips per module) and the limited power budget. This is the reason why several studies have been carried out to find the best compromise between ASICs performance and power consumption. This paper describes the current status of the MPA ASIC development where the logic for generating prompt information on particles with high transverse momentum is implemented. An overview of the readout method is presented with particular attention on the cluster reduction, position encoding and momentum discrimination logic. Concerning the architectural studies, a software test bench capable of reading physics Monte-Carlo generated events has been developed and used to validate the MPA design and to evaluate the MPA performance. The MPA-Light is scheduled to be submitted for fabrication this year and will include the full analog functions and a part of the digital logic of the final version in order to qualify the chosen VLSI technology for the analog front-end, the module assembly and the low voltage digital supply.

ATLAS is proposing to replace the entire tracking system for HL-LHC operation. The ``Letter of Intent'' baseline pixel size at higher radii was 50 × 250μm<sup>2</sup> (φ × η), based on the FE-I4 readout chip, and this was optimized for the central barrel region. The detector tracking performance in the end-cap pixel disks can benefit from enhanced resolution in the radial direction to improve the impact parameter resolution in z-coordinate (along the beam line) for high η tracks, which is critical in the high pile-up environment of the HL-LHC. So called ``strixel'' geometries, with long narrow pixels, can be proposed at higher z in the barrel where tracks pass through at large angles. Larger pixels may also be considered for an additional pixel layer if this could reduce the requirements, and therefore costs, for the outer part of the tracker.

While ATLAS pixel upgrade plans are evolving, the demonstration of providing a variety of sensor pixel shapes and sizes for a common ASIC pixel geometry will be of general application, whatever the final ASIC design.

This paper will report on the development and testing of pixel sensors with several different dimensions assembled into modules with the FE-I4 readout chip. Some of these were irradiated (with protons, 10¹⁵ n_eq/cm²) and evaluated at the DESY test beam. These, together with the test beam results with non-irradiated sensors, will be shown, as well as the results from laboratory characterization.

Wireless data transfer has revolutionized the consumer market for the last decade generating many products equipped with transmitters and receivers for wireless data transfer. Wireless technology opens attractive possibilities for data transfer in future tracking detectors. The reduction of wires and connectors for data links is certainly beneficial both for the material budget and the reliability of the system. An advantage of wireless data transfer is the freedom of routing signals which today is particularly complicated when bringing the data the first 50 cm out of the tracker. With wireless links intelligence can be built into a tracker by introducing communication between tracking layers within a region of interest which would allow the construction of track primitives in real time.

The wireless technology used in consumer products is however not suitable for tracker readouts. The low data transfer capacity of current 5 GHz transceivers and the relatively large feature sizes of the components is a disadvantage.Due to the requirement of high data rates in tracking detectors high bandwidth is required. The frequency band around 60 GHz turns out to be a very promising candidate for data transfer in a detector system. The high baseband frequency allows for data transfer in the order of several Gbit/s. Due to the small wavelength in the mm range only small structures are needed for the transmitting and receiving electronics. The 60 GHz frequency band is a strong candidate for future WLAN applications hence components are already starting to be available on the market.Patch antennas produced on flexible Printed Circuit Board substrate that can be used for wireless communication in future trackers are presented in this article. The antennas can be connected to transceivers for data transmission/reception or be connected by wave-guides to structures capable of bringing the 60 GHz signal behind boundaries. Results on simulation and fabrication of these antennas are presented as well as studies on the sensitivity of production tolerances.

The Fast TracKer (FTK) is an extremely powerful and very compact processing unit, essential for efficient Level 2 trigger selection in future high-energy physics experiments at the LHC. FTK employs Associative Memories (AM) to perform pattern recognition; input and output data are transmitted over serial links at 2 Gbit/s to reduce routing congestion at the board level. Prototypes of the AM chip and of the AM board have been manufactured and tested, in preparation of the imminent design of the final version.

Three dimensional integrated circuit technologies offer the possibility of fabricating large area arrays of sensors integrated with complex electronics with minimal dead area, which makes them ideally suited for applications at the LHC upgraded detectors and other future detectors. We describe ongoing R&D efforts to demonstrate functionality of components of such detectors. This includes the study of integrated 3D electronics with active edge sensors to produce "active tiles" which can be tested and assembled into arrays of arbitrary size with high yield.

To allow highly granular trackers to contribute to first level trigger decisions or event filtering, a fast readout system with very high bandwidth is required. Space, power and material constraints, however, pose severe limitations on the maximum available bandwidth of electrical or optical data transfers. A new approach for the implementation of a fast readout system is the application of a wireless data transfer at a carrier frequency of 60 GHz. The available bandwidth of several GHz allows for data rates of multiple Gbps per link. 60 GHz transceiver chips can be produced with a small form factor and a high integration level. A prototype transceiver currently under development at the University of Heidelberg is briefly described in this paper. To allow easy and fast future testing of the chip's functionality, a bit error rate test has been developed with a commercially available transceiver.

Crosstalk might be a big issue for a wireless readout system with many links in a tracking detector. Direct crosstalk can be avoided by using directive antennas, linearly polarized waves and frequency channeling. Reflections from tracking modules can be reduced by applying an absorbing material like graphite foam. Properties of different materials typically used in tracking detectors and graphite foam in the 60 GHz frequency range are presented. For data transmission tests, links using commercially available 60 GHz transmitters and receivers are used. Studies regarding crosstalk and the applicability of graphite foam, Kapton horn antennas and polarized waves are shown.

A new approach for track reconstruction is presented to be used in the all-hardware first level of the CMS trigger. The application of the approach is intended for the upgraded all-silicon tracker, which is to be installed for the High Luminosity era of the LHC (HL-LHC). The upgraded LHC machine is expected to deliver a luminosity on the order of 5 × 10³⁴ cm⁻²s⁻¹. This expected luminosity means there would be about 125 pileup events in each bunch crossing at a frequency of 40 MHz. To keep the CMS trigger rate at a manageable level under these conditions, it is necessary to make quick decisions on the events that will be processed. The timing estimates for the algorithm are expected to be below 5 μs, well within the requirements of the L1 trigger at CMS for track identification. The algorithm is integer-based, allowing it to be implemented on an FPGA. Currently we are working on a demonstrator hardware implementation using a Xilinx Virtex 6 FPGA. Results from simulations in C++ and Verilog are presented to show the algorithm performance in terms of data throughput and parameter resolution.

We propose to use silicon photonics technology to build radiation-hard fiber-optic links for high-bandwidth readout of tracking detectors. The CMOS integrated silicon photonics was developed by Luxtera and commercialized by Molex. The commercial off-the-shelf (COTS) fiber-optic links feature moderate radiation tolerance insufficient for trackers. A transceiver contains four RX and four TX channels operating at 10 Gbps each. The next generation will likely operate at 25 Gbps per channel. The approach uses a standard CMOS process and single-mode fibers, providing low power consumption and good scalability and reliability.

The High Luminosity LHC (HL-LHC) is expected to deliver luminosities of 5 × 10³⁴ c ^{-2 -1}, with an average number of overlapping proton-proton collisions per bunch crossing (pileup) of about 140. These extreme pileup conditions place stringent requirements on the experiments' trigger systems to cope with the resulting event rates. For the CMS experiment, a key component of the detector upgrade for the HL-LHC is a track-trigger system which would identify tracks with transverse momentum above 2 GeV already at the first-level (L1) trigger. Here, a proposal for implementing L1 tracking using ``tracklets" is presented. The expected performance of the L1 tracking from simulation studies and the use of L1 tracks to define trigger objects are discussed.

The CMS Tracker under development for the High Luminosity LHC includes an outer tracker based on ``PT-modules'' which will provide track stubs based on coincident clusters in two closely spaced sensor layers, aiming to reject low transverse momentum track hits before data transmission to the Level-1 trigger. The tracker data will be used to reconstruct track segments in dedicated processors before onward transmission to other trigger processors which will combine tracker information with data originating from the calorimeter and muon detectors, to make the final L1 trigger decision. The architecture for processing the tracker data is still an open question. One attractive option is to explore a Time Multiplexed design similar to one which is currently being implemented in the CMS calorimeter trigger as part of the Phase I trigger upgrade. The Time Multiplexed Trigger concept is explained, the potential benefits of applying it for processing future tracker data are described and a possible design based on currently existing hardware is presented.

The LHCb experiment will be upgraded between 2018 and 2019 in order to reach unprecedented precision on the measurements of the main observables of the beauty and charm quarks. This paper describes the trigger-less readout system foreseen for the upgrade.

The LHCb experiment will operate at a luminosity of 2 × 10³³ cm⁻²s⁻¹ during LHC Run 3. At this rate the present readout and hardware Level-0 trigger become a limitation, especially for fully hadronic final states. In order to maintain a high signal efficiency the upgraded LHCb detector will deploy two novel concepts: a triggerless readout and a full software trigger.

The hit combinatorial problem is a main challenge for track reconstruction and triggering at high rate experiments. At hadron colliders the dominant fraction of hits is due to low momentum tracks for which multiple scattering (MS) effects dominate the hit resolution. MS is also the dominating source for hit confusion and track uncertainties in low energy precision experiments. In all such environments, where MS dominates, track reconstruction and fitting can be largely simplified by using three-dimensional (3D) hit-triplets as provided by pixel detectors. This simplification is possible since track uncertainties are solely determined by MS if high precision spatial information is provided. Fitting of hit-triplets is especially simple for tracking detectors in solenoidal magnetic fields.

The over-constrained 3D-triplet method provides a complete set of track parameters and is robust against fake hit combinations. Full tracks can be reconstructed step-wise by connecting hit triplet combinations from different layers, thus heavily reducing the combinatorial problem and accelerating track linking.

The triplet method is ideally suited for pixel detectors where hits can be treated as 3D-space points. With the advent of relatively cheap and industrially available CMOS-sensors the construction of highly granular full scale pixel tracking detectors seems to be possible also for experiments at LHC or future high energy (hadron) colliders. In this paper tracking performance studies for full-scale pixel detectors, including their optimisation for 3D-triplet tracking, are presented. The results obtained for different types of tracker geometries and different reconstruction methods are compared. The potential of reducing the number of tracking layers and - along with that - the material budget using this new tracking concept is discussed. The possibility of using 3D-triplet tracking for triggering and fast online reconstruction is highlighted.

At the high luminosity HL-LHC, upwards of 140 individual proton-proton interactions (pileup) are expected per bunch-crossing at luminosities of around 5×10³⁴ cm^-2s^-1. A proposal by the ATLAS collaboration to split the ATLAS first level trigger in to two stages is briefly detailed. The use of fast track finding in the new first level trigger is explored as a method to provide the discrimination required to reduce the event rate to acceptable levels for the read out system while maintaining high efficiency on the selection of the decay products of electroweak bosons along with other high p_T physics signatures at HL-LHC luminosities. It is shown that the available bandwidth in the proposed new strip tracker is sufficient for a region of interest based track trigger given certain optimisations. Further methods for improving upon the proposal are discussed.

The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors from inner ATLAS read out drivers (RODs) at full rate, for total of 760Gbs, as sent by the RODs after level-1 triggers. Clustering serves two purposes, the first is to reduce the high rate of the received data before further processing, the second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The cluster detection window size can be adjusted for optimizing the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. This flexibility makes the implementation suitable for a variety of demanding image processing applications. The implementation is robust against bit errors in the input data stream and drops all data that cannot be identified. In the unlikely event of missing control words, the implementation will ensure stable data processing by inserting the missing control words in the data stream. The 2D pixel clustering implementation is developed and tested in both single flow and parallel versions. The first parallel version with 16 parallel cluster identification engines is presented. The input data from the RODs are received through S-Links and the processing units that follow the clustering implementation also require a single data stream, therefore data parallelizing (demultiplexing) and serializing (multiplexing) modules are introduced in order to accommodate the parallelized version and restore the data stream afterwards. The results of the first hardware tests of the single flow implementation on the custom FTK input mezzanine (IM) board are presented. We report on the integration of 16 parallel engines in the same FPGA and the resulting performances. The parallel 2D-clustering implementation has sufficient processing power to meet the specification for the Pixel layers of ATLAS, for up to 80 overlapping pp collisions that correspond to the maximum LHC luminosity planned until 2022.

This note summarizes the outcome of discussions about how data compression considerations apply to tracking detectors with local intelligence. The method for analyzing data compression efficiency is taken from a previous publication and applied to module characteristics from the WIT2014 workshop. We explore local intelligence and coupled layer structures in the language of data compression. In this context the original intelligent tracker concept of correlating hits to find matches of interest and discard others is just a form of lossy data compression. We now explore how these features (intelligence and coupled layers) can be exploited for lossless compression, which could enable full readout at higher trigger rates than previously envisioned, or even triggerless.