Germanium CMOS potential from material and process perspectives: Be more positive about germanium

GeO desorption from GeO₂ was directly investigated using thermal desorption spectroscopy (TDS) measurements^22,23) carried out in ultrahigh vacuum (UHV) at high temperatures,²⁴⁾ because GeO desorption from ultrathin GeO₂ on Ge in UHV was reported to occur at temperatures above 400 °C.²⁵⁾ In fact, GeO desorbs from the GeO₂/Ge stack at a relatively low temperature but, interestingly, not from GeO₂/SiO₂ stacks shown in Fig. 2. This indicates that the GeO desorption is directly related to a reaction that triggers GeO desorption at the GeO₂/Ge interface.

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Figure 3 shows both (a) schematic cross sections of a GeO₂ line-and-space pattern on Ge before and after UHV annealing and (b) the atomic force microscope (AFM) image of the pattern after UHV annealing.²⁶⁾ The Ge substrate is consumed only underneath GeO₂ lines, indicating that GeO desorption is caused by a GeO₂/Ge reaction. Another aspect of the GeO desorption is shown in Fig. 4, where (a) is a schematic image of a SiO₂ line-and-space pattern on Ge before N₂ annealing and (b) shows AFM cross-sectional images of the pattern before and after N₂ annealing at 600 °C.²⁶⁾ Since N₂ gas actually included a small amount of O₂, Ge was consumed only where it was not under SiO₂. This is a typical example of the active oxidation.

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Considering that GeO desorption is associated with the reaction at GeO₂/Ge as shown above, we suggest the following net reaction.

$$\begin{equation} \text{Ge}+\text{GeO$_{2}$}\leftrightarrow\text{2GeO} \end{equation} \tag{ 2.1 }$$

Next, let us think about what is the difference between Ge oxidation and Si oxidation thermodynamically. Vapor pressures of the volatile species Ge(g), GeO(g), and GeO₂(g) in the Ge-and-O₂ system as well as their Si counterparts in the Si-and-O₂ system under a thermodynamic equilibrium condition²⁷⁾ were first calculated using a thermodynamic database.²⁸⁾ The equilibrium vapor pressures of GeO(g), GeO₂(g), and Ge(g) (p-GeO, p-GeO₂, and p-Ge, respectively) are shown in Fig. 5(a) as a function of the p-O₂ at 550 °C. Similar reactions were calculated for Si at 900 °C, as shown in Fig. 5(b). The Si results are the same as reported elsewhere.²⁹⁾ Note that the system temperatures for both Ge and Si were ∼0.7 × T_M (T_M; melting temperature), which are typical temperatures used for the dry oxidation of these semiconductors. At p-O₂ < 10^−26.3 atm, GeO(g), GeO₂(g), and Ge(g) equilibrate with Ge(s) in the following reactions.

$$\begin{align} & \text{Ge(s)}+\text{1/2O$_{2}$(g)}=\text{GeO(g)},\\ & \text{Ge(s)}+\text{O$_{2}$(g)}=\text{GeO$_{2}$(g)},\\ & \text{Ge(s)}=\text{Ge(g)}. \end{align} \tag{ 2.2 }$$

GeO(g) and GeO₂(g) equilibrate with GeO₂(s) at p-O₂ > 10^−26.3 atm.

$$\begin{align} & \text{GeO$_{2}$(s)}=\text{GeO(g)}+\text{1/2O$_{2}$(g)},\\ & \text{GeO$_{2}$(s)}=\text{GeO$_{2}$(g)},\\ & \text{GeO$_{2}$(s)}=\text{Ge(g)}+\text{O$_{2}$(g)}. \end{align} \tag{ 2.3 }$$

Three important points in Fig. 5 are the following:

• (i)   
  p-GeO is the highest at the GeO₂/Ge interface up to p-O₂ ∼ 1 atm,
• (ii)   
  p-GeO has a negative slope against p-O₂, and
• (iii)   
  p-GeO is comparable with p-GeO₂ at p-O₂ ∼ 1 atm.

Looking at the p-O₂ ∼ 1 atm region in Fig. 5(a), one clearly sees that the p-GeO is much higher than that of SiO in Fig. 5(b), in addition to (iii). This means that GeO desorption from GeO₂/Ge observed experimentally is thermodynamically reasonable. Furthermore, a negative slope of p-GeO against p-O₂ suggests that GeO desorption from the surface may affect the region deep inside GeO₂ film and degrade both bulk and interface of GeO₂/Ge system. On the other hand, since p-GeO decreases with increase in p-O₂, the high-pressure O₂ oxidation might be effective for growing SiO₂-like GeO₂, which is discussed in the next section.

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Next, the GeO desorption kinetics is experimentally discussed. As shown in Fig. 6, the temperature giving a peak in TDS increases with the GeO₂ thickness increase, while it little depends on how GeO₂ is formed.³⁰⁾ This fact suggests that the GeO desorption is limited by diffusion through the bulk GeO₂ network. It might be, however, unlikely that GeO is the diffusion species. To clarify the diffusion species and mechanism, isotope tracing experiments using ¹⁸O and ⁷³Ge were carried out with TDS and secondary ion mass spectroscopy (SIMS).^{30) 73}Ge was used for these experiments because it is an only Ge isotope with an odd mass number and thus easier to trace in the marker experiments. Two kinds of gate stack structures focusing on ¹⁸O and ⁷³Ge were prepared, as shown in Fig. 7(a). The Ge¹⁶O is desorbed at a lower temperature, as shown in Fig. 7(b), which suggests that O of desorbed GeO is not from the interface but from the top layer. It was also suggested that Ge of desorbed GeO was also from the top layer (data not shown). Results point out that both Ge and O are desorbed from the top surface of GeO₂ at the initial stage in the temperature sweep. This initial desorption from the top layer seems inconsistent with GeO desorption being triggered by the GeO₂/Ge reaction as discussed previously. However, it is understandable by considering that the oxygen atom diffuses from the top layer toward the interface, namely, oxygen vacancy (V_o) diffusion from the GeO₂/Ge interface to the top surface. To determine the actual diffusion species through the GeO₂ film, the sample structure shown in Fig. 8(a) was prepared using both ⁷³Ge and ¹⁸O, and then annealed at 600 and 650 °C. Figures 8(b) and 8(c) show that the O atom is the dominant diffusion species in GeO₂.³⁰⁾ It is actually regarded that V_o is formed through the reaction at the interface,

$$\begin{equation} \text{Ge}+\text{GeO$_{2}$}\rightarrow\text{2GeO$_{2}$}+\text{2V$_{\text{o}}$}. \end{equation} \tag{ 2.4 }$$

Namely, the Ge substrate is oxidized by GeO₂ at the interface, while at the surface,

$$\begin{equation} \text{GeO$_{2}$}+\text{V}_{\text{o}}\rightarrow\text{GeO$\uparrow$}. \end{equation} \tag{ 2.5 }$$

In the net reaction,

$$\begin{equation} \text{Ge}+\text{GeO$_{2}$}\rightarrow\text{2GeO$\uparrow$}. \end{equation} \tag{ 2.6 }$$

The V_o formation triggered by the oxidation in (2.4) drives GeO desorption through the V_o diffusion.³⁰⁾ Figure 9 is more intuitively helpful to understand what occurs inside the GeO₂ film on a Ge substrate. This kinetic view is the key concept when we treat GeO₂/Ge gate stacks.

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GeO₂ film properties were affected by UHV annealing through the above process. Figures 10(a) (X-ray diffraction, XRD) and 10(b) (transmission electron microscope, TEM)³¹⁾ show that GeO₂ on Ge in UHV-annealing at 660 °C is crystallized to an α-quartz type structure.³²⁾ This is also understandable by considering the reduction in the crystallization barrier energy with the help of the V_o diffusion in GeO₂. This seems quite interesting from the viewpoint that V_o's make the continuous random network (CRN) type of GeO₂ structure unstable. In fact, if oxygen atom diffusion can follow the V_o diffusion instantaneously, GeO desorption associated with V_o diffusion may be observed. However, if huge amounts of V_o's are generated under the UHV condition, it is likely that the CRN structure of the GeO₂ film may be collapsed and crystallized locally. Those properties in GeO₂/Ge are quite different from those in SiO₂/Si stacks and, as discussed later, are tightly related to the GeO₂ physical properties.

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Because oxygen vacancies are always involved both at the interface and in the bulk GeO₂, we have to suppress the GeO desorption if we wish to make excellent gate stacks on Ge. There are basically two ways of solving this problem: thermodynamically and kinetically. The kinetic approach was actually carried out first, but we start with discussing the thermodynamic approach, because the thermodynamic one has been more successful and investigated in much more detail. The kinetic one is discussed in Sect. 2.3, after which the material approach combining both of them is discussed in Sect. 2.4.

2.2.1. High-pressure O₂ oxidation.

We first tried to form GeO₂ thermally under 1 atm O₂ but were not satisfied with the results. We naively conjectured that the high-pressure O₂ (HPO) oxidation might be effective for suppressing the GeO desorption because we thought enough O₂ could reduce the amount of insufficiently oxidized GeO_x in the film. Therefore, before considering the thermodynamics of Ge oxidation as described in Sect. 2.1, we carried out the oxidation of Ge in a high-pressure O₂ ambient. Since it was not possible to use the conventional quartz furnace for the oxidation at pressures above 10 atm, a stainless chamber with a quartz tube as the inner wall was used for the oxidation as shown in Fig. 11(a). Then, a SUS tube was directly put into the conventional open furnace. The schematic image of the oxidation system is shown in Fig. 11(b). Since it was a very simple system, the actual p-O₂ in it could not be directly measured at elevated temperatures. However, because the p-O₂ measured after the oxidation was the same as the initial p-O₂, only a very slight O₂ leakage (if any) in this process was confirmed and the actual p-O₂ was estimated according to the Boyle-Charles's law. The p-O₂ at the oxidation temperature around 600 °C was estimated from the typical p-O₂ of ∼70 atm at room temperature to be roughly 200 atm. p-O₂ in this paper is hereafter denoted by the room-temperature p-O₂. Although this tube is obviously not suitable for use in the industrial-scale production, we have learned much from these experiments. Very fortunately, in the first HPO experiment, we were able to demonstrate surprisingly good MOS capacitor characteristics with HPO-grown GeO₂ on Ge.³³⁾ Details of electrical characteristics are discussed in the next section.

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Low-temperature HPO of Si at pressures up to 500 atm was reported a couple of decades ago to prepare high-density SiO₂ films of sufficient thickness.³⁴⁾ Later, a more practical furnace was used to study the HPO oxidation of Si at pressures up to 10 atm in a quartz tube.³⁵⁾ Although we did not know that high-pressure O₂ oxidation of Ge was carried out in the early 80's by Crisman and coworkers,^36,37) before our first demonstration of significantly improved capacitance–voltage (C–V) characteristics in HPO-grown GeO₂/Ge gate stacks,³³⁾ they surprisingly demonstrated Ge gate stack improvement by using very high pressure O₂ gas. Therefore, we should appreciate their original work on the HPO oxidation of Ge.

2.2.2. GeO₂/Ge MOS capacitors.

As expected from the thermodynamic consideration discussed previously, the HPO of Ge dramatically improved the Ge MOS capacitor characteristics.³⁸⁾ Furthermore, because the C–V characteristics of HPO-grown GeO₂/Ge MOS capacitors showed a slight hysteresis, we tried to annihilate the interface defects by post-oxidation annealing (POA) at a lower temperature (400 °C). This POA was carried out using H₂, N₂, and O₂. As seen when comparing Figs. 12(a) and 12(b), we found that O₂ POA at a lower temperature was quite effective in improving C–V characteristics.³⁹⁾ Hereafter, we call it low-temperature oxygen annealing (LOA). The LOA was actually carried out at 400 °C in 1 atm O₂ after the formation of high-quality bulk GeO₂ by HPO at 550 °C. This process is hereafter called HPO+LOA.

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The effectiveness of LOA was also thermodynamically justified as follows. Note that the p-GeO at the GeO₂/Ge interface is thermodynamically fixed, independent of the p-O₂ at a given temperature, because of the Gibbs's phase rule. Interface properties can therefore be further improved, without degrading bulk GeO₂ properties, by lowering the temperature. It was actually confirmed by the calculation that p-GeO was decreased by lowering the temperature in 1 atm O₂.²⁷⁾ This means that improving MOS C–V characteristics by LOA in Fig. 12(b) is thermodynamically reasonable. Thus, it is concluded with confidence that the wonderful MOS gate stacks on Ge can be made by suppressing the GeO desorption from GeO₂/Ge gate stacks.

Next, we quantify how the interface is improved by estimating the interface state density D_it. Those who are not familiar with the C–V characteristics of Ge MOS capacitors might think that the minority carrier response in the inversion region at low frequencies in Fig. 12 is huge and that D_it should be high. This is not true. It is due to the intrinsic bulk minority carrier response in the Ge bulk with the narrower energy band gap. This means that characterization methods usually available for estimating the D_it in Si MOS capacitors cannot be used in Ge cases. For example, the conductance method in which the minority carrier capture and emission only from interface states are assumed⁴⁰⁾ is widely used for estimating the D_it spectrum in Si MOS capacitors quantitatively. In the C–V characterization of Ge MOS capacitors, however, the bulk minority carrier generation needs to be taken into account. Therefore, if we apply the normal conductance method to Ge MOS capacitors at room temperature, we would have a big error in the D_it estimation. There are two ways to overcome this difficulty. One is to lower the measurement temperature, because lowering the temperature must reduce the minority carrier generation in the bulk exponentially. The other is to develop a new equivalent circuit model to describe Ge MOS capacitor characteristics at room temperature. The equivalent circuit was carefully developed by Fukuda et al.⁴¹⁾ and Martens et al.⁴²⁾ We employed the former method because it was experimentally straightforward.

Figure 13 shows D_it profiles estimated by the conductance method. They are the profiles estimated at 200 and 100 K in MOS capacitors with GeO₂/Ge(100) grown both by HPO and by HPO+LOA. The midgap D_it is on the order of 10¹⁰ cm⁻² eV⁻¹ in HPO+LOA,³⁹⁾ which is to our knowledge the lowest of midgap D_it values so far reported for Ge gate stacks. Note that forming gas annealing (FGA) was not employed for reducing D_it. The reason why the oxidation process can make Ge interface quality so remarkable may be that Ge–O bonds at the GeO₂/Ge interface are more flexible than Si–O bonds at the SiO₂/Si interface. Therefore we regard the LOA as the self-passivation of the GeO₂/Ge interface by oxygen itself rather than H₂ gas in FGA. The effectiveness of aforementioned oxidation process may also be understandable in conjunction with the viscoelastic properties of GeO₂.⁴³⁾

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The FGA effect on GeO₂/Ge interfaces is still under debate in related conferences. Our experiments have never shown any D_it improvements in the FGA, although annealing temperature effects have been observed occasionally. It was also reported that H-terminated Ge(100) was unstable.⁴⁴⁾ However, hydrogen is a tricky atom, so we need to carefully investigate it in more detail, including deuterium or radical effects.⁴⁵⁾

The surface orientation of the substrate is always an issue in surface channel FETs in terms of both process stability and carrier mobility. Since the carrier mobility is discussed in Sect. 3.2, the process sensitivity and MOS capacitor characteristics are addressed here. The oxidation rates of Ge(100) and (111) under 1 atm O₂ at 600 °C are shown in Fig. 14 as a function of oxidation time. The oxidation rate of Ge(111) is much lower than that of (100).³⁹⁾ This suggests that Ge(111) would be better in terms of GeO₂ scalability as the interfacial layer of high-k dielectric film. Furthermore, the substrate orientation dependence of the GeO desorption was also investigated after depositing 30-nm-thick GeO₂ on Ge(100) and (111) wafers. Figure 15 shows that the GeO desorption temperature is much higher on (111) than on (100),³⁰⁾ and these results strongly suggest that Ge(111) is superior to Ge(100) with regard to the rate of GeO desorption under a given process condition. Concerning the interface, no significant D_it difference between Ge(100) and Ge(111) was observed when examining the C–V characteristics of MOS capacitors made using the HPO+LOA process.³⁹⁾

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2.2.3. Defects in bulk GeO₂.

Note that the quality of not only the interface but also the bulk GeO₂ film grown in HPO is greatly improved. Figure 16 shows that (a) the water etching rate is slightly less in HPO-GeO₂ and that (b) C–V hysteresis increases with the time left in the air more clearly in APO-GeO₂ (APO: atmospheric pressure O₂) than in HPO-GeO₂. These facts indicate that the HPO process densifies the GeO₂ film and reduces the amount of electrical traps in it. The density increase of HPO-GeO₂ directly detected by the grazing incident X-ray reflectivity (GIXR) measurement is shown in Fig. 17.⁴⁶⁾

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We suspect that APO-grown GeO₂ films may have V_o-induced voids in it. Figure 18 shows the impact of PDA on GeO₂ film properties, evaluated by the band-edge photo-absorption with spectroscopic ellipsometry.²³⁾ An appreciable subgap (band edge tailing) formation is observed in N₂- or APO-PDA cases but not in HPO-PDA. The optical band gap of HPO-GeO₂ is estimated to be ∼6.0 eV. This suggests that the subgap formation may be related to oxygen deficiency in the GeO₂ film. Looking at the spectra more carefully, one can see that the subgap absorption seems to consist of two peaks at ∼5.1 and ∼5.8 eV. Those peaks might be correlated with defects such as neutral O vacancies or Ge²⁺, which was reported as a plausible origin of ∼5 eV photo-absorption observed in oxygen-deficient GeO₂ bulk glass.⁴⁷⁾ Furthermore, subgap formation was not detected in GeO₂ deposited on SiO₂ (data not shown). Therefore, the oxygen deficiency is closely related with the interface reaction discussed in Sect. 2.1.

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Electron spin resonance (ESR) studies were also carried out to detect defects in the GeO₂/Ge stack.³¹⁾ Figure 19(a) shows that almost no signals are detected in case of HPO-annealed GeO₂ on Ge, while bulk defect signals in other cases are clearly observed. The annealing temperature dependence of defect signals is shown in Fig. 19(b). No magnetic field direction dependence in signals suggests that defects such as the P_b centers commonly observed at SiO₂/Si interface are not located at the GeO₂/Ge interface. It was also reported that the P_b centers at the GeO₂/Ge interface were not detectable by the conventional ESR.⁴⁸⁾ This too might be again attributed to more flexible bonds in the Ge–O network, although very small Ge dangling bond signals were later detected using electrically detected magnetic resonance (EDMR) measurement.⁴⁹⁾

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X-ray photoelectron spectroscopy (XPS) analysis has been widely used for characterizing SiO₂/Si gate stack properties. Although the sub-oxide analysis has not been established in GeO₂/Ge yet, most studies employ the same method for GeO₂/Ge as that for SiO₂/Si by assuming the Ge⁴⁺ position at a given binding energy. The value of Ge⁴⁺ is substantially scattered among published reports, so it is presently not safe to evaluate the sub-oxide formation kinetics on Ge by using the same XPS analysis used to evaluate them on Si. It is worthwhile mentioning here that the charging effects⁵⁰⁾ or the moisture effects⁵¹⁾ in the XPS measurement of GeO₂ should be much more carefully considered than in the XPS measurement of SiO₂/Si. HPO-GeO₂ is more robust against the charging in XPS measurement (data not shown).

We systematically measured the band offset at GeO₂/Ge by both XPS and internal photoemission (IPE) spectroscopy. The IPE study was carried out in Au (∼15 nm)/GeO₂/Ge metal–inulator–semiconductor (MIS) capacitors. IPE can determine the conduction band offset at the oxide/semiconductor interface directly.⁵²⁾ Figure 20 shows our IPE system.⁵³⁾ As shown schematically in Fig. 21, the conduction band offset in HPO-GeO₂/Ge was estimated to be 1.65 ± 0.1 eV.⁵⁴⁾ Furthermore, we observed an appreciable spectrum difference between HPO-GeO₂/Ge and APO-GeO₂/Ge. In APO-GeO₂, there seems to be tailing near the photoemission threshold. This suggests that APO-grown GeO₂ may have a huge amount of defect states near the conduction band edge. Smaller values of the energy band gap of GeO₂ and band offset at GeO₂/Ge reported in the literature might be mainly due to poor GeO₂ quality.

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All of the results obtained experimentally show that HPO can produce high-quality GeO₂ on Ge in addition to a considerably low D_it. Thus, it is concluded that HPO and HPO+LOA are powerful methods for preparing perfect GeO₂/Ge gate stacks without degrading the quality of the GeO₂ bulk film or the GeO₂/Ge interface. Moreover, it should be emphasized that everything is thermodynamically controlled in the present process.

GeO₂/Ge interface formation is always associated with GeO desorption, so HPO is thermodynamically effective for making excellent GeO₂/Ge gate stacks. On the other hand, we know that actual reactions are often dominated by kinetics rather than thermodynamics. Therefore, a kinetic suppression of GeO desorption from Ge gate stacks has also been attempted. First, the reaction blocking layer was inserted between GeO₂ and Ge. 10-nm-thick GeO₂ films were deposited on both Ge and SiO₂/Si. Figure 22 shows that the C–V characteristics of a Au/GeO₂/Ge MOS capacitor are significantly degraded, while those of a Au/GeO₂/SiO₂/Si MOS capacitor are apparently normal.²²⁾ This suggests that excellent gate stacks on Ge can be obtained by putting a more stable interlayer between Ge and GeO₂. If so, GeO₂ is no longer needed. In that sense, SiO₂/Ge gate stacks might be good.

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In fact, a number of efforts using Si-cap technology on Ge have been carried out to achieve good performance of Ge gate stacks, mainly by the IMEC group.^55,56) In this method, SiO₂/(Si)/Ge is used in place of GeO₂/Ge gate stacks. As shown in Fig. 23, Si can be expitaxially grown on Ge in a controlled manner by using a continuous growth process in a chamber,⁵⁷⁾ although the ultimate control of Si thickness and/or Si oxidation is needed to obtain well-controlled gate stacks. This method has been successfully utilized for Ge MOSFETs^57,58) and has made it possible to make use of Si process technology without considering how to suppress the reaction at oxides/Ge. It is a great benefit in the Si cap process on Ge. In our experiments, however, Si passivation works well for D_it in the lower half of Eg but degrades the upper half. This means that it may work for p-MOSFETs but not for n-MOSFETs,⁵⁹⁾ although our passivation was not by the epitaxial Si growth. Furthermore, from the viewpoints that EOT scaling and narrow process window (whether the Si-cap layer is consumed or not is quite marginal even if the cost issue is not taken into account) and poor electron mobility reasons, we have not employed the Si cap process for Ge gate stack formation.

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Another kinetic approach is the control by cutting the desorption at the top surface instead of suppressing the reaction at the Ge interface in Eq. (2.1). It is expected that a Si cap might serve as a layer blocking GeO desorption from the top. GeO₂ films deposited on Ge with and without a Si cap layer were prepared and then annealed in N₂ at 600 °C. Figure 24 shows the annealing time dependence in N₂ of GeO₂ thickness measured by GIXR. With the Si cap, the thickness changes very little with PDA time, while without the Si cap, it decreases with PDA time.⁵⁹⁾ This suggests that the Si-capped GeO₂/Ge MOS capacitor may reveal a very slight degradation in C–V characteristics. To make the Si-cap conductive as the gate electrode, Ni was deposited, followed by silicidation annealing. Figure 25 shows the C–V characteristics of two kinds of GeO₂/Ge gate stacks: a GeO₂ MOS capacitor annealed in N₂ before Au gate electrode deposition, and a MOS capacitor with NiSi_x-capped GeO₂. Well controlled C–V characteristics were achieved only in the latter case.⁶⁰⁾ This is direct evidence that the kinetic suppression of GeO desorption significantly improves GeO₂/Ge gate stacks.

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Although we tried to push the kinetic approach forward at the early stage of our Ge research, we have put emphasis on the thermodynamic approach because the metal capping process would be expected to increase the process complexity in device integration. In the material approach discussed in the next section, both the thermodynamic and kinetic approaches are in principle working together. This is a key concept in the EOT scaling discussed in Sect. 4.3.

From the early stage of our Ge research, we have tried to prepare Ge gate stacks with various high-k dielectrics.⁶¹⁾ Our experiences gave us the naïve impression then that trivalent metal oxides such as Y₂O₃, Sc₂O₃, and Al₂O₃ or rare-earth oxides (RE-oxides) might be friendly to Ge in terms of the interface control, while HfO₂ should significantly degrade the Ge interface. The results of theoretical calculations also gave us that impression.⁶²⁾

A difference between Y₂O₃/Ge and HfO₂/Ge is seen in the C–V characteristics in Fig. 26(a).⁵⁹⁾ More distinctly, the interface quality difference is shown in the Zerbst plot⁶³⁾ in Fig. 26(b). Y₂O₃ on Ge is much better than HfO₂ on Ge from the interface control viewpoint. Figure 27 shows that Y₂O₃/GeO₂ is significantly different from HfO₂/SiO₂ from the viewpoint of intermixing at the interface.⁵⁹⁾ In fact, as described later in Sect. 3.1, we achieved the highest electron mobility in Ge MOSFETs with a Y₂O₃-doped GeO₂ (YGO) interface formed by HPO-PDA of Y₂O₃.^58,64) Since Y₂O₃ or Sc₂O₃ shows the lowest standard Gibbs free energy change (ΔG°) among various oxides thermodynamically, Y or Sc diffusion to GeO₂ enables the GeO desorption to be suppressed very effectively. This is discussed in more detail in Sects. 4.2 and 5.2 from the viewpoints of both oxygen potential control and gate stack reliability. Thus, in our experience, we have come to the conclusion that YGO should be a most promising gate dielectric film on Ge. In terms of the EOT scalability, however, YGO can be the interlayer between a real high-k material and Ge because the dielectric constant of YGO is not so high (k = 6–8). This is discussed in Sect. 4.2.

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It is practically feasible to use Al₂O₃ for Ge gate stacks. The Al₂O₃/GeO_x/Ge gate stacks have been intensively studied.^65,66) In this process, atomic layer deposition (ALD)-Al₂O₃ was deposited and the deposition was followed by plasma-excited O^* PDA at 300 °C. In fact, Al₂O₃ is most easily deposited by ALD. The cross-sectional view and TEM image are shown in Figs. 28(a) and 28(b), respectively.⁶⁶⁾ Takagi's group further reported that the interface GeO_x formation was needed to keep the low D_it shown in Fig. 28(c).⁶⁵⁾ 1-nm-thick GeO_x is needed to achieve a low D_it, and the interface is degraded when the thickness is about 0.5-nm-thick GeO_x. A good point of this process is that the Al₂O₃ layer works as a plasma-protection barrier and an oxygen-diffusion stopper in addition to being friendly to the conventional CMOS process.

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Since we think that Al-strengthened GeO₂ might be formed at the interface, it is in some sense similar to the YGO interface proposed above. Namely, both YGO and Al₂O₃-doped GeO₂ can serve as an oxygen-diffusion-blocking layer and stabilize GeO₂ by forming the film with modified continuous random network. This is the kinetic control of Ge gate stacks. From this viewpoint, the material approach of selecting the right material requires consideration of the thermodynamic as well as kinetic control of GeO₂ on Ge. Both of them are crucially important for establishing reliable ultrathin-EOT gate stacks and so are discussed in Sect. 5.2.

Another material approach is from the rare earth oxides on Ge. Figure 29(a) shows C–V characteristics of a Ge MOS capacitor prepared by HPO of (La–Lu)₂O₃ (LLO). They look almost ideal.⁶⁷⁾ It is interesting to note that LLO is a real high-k material (k ∼ 20) and stays amorphous up to around 1000 °C.⁶⁸⁾ As shown by the TEM image in Fig. 29(b), a rather thick interface layer was formed by HPO. We noted that the interface layer was not pure GeO₂ but LLO-mixed GeO₂.⁶⁹⁾ Since we have not optimized the LLO gate stack, we will no longer talk about it in this paper. However, further optimization might make it a great gate stack on Ge.

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At the early stage of considering Ge compounds on Ge, GeON instead of pure GeO₂ was favorably considered in analogy to SiON in advanced Si technology.^70–76) C–V characteristics were much improved, but a high-electron-mobility benefit in Ge n-channel FETs has not so far been reported. We paid attention to the fact that N could also lower the oxygen potential thermodynamically as discussed later in Sect. 3.3.^77,78) So GeO desorption could be reduced and the interface properties might be improved by fine-tuning the N profile in GeO₂. As we did not have an appropriate technique for the optimum nitridation of Ge for N not to be located at the interface, we stopped studying the GeON gate stack. But it has a potential for the further improving the interface layer.

Ge oxidation at an optimized temperature is obviously the most popular method to form Ge gate stacks, as it is to form Si gate stacks. To suppress GeO desorption, low-temperature oxidation is thermodynamically favored. Matsubara et al. showed that C–V characteristics with a relatively low D_it could be obtained by just oxidizing Ge at 550 °C.⁷⁹⁾ Although that seems to be inconsistent with our results, we cannot say that there is no process window for improving gate stack characteristics just by a simple oxidation. Nevertheless, even if there might be such a small process window, GeO₂ becomes thermodynamically unstable at rather high temperatures above 600 °C.

Although so far we have mainly discussed GeO desorption from GeO₂/Ge gate stacks, we actually need to understand Ge oxidation kinetics. As mentioned previously, the oxidation rate of Ge is described by the linear-parabolic law like that describing the oxidation rate of Si. Although as mentioned in Sect. 2.2.2, Ge oxidation appears so related to the GeO desorption process, it is not obvious whether the Deal–Grove model is or is not valid for Ge. Two experimental results that cannot be easily explained by the Deal–Grove model are discussed in the following.

First, the anomalous p-O₂ dependence of the rate of Ge oxidation is discussed. Ge(100) wafers were oxidized in wide ranges of temperature and p-O₂. GeO₂ thickness versus oxidation time at 500 °C is shown in Fig. 30(a) with of p-O₂ as a parameter. GeO₂ thickness versus p-O₂ temperature is shown in Fig. 30(b) with the oxidation temperature as a parameter.⁸⁰⁾ Note a reverse p-O₂ dependence of the oxidation rate. It is surprising that the oxidation rate is reduced below 520 °C as the p-O₂ increases above a critical p-O₂. This has never been observed in the oxidation of Si. It is hereafter called low-temperature high-pressure O₂ (LT-HPO) oxidation. It is strange because a higher p-O₂ means a larger amount of O₂ molecules in the ambient. Note that in Fig. 30 p-O₂ is denoted by the room-temperature p-O₂. Anomalous p-O₂ dependence in low p-O₂ was also discussed in Ref. 21. Therefore, it is general behavior in Ge oxidation, depending on the temperature. Figure 31 shows that (a) the density of LT-HPO GeO₂, estimated by GIXR, is greater than that of HT-HPO GeO₂ and (b) the wet etching rate is significantly reduced in LT-HPO. This suggests that the reverse p-O₂ dependence may be partly due to the densification of the GeO₂ film. We applied the Deal–Grove model to characterize the results. To qualitatively reproduce the experimental behavior shown in Fig. 30, improbably large pressure–dependent B parameter in the Deal–Grove equation is needed as shown in Fig. 32.

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To understand the Ge oxidation correctly, the oxygen atom kinetics should be clarified, since we know that the oxygen atoms diffuse much more easily than Ge in GeO₂, as discussed in Fig. 8. In order to trace the oxygen atom movement in the oxidation, the isotope ¹⁸O marker experiment was carried out. A Ge¹⁶O₂ (∼10 nm)/Ge sample grown conventionally was reoxidized by ¹⁸O₂, and then both ¹⁸O and ¹⁶O profiles in the film were inspected by the high-resolution Rutherford backscattering spectrometry. The results showed that ¹⁸O was not localized at the GeO₂/Ge interface but spread throughout the film.⁸¹⁾ This is in contrast with the Deal–Grove model commonly recognized for Si. In order to more clearly confirm the oxidation kinetics of Ge, both Ge¹⁶O₂/Ge and Si¹⁶O₂/Si samples have recently been prepared again by the normal ¹⁶O₂ oxidation of Ge and Si substrates, at 550 °C for GeO₂/Ge and at 900 °C for SiO₂/Si (the temperatures are equivalent to each other when normalized by the melting temperature). The initial thickness was relatively thick (∼120 nm) for both GeO₂ and SiO₂. Then both were put into a 100% (actually above 98%) 1 atm ¹⁸O₂ ambient, as shown in Fig. 33(a). The oxide thickness was increased to about 130 nm for both cases. These samples were inspected by the SIMS measurement. The depth profiles of secondary ion intensity of both ¹⁸O and ¹⁶O are shown for GeO₂/Ge and SiO₂/Si systems in Fig. 33(b).⁸²⁾ Look at the profile difference of ¹⁸O at the Ge interface from that at the Si one. ¹⁸O is accumulated at the interface in the Si case, which was as reported previously,⁸³⁾ while in the GeO₂/Ge case, ¹⁸O gradually decreases to the interface. Since the Deal–Grove model predicts that the oxide is newly formed through the reaction of O₂ with semiconductors at the interface, ¹⁸O accumulation should be observed as in the Si case. The fact that no special feature at the interface was observed definitely indicates that the Deal–Grove model is not applicable to Ge oxidation.

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What is the possible kinetics of Ge oxidation over the Deal–Grove model? Although it is still under investigation, our view is roughly described as follows.⁸²⁾ In case of Ge oxidation, we should take account of GeO desorption, in which V_o diffusion is involved. In fact, a work reported in a recent paper found that the oxygen vacancy V_o may be involved in the oxidation process by inspecting the nuclear reaction profiling of ¹⁸O.⁸⁴⁾ The SIMS results in Fig. 33 also suggest that O atoms should diffuse through the GeO₂ film. It is unsure whether this is driven by an exchange process like that discussed in GeO desorption in Sect. 2.1, with the help of V_o formation, or by the interstitial-mediated diffusion.⁸⁵⁾ The V_o-mediated model, however, seems to be reasonable when it is considered that HPO can suppress V_o generation inside the film thermodynamically, resulting in the significant suppression of the oxidation shown in Fig. 30. Namely, the oxidation of Ge is likely to be driven by the V_o generation at the interface in Eq. (2.4), followed by the reaction between V_o and O. The analytical model like the Deal–Grove one is now under way to establish.

Finally, ozone or O^* (oxygen radical) oxidation of Ge is briefly discussed. It was investigated particularly by a group at Stanford University,⁸⁶⁾ in order to suppress partly GeO desorption by employing a low-temperature process. Ge can be oxidized by ozone or O^* at low temperatures with a quite low activation energy, thanks to the high oxidation power of ozone or O^*. In the ozone or O^* oxidation process, the lifetime of O^* concentration, which is dependent on the temperature, should be taken into account. Therefore, the simple Deal–Grove model is not applicable even for the Si case. We studied the O^* oxidation of Ge by using O^*, which was generated by the µ-wave excited plasma (2.45 GHz) as shown in Fig. 34.⁸⁷⁾ A distinct difference between normal O₂ (including HPO) and O^* oxidation is that, as shown in Figs. 35(a) and 35(b), there is little temperature dependence in O^* oxidation. C–V characteristics were good, particularly for thin GeO₂ formation. However, we stopped the O^* process research because the films were not stable at higher temperatures. It may be resumed when the low-temperature oxidation is definitely needed.

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We are interested in Ge CMOS, but as mentioned in the introduction, so far, n-MOSFET technology has actually been a bottleneck. Therefore, it is a big concern that n-channel Ge MOSFETs might be intrinsically poor even though the bulk electron mobility is expected to be high.⁸⁸⁾ We applied the gate stack formation process described in the previous sections to n-MOSFET fabrication. Long-channel n-MOSFETs were fabricated on a Ge substrate using the two-step HPO+LOA process.³⁸⁾ Several channel lengths (W/L = 90 µm/100–500 µm) were defined, and phosphorus (1 × 10¹⁵/cm² dose) was implanted with 100 keV to form source/drain (S/D) regions. Such large FETs enabled us to estimate electron mobility very accurately using the split C–V technique without being worried about by size uncertainty and/or parasitic resistance and capacitance. GeO₂ was grown at 550 °C for 10 min in HPO (p-O₂ = 70 atm at room temperature), followed by LOA at 400 °C. Then, Al was deposited and defined for the gate electrode. Note that spacer Y₂O₃ was used to protect GeO₂ from the wet process and air exposure because we found that Y₂O₃ was water-resistant and rather compatible with Ge as discussed in Sect. 2.4.

Figure 36(a) shows the transfer characteristics (I_S–V_G) of Ge(100) n-MOSFETs in which GeO₂ was grown by HPO+LOA.³⁸⁾ The I_on/I_off current ratio at 300 K was about ∼10⁴. The subthreshold swing (S-factor) was 125 mV/dec, which was rather high, considering the low D_it determined using the conductance method (Fig. 14). Since the S-factor should have a linear temperature dependence around room temperature,⁸⁹⁾ the temperature dependence of the S-factor was measured from 150 to 300 K, as shown in Fig. 36(b). The S-factor at 300 K extrapolated from the temperature dependence was 95 mV/dec,³⁹⁾ which was reasonable and much smaller than the measured value. This suggests that the S-factor at 300 K might be degraded owing to the S/D junction leakage current in the subthreshold region in this device. The impact of LOA on the electron effective mobility (μ_eff) in addition to that of HPO is shown in Fig. 37 as a function of electron density. On Ge(100), the peak electron mobility after HPO+LOA was 810 cm² V⁻¹ s⁻¹, while that after HPO was 610 cm² V⁻¹ s⁻¹. The lower μ_eff in MOSFET fabricated by HPO only is explainable by the Coulomb scattering due to relatively high values of D_it (Fig. 12).

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As already mentioned in Sect. 2.2, the surface orientation of Ge substrates affects both the GeO₂ formation and GeO desorption processes. In this section, we discuss the effect of substrate surface orientation on electron mobility. Figure 38 shows that the peak electron effective mobility on Ge(111) was about 1,100 cm² V⁻¹ s⁻¹ at 300 K and was 1.4 times better than that of Ge(100).³⁹⁾ This suggests that the (111) surface should intrinsically be better than the (100) one not only with regard to the process stability as discussed in Sect. 2.2 but also with regard to the FET performance. An advantage of MOSFETs on the Ge(111) surface under the ballistic carrier transport was expected from the analytical estimation of two-dimensional projections in the conduction-band energy.⁹⁰⁾ The (100) surface in Si, roughly speaking, corresponds to the (111) surface in Ge as shown in Fig. 39. This view is also applicable for the diffusive transport case in terms of the effective mass. In actual scaled CMOS design, the surface orientation effects are discussed in conjunction with strain effects in both Si and Ge.⁹¹⁾ In particular, a possible method to make the best of strain effects on the mobility in Fin-FETs is now deliberately studied both experimentally and theoretically,^92,93) as obviously expected from two-dimensional projection views. In this review, however, we would focus on unstrained transport characteristics to pay attention to the material and process fundamentals of Ge.

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We further improved the electron μ_eff by optimizing the two-step HPO+LOA process for Y₂O₃ on Ge(111). Figure 40 shows the peak electron mobility progress with the calendar year.³¹⁾ The peak electron and hole mobility values obtained so far have approached 1,920 cm² V⁻¹ s⁻¹ on Ge(111) and 720 cm² V⁻¹ s⁻¹ on Ge(100). The highest electron mobility case is for Y₂O₃ on Ge(111) by using the HPO+LOA process with a longer LOA time. It is about ×2.5 of the universal electron mobility in Si MOSFETs and about half of the bulk electron mobility in Ge. Note that, as discussed in Sect. 2.4, the interface of this gate stack is YGO rather than Y₂O₃. This interface may further decrease D_it, resulting in the peak electron mobility enhancement. Concerning the hole mobility, we have also improved it to ×3.5 that of Si without any strain effect. These results certainly encourage us to promote Ge CMOS. Figure 41 shows the μ_eff values of electron and hole as functions of electron and hole densities, with different LOA times and different surface orientations of Ge.⁶⁴⁾

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In the conventional mobility analysis, the temperature dependence is the property best characterizing the scattering mechanism in the channel.⁹⁴⁾ The temperature dependence of the peak electron μ_eff is shown in Fig. 42, where the slope of temperature dependence changes from positive to negative with an increase in the peak electron μ_eff. This clearly suggests that the scattering mechanism changes from Coulomb to phonon scattering. Namely, the electron transport in the inversion channel has become intrinsic with dramatic interface improvements. To our knowledge, this is the first demonstration of phonon scattering limited mobility in Ge n-MOSFETs.

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Everything so far seems to be good. What is the remaining problem? Concerning the carrier mobility, it has often been claimed that the most relevant mobility in the actual circuit operation is not the peak mobility but that in the high-electron-density region. That is absolutely true. The electron mobility in high N_s region in Fig. 41 is almost comparable to that of the Si counterpart. Does this mean that there is no future for Ge CMOS? In the next section, we focus on this. Another concern is the mobility reduction in the thin EOT region.⁵⁵⁾ This is actually very important in CMOS scaling and will be discussed in Sect. 4.

As shown schematically in Fig. 43, Coulomb scattering, phonon scattering, and surface roughness scattering are widely recognized as dominant carrier scattering mechanisms in the Si inversion channel.⁹¹⁾ By employing HPO in the Ge oxidation, Coulomb scattering has been dramatically reduced, thanks to the D_it reduction, resulting in the peak electron mobility in Ge now being 2.5 times that in Si. Reasoning by analogy to the Si MOSFET, one may suspect that the larger surface roughness on Ge might degrade the mobility at high electron density (high effective field, E_eff). However, we reported that the rms value measured by the AFM was not necessarily related to the high-N_s electron mobility.⁹⁵⁾ Here, note that not only the roughness height but also the roughness correlation length should be considered in the conventional roughness scattering formulation.⁹⁶⁾ We therefore tried to realize the atomically flat surface on Ge in order to achieve both ultimately small rms and large correlation length in the surface roughness.

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We fortunately succeeded in preparing the atomically flat surface by H₂ annealing.⁹⁷⁾ This method has been widely used on Si surfaces,⁹⁸⁾ but to our knowledge, this was its first demonstration on Ge. Figure 44(a) shows an AFM image of the Ge(111) surface in H₂ annealing at 650 °C, in which only a couple of atomic steps are clearly observed in an area ∼1 µm square. Each step corresponds to one monolayer on Ge(111), as shown in Fig. 44(b). As shown in Fig. 45, this H₂ annealing method also enabled atomically flat surfaces on Ge(110) and (100) to be formed at relatively high temperatures.⁹⁹⁾ Although the surface planarization mechanism has not been studied in detail, microscopic surface patterns on three surfaces on Ge are the same as those on Si, and the same kinetics that work for Si may work for Ge as well.

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Note here that what is needed is not an atomically flat surface but an atomically flat interface with a dielectric film after the gate stack formation. To investigate how the atomically flat surface was affected by the oxidation process, the atomically flat Ge(111) surface was oxidized in HPO (∼5 nm) at 500 °C. AFM images before and after oxidation are shown in Fig. 46(a). It is surprising that the step-and-terrace structures are clearly maintained in the oxidation. Figure 46(b) summarizes systematic results of the rms roughness after the oxidation when the temperature and p-O₂ were changed.¹⁰⁰⁾ The roughening is by and large suppressed at lower temperatures under high p-O₂, in which atomically flat interface is maintained. The fact that LT-HPO actually keeps the interface flat was also observed on as-cleaned Ge surfaces. Figure 47 shows the rms histogram at 500 °C with p-O₂ as a parameter. A decrease in the histogram width on the as-cleaned Ge surface means that the oxidation under higher p-O₂ at 500 °C can reduce the surface roughness. The roughening process should be directly associated with the oxidation of the Ge substrate and will be further discussed in Sect. 4.

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Let us go back to the effect of surface flatness on electrical properties. Figure 48 shows the μ_eff–N_s relationship in three kinds of processed FETs.¹⁰¹⁾ FET-A was fabricated on the atomically flat Ge(111) by HPO at 500 °C, FET-B was fabricated by HPO at 500 °C, and FET-C was fabricated by HPO at 550 °C. The peak electron mobility is almost the same for each of the samples because of the very low D_it at the GeO₂/Ge interface, while the high-N_s electron mobility of each is distinctly different from those of the others. Only FET-A shows significantly higher electron mobility in the high-N_s region. Thus, it is concluded that the surface roughness control followed by the appropriate oxidation enables us to improve the high-N_s electron mobility. Concerning the poor electron mobility in the high-N_s region, another possible origin is that there might be more interface defects near the conduction band edge of Ge.¹⁰²⁾ This is partly true because the surface planarization might reduce such ionized defects as well, while it is also true that the Coulomb scattering may be reduced, thanks to the more effective screening by free carriers present at high densities. The border traps in dielectric films with poor interface on Ge or the real space transfer of electrons from the channel to the dielectric film side (carrier spillover effect) may also be a concern in case of the low energy barrier at the Ge interface. Although further analysis is obviously needed, the facts that atomically flat surface planarization of the Ge substrate by H₂ annealing definitely improves the high-N_s electron mobility and that a good Ge interface with HPO cannot solve the mobility degradation at the high-N_s region suggest that the degradation origin should exist in the Ge substrate side including the surface. Whatever the H₂ annealing effect mechanism is, this is good news from the technical perspective.

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The electron mobility in Ge MOSFETs has been enhanced remarkably thanks to the significant reduction of carrier scattering origins such as D_it and the surface roughness. Concerning a single FET, the channel interface in the Ge gate stack is obviously crucial for improving the carrier transport in the channel, while the Ge substrate has not been seriously considered because phonon scattering should be "intrinsic" in Ge. In this section, we discuss that the substrate can affect the electron mobility even when device fabrication processes are exactly the same.¹⁰³⁾ We prepared Ge MOSFETs on two different kinds of p-Ge wafers, denoted here by wafers A and B. Both gate stacks were formed by HPO-GeO₂ as described previously. Figure 49 shows the effective electron mobility as a function of electron density on two kinds of wafers. Note that there is a striking difference in the effective electron mobility at the low-electron-density region. According to the conventional analysis of the inversion layer mobility in Si-MOSFETs, the Coulomb scattering probability should be quite different between two kinds of MOSFETs on wafers A and B. There are two sources of Coulomb scattering centers in Ge gate stacks. One is at the GeO₂/Ge interface and/or in GeO₂, and the other is in the Ge bulk. Figure 50 shows D_it spectra of two gate stacks on wafers A and B, estimated by the low-temperature conductance method.¹⁰¹⁾ No difference in D_it spectra is observed between them. Furthermore, the dopant density was almost the same in the SIMS measurement. This suggests that the probabilities of Coulomb scattering by D_it and dopant atoms should be the same　 between A and B. Thus, the significant mobility degradation on wafer B in Fig. 49 seems mysterious in the conventional scattering analysis in FETs.

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As discussed in Sect. 3.3, H₂ annealing is effective for achieving an atomically flat surface of Ge substrates. Together with this finding, we found that the H₂ annealing of wafer B could improve the electron mobility significantly as shown in Fig. 51.¹⁰³⁾ Increasing the H₂ annealing temperature enhances the peak electron mobility significantly. In addition, it is interesting to see that the H₂ annealing of Ge wafer B does not affect the hole mobility in p-channel Ge MOSFETs. The results suggest that possible defects seem to be electrically inactive in the accumulation and depletion regions of the p-Ge substrate. Also note that, as shown in Fig. 52, D_it is not at all sensitive to H₂ annealing, as expected from Fig. 50. This suggests that there may be a new origin of the electron mobility degradation in the Ge substrate, because the peak electron mobility is not affected very much by the surface roughness scattering. Here, we note that the oxygen concentration near the surface of wafer B is reduced in H₂ annealing and depends on the annealing temperature as shown in Fig. 53. In wafer A there was no oxygen detectable by the SIMS. Typical metals in wafer B were not present at levels above 5 × 10¹⁰ atoms/cm².

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To further investigate the oxygen effects, oxygen ions (100 keV, 10¹³ cm⁻²) were intentionally implanted in wafer A, as indicated in Fig. 54(a). Figure 54(b) shows that the electron mobility is significantly improved by H₂ annealing.¹⁰³⁾ In fact, as shown in Fig. 55, the oxygen profile in wafer A differed significantly between the conditions with and without implanted oxygen.¹⁰¹⁾ Note that the step-and-terrace structure of the Ge surface was exactly the same for both wafers A and B. Hence, the oxygen-related scattering centers in the Ge wafer could be the origin of electron mobility degradation in Ge n-MOSFETs.

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Possible defects in the inversion state are schematically depicted in Fig. 56, in which the defect might be an acceptor type and located in the upper half of the energy band gap.¹⁰³⁾ Although the DLTS measurement was carried out to characterize oxygen-related defects in wafer B, no difference has been observed.¹⁰⁴⁾ The exact origin is still under investigation, but this finding points out that the oxygen control in the Ge substrate is substantially important for achieving high-performance Ge n-MOSFETs. The Ge wafer quality has not matured yet, which means that there is plenty of room to optimize it. Note that the above considerations should be applied not only for Ge wafers but also for epitaxially grown Ge films.

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We have already discussed the LT-HPO, which enables thin GeO₂ to be formed on Ge by the thermal oxidation process under a high O₂ pressure. However, even though LT-HPO makes the EOT thin and the interface flat on Ge, it does not necessarily ensure that remarkable interface properties at GeO₂/Ge are accomplished. Thus, electrical characterization in MOS capacitors and FETs should be carried out. Figure 57 shows the bidirectional C–V characteristics of pure GeO₂/Ge MIS capacitors with 1.5 nm EOT GeO₂ grown by LT-HPO. Very small hysteresis and frequency dispersions in the weak inversion regime in C–V characteristics indicate that ultrathin GeO₂/Ge gate stacks still guarantee superior interface properties together with the flat interface. Furthermore, it is worthwhile mentioning the thermal robustness of LT-HPO-grown GeO₂ on Ge. GeO₂ films grown by LT-HPO on atomically flat Ge(111), (100), and (110) were annealed in N₂ as a function of PDA temperature, and MOS capacitors and MOSFETs were fabricated. Figures 58(a) and 58(b) show the D_it and interface roughness. μ_eff is very slightly degraded on Ge(111), while a huge degradations are observed on Ge(100) and Ge(110). Figure 59 shows the comparison of the μ_eff–N_s relationship in n-MOSFETs fabricated by the same LT-HPO process on Ge(111), (100), and (110) wafers with N₂ PDA at 500 and 550 °C.¹⁰⁵⁾ The advantage of Ge(111) discussed so far is also kept for the whole N_s region. Thus, it is concluded that LT-HPO does not have any unfavorable effects on electrical properties. It is fortunate to see a big advantage of the Ge(111) surface against the thermal process, in addition to the highest electron mobility.

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Considering both the conduction band offset at GeO₂/Ge (∼1.6 eV⁵⁴⁾) and the relative dielectric constant of GeO₂ (∼6), the thinning limit of EOT of GeO₂ will be estimated to be approximately 1–1.5 nm, by considering that in SiO₂/Si MOS¹⁰⁶⁾ because a key parameter in the direct tunneling in the gate dielectric film is $k\sqrt{\varphi }$ (φ: band offset). Therefore, we will be able to reduce the GeO₂ EOT on Ge down to ∼1 nm. However, considering that Ge should be beyond Si, high-k gate dielectric films are inevitably needed instead of GeO₂, in addition to the LT-HPO method. We have fortunately found a good way of solving this matter as described in the following.

Now, we go back to thermodynamics. A remarkable job of HPO on Ge is based on the decrease in the Gibbs free energy change ΔG in the Ge oxidation process thermodynamically, as discussed in Sect. 2.1. There is another way of lowering ΔG in the oxidation. It is to replace HPO-GeO₂ with another oxide having a lower ΔG° (the standard Gibbs free energy change per O₂ molecule at 1 atm p-O₂). That is, we can stabilize Ge gate stacks using low-oxygen-potential oxides instead of HPO-GeO₂. We can search for candidate oxides in the Ellingham diagram.¹⁰⁷⁾ Figure 60 shows ΔG° as a function of temperature for various oxides. Consider the following reaction:

$$\begin{equation} \text{M}+\text{O$_{2}$}\leftrightarrow\text{MO$_{2}$}+\Delta G^{\circ}, \end{equation} \tag{ 4.1 }$$

in which M is a metal. A lower ΔG° means in principle a more stable oxide (higher formation energy). It is clear that SiO₂ is much more stable than GeO₂. Interestingly, many rare-earth oxides and transition metal oxides are much more stable than SiO₂. The reaction constant K in Eq. (4.1) is given by

$$\begin{equation} K=\frac{[\text{MO$_{2}$}]}{[\text{M}][\text{O$_{2}$}]}. \end{equation} \tag{ 4.2 }$$

Thus,

$$\begin{equation} \Delta G=\Delta G^{\circ}+\mathit{RT}\ln K=\Delta G^{\circ}+\mathit{RT}\ln\left(\frac{1}{\text{p-O$_{2}$}}\right). \end{equation} \tag{ 4.3 }$$

It is assumed in the above equation that O₂ is only gas phase in the reaction. In the equilibrium state, ΔG = 0. ΔG° for a specific oxide can be obtained as the equilibrium oxygen vapor pressure.

$$\begin{equation*} \Delta G^{\circ}=-\mathit{RT}\ln K=\mathit{RT}\ln(\text{p-O$_{2}$})_{\text{eq}}. \end{equation*}$$

Therefore,

$$\begin{equation} \Delta G=\mathit{RT}\ln\left[\frac{(\text{p-O$_{2}$})_{\text{eq}}}{(\text{p-O$_{2}$})}\right]. \end{equation} \tag{ 4.4 }$$

This relationship explains why HPO is very effective in stabilizing GeO₂ in the simple Ge oxidation. More interestingly, it points to the fact that selecting a lower ΔG° oxide among various oxides (instead of or in addition to using HPO) is another way of achieving more stable gate stacks on Ge. ΔG is of course further decreased with an increase in p-O₂. Thus, it naturally follows that HPO-Y₂O₃ is one of the most promising candidates on Ge. Note, however, that not all dielectric films with a lower ΔG° will be appropriate for gate stacks, as was the case of high-k material selection on Si.¹⁰⁸⁾ Y₂O₃ is fortunately what we have empirically regarded as the "Ge-friendly dielectric" for Ge gate stacks.⁶¹⁾ Furthermore, we know that the interface is much better in Y₂O₃-doped GeO₂ (YGO) than in pure Y₂O₃, as discussed in Sect. 3.2.⁶⁴⁾ Now, it is evident that YGO instead of GeO₂ should be our target dielectric.¹⁰⁹⁾

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YGO films were deposited on Ge using the rf co-sputtering of GeO₂ and Y₂O₃. It is worthwhile to show the GeO desorption temperature and water etching rate of 10%-Y₂O₃-doped GeO₂ (YGO) and Sc-doped GeO₂ (ScGO) together with those of pure GeO₂ in Figs. 61(a) and 61(b).¹¹⁰⁾ Doping only 10% Y₂O₃ (Sc₂O₃) into GeO₂ significantly strengthens the GeO₂ film. The interface layer formation through YGO in O₂ PDA at 550 °C was estimated by CET increase in gate stacks with 10 and 30% YGO. Figure 62 actually shows no increase in capacitance equivalent thickness (CET) even in the 10% YGO case, while CET increase is significant in the case of pure GeO₂. This indicates that YGO suppresses the O and/or V_O diffusion kinetically as well as stabilizes the GeO₂ film thermodynamically. Figure 63 shows the Y₂O₃ concentration dependences of the (a) relative dielectric constant and (b) water etching rate. k is above 8 even in 10% YGO, and almost saturates to be 10 in 20% YGO. No water etching is actually observed in 20% YGO.¹⁰⁹⁾

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D_it on Ge is shown as a parameter of Y% together with HPO-grown pure GeO₂ in Fig. 64(a), together with the remarkable C–V characteristics of 10% YGO MOS capacitors in Fig. 64(b). The 10% YGO case is actually the same as the HPO-grown pure GeO₂ case. D_it is degraded above 20% in YGO. This might be due to the phase segregation with a miscibility boundary around 15% YGO between Y-doped GeO₂ and Y-germanates.¹¹¹⁾ Such a low D_it certainly should enable the achievement of very high electron and hole mobility values, as high as those in HPO-grown GeO₂ gate stack MOSFETs on H₂-annealed Ge(111). As shown in Fig. 65, the highest electron mobility is obtained in the 10% YGO case.¹⁰⁹⁾ All of the results so far obtained strongly suggest that YGO has a great potential for scaled Ge gate stacks. Note that no HPO was used for YGO in this experiment.

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We investigated various M₂O₃-doped GeO₂ including Al₂O₃ in terms of D_it. YGO was the best of those evaluated in our experiments, although the best property quantitatively may, of course, depend on the optimization level. Therefore we focus on YGO in the following section. Further material properties and structural consideration of YGO are discussed in Sect. 5 in conjunction with the gate stack reliability.

Ge is more reactive to high-k materials than Si. This is an advantage in the sense that the interface GeO₂ layer might be efficiently removed, as well as a disadvantage in the sense that the channel interface might be degraded by the mixing of Ge with high-k materials. The difficulty is that the advantage and the disadvantage have the same origin. However, we have to keep in mind that it was impossible to bring high-k technology into the CMOS platform before 2000. If we understand the high-k/Ge interface deeply, we should certainly be able to overcome this challenge.

As discussed in the previous section, YGO is one of the most promising candidates for Ge gate stacks. Since the dielectric constant of YGO is not so high, however, a real high-k layer on YGO is needed for further EOT reduction. Since the interface layer (IL) might readily intermix with the high-k material during the thermal process, high-k dielectrics should be designed in consistency with the YGO-IL. Figure 66 shows that a YGO-IL thicker than 1 nm can sufficiently suppress the cation diffusion from the top HfO₂, while further downscaling results in a marked interface degradation.¹¹²⁾ Therefore, HfO₂ will not be a good choice for scaled gate stacks on Ge, even in cases with YGO-IL. We would like to propose YScO₃ as a high-k dielectric film on YGO. Figure 67 shows that YScO₃ is a real high-k material (k ∼ 17), although both Y₂O₃ and Sc₂O₃ have only medium-k values.¹¹³⁾ Structural relaxation and denser packing in YScO₃ might be the origin of the k-enhancement.¹¹⁴⁾ In addition, YScO₃ is also reported to have a sufficient energy band gap (∼6 eV).¹¹⁵⁾ Note that a most beneficial point of YScO₃ is that this material, unlike Hf on Ge, does not degrade the gate stack even if Y and/or Sc may diffuse to the interface, because both binary oxides are Ge-friendly and have the lowest ΔG°.

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To demonstrate aggressive EOT scaling into the deep sub-nm EOT regime, a thin YGO-IL was deposited, followed by the deposition of ternary YScO₃ instead of a high-k binary oxide. Figure 68(a) shows well controlled C–V characteristics in YScO₃/YGO/Ge gate stacks with EOTs as thin as 0.5 nm. The gate leakage current is shown in Fig. 68(b) as a function of EOT for various gate stacks. The YGO interlayer with YScO₃ and HfO₂ looks quite promising in terms of the gate leakage current, but when D_it is considered in Fig. 66, the YScO₃/YGO gate stack is the most probable. YScO₃/YGO/Ge(111) n-FETs were fabricated to verify the robustness of the present gate stack design.¹¹²⁾ As shown in Fig. 69, the peak electron mobility of 1,057 cm² V⁻¹ s⁻¹ was obtained with 0.8 nm EOT, thanks to a lower D_it than the HfO₂/YGO case. Thus, it is safely concluded that YScO₃/YGO/Ge is the most promising and realistic gate stack with a 0.5 nm EOT.¹¹²⁾ (We used a 0.8 nm EOT gate stack for the mobility extraction, just because our FET was large and the gate leakage current made accurate mobility analysis difficult in 0.5 nm EOT region.)

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Here let us summarize the electron effective mobility for both peak and high-N_s region as a function of EOT in gate stacks with GeO₂/Ge, as shown in Figs. 70(a) and 70(b)¹⁰⁹⁾ and with YGO/Ge in Fig. 71.¹¹²⁾ By taking care of materials (thermodynamics) and processes (kinetics), we can reduce EOT without degrading either peak or high-N_s electron mobility values. This is wonderful news for making Ge CMOS devices more viable.

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Several kinds of typical gate stacks on Ge were first compared from the viewpoints of initial trap density and trap generation. Each film was prepared by the same process for systematic study, and HPO-GeO₂ was always included for comparison.

Figure 72(a) shows a schematic image of the trap filling process at a low electric field, and Fig. 72(b) shows V_FB shift as a function of stress time for Y-, Sc-, and Al-doped GeO₂ (YGO, ScGO, and AGO) and HPO-GeO₂/Ge stacks at a low stress field (E_stress = 4 MV/cm).¹²⁰⁾ E_stress is defined by V_OX/EOT, not only because it is a fair comparison concerning the practical device application but also because it is compatible with the thermochemical model for the dielectric degradation of high-k films.¹¹⁷⁾ Very small V_FB shifts suggest that the initial gate stack properties are very good for any of the dielectric films on Ge investigated in the present experiments. Next, the difference in trap generation among YGO, ScGO, AGO, and HPO-GeO₂ under high positive field stress is shown in Fig. 73.¹²⁰⁾ Although we experimentally do not have the thickness dependence of V_FB shifts, we can compare those films by assuming that the traps are generated close to the interface. Note that YGO shows the lowest trap generation rate under the present stress condition. On the other hand, the HPO-GeO₂/Ge gate stack is significantly degraded under high field stress, though it shows good initial C–V characteristics. Because the SiO₂/Si system is always the reliability reference and the best as compared with newly developed ones, it is surprising that the GeO₂/Ge system is much worse than the YGO/Ge one. This is one of the most important findings in Ge gate stack reliability, and it is worthwhile considering why YGO is better than GeO₂ on Ge. Next, let us discuss about it from the viewpoint of the network structure strength in dielectric films.

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Why does YGO or ScGO have a lower trapping generation rate than GeO₂? It will be reasonable to consider that electrical reliability is directly connected to structural stability in gate dielectric films, because gate stack degradations such as the trap generation and dielectric breakdown should be triggered by the local bond breaking in the network structure of the dielectric films. Since the water etching rate of YGO is much less than that of GeO₂ as shown in Fig. 63, the YGO network should be much stronger than the GeO₂ one. A local bond rearrangement in network structure rather than a single bond breaking may be more critical in the high field stress. Namely, the lower level of trap generation rate in YGO on Ge is considered to be due to the fact that Y cations in GeO₂ may strengthen the structural network of GeO₂.¹²⁰⁾ Therefore, the impact of structural change on the dielectric properties is next discussed systematically.

We introduce a "rigidity" in order to quantitatively characterize a topological concept of the structural network in dielectric films.¹²¹⁾ Let us define the rigidity of dielectric films by both single bond strength and network strength as follows:

$$\begin{equation} \textit{rigidity}=\gamma N_{\text{av}}, \end{equation} \tag{ 5.1 }$$

where γ is a prefactor (dimensionless) representing the single bond strength. The value of γ is assumed to be 1 for SiO₂. Oxides with a metal–oxygen (M–O) single bond stronger or weaker than that of Si–O have a γ value larger or smaller than 1, respectively. Note that γ < 1 for both GeO₂ and conventional high-k materials. Suppose that N_av is an average of the coordination number of each atom in the network, as already defined by Lucovsky et al.:¹²²⁾

$$\begin{equation} N_{\text{av}}=\frac{\text{total coordination number}}{\text{atom number}}. \end{equation} \tag{ 5.2 }$$

Figure 74(a) shows the N_av of YGO calculated by assuming its possible network structures, as a function of Y-ratio in YGO. N_av(YGO) was calculated by assuming that the coordination number of Y was 7, as follows:

$$\begin{equation} N_{\text{av}}(\text{YGO})=xN_{\text{av}}(\text{Y$_{2}$O$_{3}$})+(1-x)N_{\text{av}}(\text{GeO$_{2}$}). \end{equation} \tag{ 5.3 }$$

Here, x = Y/(Y + Ge). Figure 74(b) shows a schematic image of the effect of Y addition on GeO₂ network. YGO is regarded as the modified random network structure. Here, γ is assumed to be 0.8 in GeO₂, because the bond strength of Ge–O is 0.8× that of Si–O, although γ might be lower than 0.8 in Y-rich YGO,¹²¹⁾ which is shown in Fig. 74(a). By defining the rigidity, we can compare the network robustness among different dielectric films. Namely, we think that the trap generation is not a simple bond breaking but a local network rearrangement around the broken bond. Thus, the rigidity is more important than the single bonding energy. As a result, GeO₂ (rigidity ≃ 2.1) is more flexible than the moderately rigid SiO₂ (rigidity ≃ 2.67), but it is less robust against an external stress than SiO₂ because of its smaller rigidity.

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The concept of the rigidity is not new in the continuous random network (CRN) type of amorphous films and has already been discussed topologically in the glass community.^123,124) We have applied this concept to sub-nm EOT dielectric films on Ge in terms of the cation introduction into GeO₂. This is the first case that the rigidity is redefined by taking account of the single bond strength in addition to N_av. The N_av concept was also conjectured in gate stacks on Si by nitrogen (cation) doping into SiO₂,¹²⁵⁾ but as discussed here, the cation doping changes GeO₂ more considerably and favorably.

Figure 75 suggests schematically that a lower rigidity (with a low N_av and the same γ) leads to a lower $N_{\text{t}}^{0}$ and $D_{\text{it}}^{0}$ at the initial stage. We assume that $D_{\text{it}}^{0}$ shows a parabolic dependence on the rigidity as follows:

$$\begin{equation} D_{\text{it}}^{0}(\text{or}\ N_{\text{t}}^{0})\propto(\gamma N_{\text{av}}-\gamma N_{\text{av}}^{*})^{2}, \end{equation} \tag{ 5.4 }$$

where $\gamma N_{\text{av}}^{*}$ is the reference rigidity of a very flexible network. The parabolic dependence of the initial $D_{\text{it}}^{0}$ on the rigidity seems intrinsic at the interface because a mechanical strain on each atom might be involved in the initial $D_{\text{it}}^{0}$. A similar parabolic type of dependence has been reported in the anion-doped case in SiO₂/Si gate stacks.¹²⁵⁾ Consequently, a lower rigidity will be more appropriate for better initial properties. In contrast, in a very rigid network, higher coordination puts more constraints on the ions, exceeding their degree of freedom. Higher rigidity in dielectric films therefore initially results in a higher probability of bond breaking and trap formation. On the basis of above topological concept of dielectric film network structure, we can understand experimental results of the initial interface states density ($D_{\text{it}}^{0}$) and preexisting trap density ($N_{\text{t}}^{0}$) in dielectric films with different rigidity values on Ge.

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Next, we conjecture the gate stack reliability against high electrical stress. We think that the gate stack degradation should originate from the network deformation in the bulk or at the interface triggered by a local bond breaking. Therefore we intuitively define the energy to deform the dielectric film network as follows:

$$\begin{equation} \Delta_{\text{deform}}=\textit{rigidity}\times\Delta_{0}, \end{equation} \tag{ 5.5 }$$

where Δ_deform is the energy needed to deform the network and Δ₀ is an energy constant. To verify the relationship between rigidity and reliability, the degradation of gate stack properties was directly compared between flexible HPO-GeO₂/Ge and moderately rigid YGO/Ge. The experimental data plotted in Fig. 76(a) show that under a high positive E_stress, the YGO/Ge gate stack shows a lower D_it generation rate than the more flexible GeO₂/Ge. Since HPO-GeO₂ was easily broken down in case of high negative E_stress, only the positive E_stress results are shown. This is direct evidence that GeO₂/Ge layer is much weaker than YGO/Ge, although the degradation mechanism should be further studied. The same trend was found in the bulk trap (N_t) generation, which was estimated from the stress-induced leakage current (SILC) under E_stress = +9 MV/cm, as clearly shown in Figs. 76(b) and 76(c). As shown schematically in Fig. 77, the energy needed to break all the bonds and displace the ions in a rigid network is likely to be higher than that needed in a flexible one.¹²⁰⁾

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By comparing our model with the thermochemical model,¹¹⁷⁾ the trap generation rate g can be described as follows:

$$\begin{equation} g\propto\exp\left(-\frac{\Delta_{\text{deform}}-\mu E_{\text{loc}}}{k_{\text{B}}T}\right)=\exp\left(-\frac{\Delta_{0}\gamma N_{\text{av}}-\mu E_{\text{loc}}}{k_{\text{B}}T}\right), \end{equation} \tag{ 5.6 }$$

where μ is the local dipole moment and E_loc is the local electric field. Both sets of experimental results are consistent with our view that the higher rigidity in YGO can make GeO₂ more robust against high electrical stress. Namely, good initial passivation should be compromised with the long-term reliability, in addition to the process robustness and EOT scalability. Thus, it is emphasized that an IL with a moderate rigidity such as YGO is better to integrate with high-k dielectrics than GeO₂-IL, even if a decent C–V curve is initially obtained in high-k/GeO₂/Ge gate stacks.

The rigidity model is not quantitative but rather intuitive. Nevertheless, we think that the rigidity is a useful concept for achieving both good initial and highly reliable properties in MOS gate stacks including other semiconductors, although much more data are needed.

To further demonstrate substantial effects of the rigidity control on the gate stack reliability, we prepared a moderately rigid dielectric 10% YGO/Ge followed by PDA in LT-HPO at 500 °C, which enabled the YGO film to be made further V_o-free. Moreover, EOT extracted from C–V characteristics was very slightly changed in LT-HPO PDA, which means that further Ge oxidation was negligible in this additional PDA.¹²¹⁾ Figure 78(a) shows a very low D_it at the LT-HPO-YGO/Ge interface thanks to the sufficient flexibility of the HPO-YGO network and well-controlled process condition. The V_FB shift is also negligible under E_stress = 4 MV/cm with both polarities as shown in Fig. 78(b), which shows that $N_{\text{t}}^{0}$ values are lower than 9 × 10¹⁰ cm⁻² for both electron and hole traps in as-prepared LT-HPO-YGO/Ge gate stacks. Related to the low $N_{\text{t}}^{0}$, the initial gate leakage current in LT-HPO-YGO/Ge is comparable to that in the YGO/Ge stacks. SILC is also surprisingly small in LT-HPO-YGO/Ge gate stacks, as shown in Figs. 79(a) and 79(b) for both the positive and negative polarity stress cases. Figures 80(a) and 80(b) show J_G increase and D_it generation under the positive 9 MV/cm stress, respectively, for HPO-GeO₂, YGO, and LT-HPO-YGO gate stacks. The GeO₂/Ge stack is easily degraded though its initial characteristics appear rather better. Note also that LT-HPO-YGO may have the same trap generation origin as YGO, because the slope in Fig. 80(a) is almost the same in the form of ∼αtⁿ, while it is much better than YGO in terms of D_it generation. The stress field polarity dependence of Ge gate stack reliability is apparently the same as that of SiO₂/Si gate stacks, but it seems to be more significant. Although the poorer GeO₂/Ge interface is likely to be the origin, further study is needed.

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Furthermore, the effect of top high-k materials (YScO₃ and HfO₂) on gate stack reliability is discussed for the YGO-IL case for further EOT scaling. As shown in Fig. 81, YScO₃/YGO/Ge shows a much smaller V_FB shift than HfO₂/YGO/Ge under two kinds of high negative E_stress conditions. Although both have EOT = 0.8 nm, the V_FB shift as a function of the stress time differs significantly between them. This implies that top high-k films should be selected by taking account of their reliability, particularly for the sub-nm EOT region. YScO₃, unlike Hf on Ge, does not degrade the gate stack even if Y and/or Sc may diffuse to the interface, as already discussed in Fig. 66. Figure 82 demonstrates that, thanks to the suppression of trap generation, YScO₃/YGO/Ge can survive a much longer time than HfO₂/YGO/Ge under considerably high voltage conditions, although more data are obviously needed to discuss the breakdown lifetime. All the experimental results obtained so far indicate that the rigidity concept is quite useful for the reliability consideration of Ge gate stacks.

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A wrong view that GeO₂/Ge should be the best for Ge gate stack has often been addressed. We also considered that it would be. In this paper, we have proposed the new concept of the rigidity of dielectric films for achieving both reliable and scalable Ge gate stacks; resultantly, we have found that the GeO₂/Ge gate stack has an intrinsic weakness against electrical stress. We do not hesitate to say that a dielectric film with moderate rigidity should be employed to satisfy good initial passivation, process robustness, and long-term reliability simultaneously in scaled Ge gate stacks.¹²¹⁾ Nevertheless, there is no question about the fact that a detailed understanding of GeO₂/Ge should be the basis of Ge gate stack design.

The reliability study of Ge gate stacks started just a couple of years ago.^{56,126–128)} Most of reliability studies have focused on the BTI stress in Ge or Ge-rich SiGe p-MOSFETs, since p-MOSFETs are now in more urgent need. The interface defect generation models proposed so far have tried to explain experimental results by considering the defect distribution in space and energy. This is the same method as carried out in Si CMOS reliability assessment. Most of the proposals are based on the conventional band-diagram perspectives, and few studies from materials viewpoints have been reported. We have discussed Ge gate stack reliability from a more material engineering viewpoint in conjunction with well-controlled gate stack formation. We would now hesitate to quantitatively assess the reliability of Ge gate stacks. Nevertheless, we surely have to recognize that GeO₂/Ge is unlikely to meet the reliability requirements. This has also been recently reported by another group.¹²⁶⁾ The gate stack reliability has usually been discussed as a function of stress time, and then the degradation kinetics in gate stacks has been conjectured. However, the same strategy is not always applicable for new materials. We believe that a key guideline such as the rigidity is needed for establishing the reliability framework in Ge devices.

In metal/Ge junctions, the Fermi level of Ge is strongly pinned at the charge neutrality level (CNL) close to the valence band edge of Ge,^136,137) which means S ∼ 0 in Eq. (6.2). It is said that gap states above and below the CNL serve as acceptor- and donor-type states, respectively. The CNL is in principle determined in the semiconductor side. A more detailed explanation considering the density of states in the conduction and valence bands is found in textbooks.¹³⁰⁾ To systematically investigate FLP, we prepared metal/Ge junctions using various metals with a wide range of vacuum work functions in UHV. All metal/p-Ge showed ohmic and all metal/n-Ge junctions showed Schottky diode characteristics. The effective work function, which was calculated from the experimental SBH by assuming the simple definition of the work function in Fig. 83, is plotted by comparing with the work functions of pure metals reported¹³⁸⁾ in Fig. 84.¹³⁷⁾ The CNL at the metal/Ge interface is estimated by plotting the SBH as a function of the pure metal work function in Fig. 85,¹³⁷⁾ and is close to the branch point calculated for the bulk Ge.¹³⁹⁾ Note that, in this experiment, not only the work function but also the interface conditions such as inter-reaction, inter-diffusion and/or morphology should differ from metal to metal on Ge. This suggests that the Fermi level of a metal at a metal/Ge interface is intrinsically pinned at the CNL of Ge, although the FLP mechanism is still under debate and no consensus has been reached yet.¹³⁰⁾ It is also regarded as the fact that the Fermi level in Ge is fixed at the CNL. Thus, we infer that the FLP on Ge is caused by the so-called metal-induced gap states (MIGS) mechanism because it is the only intrinsic mechanism so far proposed for the FLP at metal/semiconductor interfaces. In addition, the MIGS is theoretically more appropriate for narrower energy band gap semiconductors such as Ge, although the MIGS model cannot generally characterize the FLP on any semiconductors. It would be significantly useful in Ge device technology that we could manage to control the intrinsic FLP on Ge.

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6.1.1. Fermi-level pinning modulation: tunnel contact.

Owing to the strong FLP on Ge, ohmic characteristics for p-Ge and Schottky ones for n-Ge were experimentally observed regardless of the metal work function. On the other hand, as already discussed in previous sections, the flat-band voltage (V_FB) and surface potential in Ge MIS capacitors are substantially modulated without showing the strong FLP at the metal/insulator and insulator/Ge interfaces, respectively. This suggests that the strong FLP observed at metal/Ge junctions should be substantially unpinned by inserting an oxide layer between metal and Ge. In addition, putting an insulator between the metal and Ge may alleviate the FLP because it may suppress the metal wave function evanescent into Ge. Thick oxide insertion, however, obviously cannot be used at source/drain junctions. Thus, we investigated the effect of inserting an ultrathin oxide (UTO) into the metal/Ge interface to alleviate the FLP.

Both n- and p-type Ge(100) substrates were used. GeO₂ was used as the UTO on Ge. We first checked Ge MIS capacitor characteristics with thick GeO₂ (15 nm). Both Au and Al electrodes were deposited on the same Ge substrate. In C–V characteristics at 1 MHz, the surface potential at the thick-oxide/Ge interface was of course controlled by gate bias, and a reasonable V_FB difference at 1 MHz (0.8 V) was obtained between Al and Au gate GeO₂/Ge MOS capacitors. Metal/Ge junctions on n- and p-Ge show Schottky and ohmic characteristics in Fig. 86(a), while very interestingly, the diode characteristics are totally changed by inserting thin GeO₂ film as shown in Fig. 86(b). The reversely biased current density increases on n-Ge and decreases on p-Ge by increasing the interfacial GeO₂ thickness, as shown in Figs. 87(a) and 87(b).¹⁴⁰⁾ This transition obviously indicates that the Fermi level of metal is effectively shifted toward the conduction band edge (CBE) of Ge by the UTO insertion, as expected above. Figure 88 shows the GeO₂ thickness dependence of SBH alleviation. With an increase in the GeO₂ thickness, the FLP on Ge is gradually alleviated, and it is seen that SBH goes back toward the value expected by the vacuum work function. Although the SBH estimated in metal/UTO/Ge junctions may include a potential drop across the UTO, the effective SBH enhancement observed on p-Ge cannot be simply explained by the potential drop. Furthermore, if the UTO film may act as the defect passivation at the interface, the SBH should shift more abruptly and then saturate with increasing GeO₂ thickness. Thus, the results seem to support the MIGS model that the wave function tailing from the metal into Ge is essentially involved in the FLP.

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Although we considered that the UTO insertion technique was the first proposal and demonstration for tuning the SBH when we presented experimental results at IEDM 2007,⁶⁰⁾ we later found that this FLP alleviation method had been proposed by Connelly et al. for the FLP on Si.¹⁴¹⁾ They reported that the SBH was modulated by 0.25 eV when an ultrathin Si₃N₄ film was inserted between Mg and Si from the MIGS suppression viewpoint. Now, the UTO insertion contact is called the tunnel contact using several insulators on Ge.^142–148) Since TiO₂, in particular, has a small band offset energy against the Ge (Si) conduction band edge, the tunnel resistance should be very small in terms of the tunnel contact.¹⁴⁷⁾

However, since the pinning parameter is still very small (∼0.2) after the UTO insertion, the Fermi level seems to still be strongly pinned. In addition, this fact does not necessarily prove that the MIGS model is logically correct, and it is debated that the UTO thicknesses reported in the literature might be rather thick in terms of the suppression of wave function tailing. It should be further studied. Nevertheless, this method is the first experimental demonstration from the engineering viewpoint that metal can make an ohmic contact on n-Ge without any doping.

6.1.2. Fermi-level pinning modulation: electron density tuning in metals.

After our demonstration of the UTO insertion effect on FLP alleviation on Ge, several methods for modifying the FLP without inserting an insulator have been reported. amorphous (a-) TiN deposited by sputtering was demonstrated to make an ohmic contact to n-Ge.¹⁴⁹⁾ Figure 89 shows J–V characteristics both on n- and p-type Ge with TiN deposited by rf-sputtering. Increasing the rf-power seems to shift the pinning position from the valence band edge to the conduction band side. The apparent CNL shift seems to be the same as in the nitride insertion cases.¹⁴²⁾ The authors have considered an amorphous interlayer as a key to the FLP modulation, but the detailed physics underlying this shift is still under investigation.¹⁵⁰⁾

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It has been reported that SBHs of metals such as Fe₃Si,¹⁵¹⁾ Mn₅Ge₃,¹⁵²⁾ Sn,¹⁵³⁾ and graphene¹⁵⁴⁾ on Ge deviate from the strong FLP trend. Recently, W-encapsulating Si cluster film insertion has also been reported.¹⁵⁵⁾ Most of those reports except graphene case maintain that the FLP on Ge is not determined by MIGS because SBH is modulated by changing the metal even in the direct metal/Ge structure. In case of graphene, they proposed the MIGS model because SBH changed with an increase in the number of graphene layers. Several UTO or ultrathin nitride (UTN) insertion methods reported in the literature actually seem to be in principle the same as ours, but the direct metal deposition cases are different in terms of both no potential barrier against the wave function tailing and the atomic ordering at the Ge interface in epitaxial metal cases. It is, however, difficult to conjecture the pinning mechanism because the work function has not been systematically characterized in those systems. As a result, the mechanism of FLP at metal/Ge interfaces is still controversial, although it is very favorable practically that various materials can be used as the ohmic metal on n-Ge.

Since SBH is in principle determined by both the metal work function and electron affinity of a semiconductor as shown in Fig. 83, the work function in metal is one of key elements in SBH. Therefore, let us consider what determines the work function in metals. It consists of both the bulk and surface parts, which is schematically described in Fig. 90(a). The bulk part Φ_b comes from many electron effects, while the surface part Φ_s is from the wave function evanescent to the vacuum, which forms the surface dipole.¹⁵⁶⁾ Although this view based on the jellium model is too simple for quantitative discussion, the work function trend in many simple metals can be described by this approach as shown in Fig. 90(b). With an increase in electron density in metals, the work function increases mainly due to the surface contribution increase. Since the surface part is in principle determined from the tunneling from the metal to vacuum, its penetration extent depends on the electron density and surface orientation of metals.¹⁵⁷⁾ We note that the surface part in the work function looks similar to the physical implication of MIGS originally proposed by Heine.¹⁵⁸⁾ A difference with respect to solid–vacuum interfaces is that the wave function tails oscillate at solid–solid interfaces due to the Bloch wave function nature in semiconductors, as schematically shown in Fig. 91. In more detail, the non-jellium contribution should of course be taken into account, but the electron density effect is expected to be qualitatively correct.^156,159)

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We have very recently studied the effects of metal on FLP from the aforementioned aspect. Technically speaking, if we believe that the FLP on Ge is mainly characterized by the MIGS model, we might control it by changing the electron density and surface orientation of the metal side, as expected from the work function theory. We prepared several kinds of germanides on n-Ge and measured their SBHs at room temperature. Although we do not presently know the exact work functions of germanides, the germanide with a rather low work function metal, GdGe_x shows the higher I_off current on n-Ge(100), as shown in Fig. 92(a). This implies the smaller SBH at the GdGe_x interface. More interestingly, GdGe_x on n-Ge(111) exhibits ohmic I–V characteristics as shown in Fig. 92(b),¹⁶⁰⁾ although a direct Gd/Ge junction does not show appreciable surface orientation dependence. Figure 92(c) shows the cross-sectional TEM image of GdGe_x/Ge(111), in which no interfacial layer is observed. In the preliminary XRD analysis, Gd₂Ge₃ is likely,¹⁶¹⁾ but a more detailed analysis is needed. The electron density in GdGe_x estimated by the Hall effect measurement was ∼7 × 10²¹ cm⁻³, which is ∼1 order of magnitude smaller than the electron density in conventional metals. Although the present result is not necessarily conclusive for the SBH formation mechanism on Ge, it is strongly suggested that the free electron density in metals has a significant effect on the SBH formation on Ge. The experiments are still preliminary but the results are exciting.

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Most of metal/Ge junctions reported so far^149–155) seem to be consistent with this view. We do not maintain that the FLP mechanism at any metal/semiconductor junctions should be understandable from the MIGS model. And, we do not think a single mechanism always determines the FLP for a given semiconductor, including Ge, but a couple of mechanisms might work together. We think that the MIGS dominant behavior comes from the fact that Ge is a special semiconductor with a narrow energy band gap and a branch point near the valence band edge. Resultantly, both methods in the UTO insertion and in the electron density tuning can suppress the wave function tailing into Ge. The latter effect seems to be applicable for Si as well, in the recent experiment using Bi electrode.¹⁶²⁾

Finally in this section, we would like to reconsider the work function Φ_M used in Eq. (6.2), in which Φ_M is the metal work function with the vacuum interface. As discussed in this section, the work function in itself consists of two components. One is the bulk component and the other is the surface one. This fact means that the work function is sensitive to the surface counterpart. Namely, the work function is not a material constant but should depend on what the counter material is. Now, we come to the question "Is the work function at the Schottky interface the vacuum one, Φ_M ?" In fact, Φ_M is very sensitive to the surface orientation and contamination. Therefore, we rewrite the metal work function on semiconductors as follows, by assuming that any finite shift from the Schottky limit may come from the work function modulation on semiconductors.

$$\begin{equation} \Phi_{\text{B}}=S(\Phi_{\text{M}}^{\text{V}}-\Phi_{\text{CNL}})+(\Phi_{\text{CNL}}-\chi)=\Phi_{\text{M}}^{\text{semi}}-\chi, \end{equation} \tag{ 6.3 }$$

where $\Phi _{\text{M}}^{\text{V}}$ and $\Phi _{\text{M}}^{\text{semi}}$ are the work functions in vacuum and on semiconductor, respectively. That is,

$$\begin{equation} \Phi_{\text{M}}^{\text{semi}}=S\Phi_{\text{M}}^{\text{V}}+(1-S)\Phi_{\text{CNL}}. \end{equation} \tag{ 6.4 }$$

This equation means that $\Phi _{\text{M}}^{\text{semi}}$ is determined by both Φ_M and Φ_CNL with the weight of S and 1 − S. In case of S = 1, $\Phi _{\text{M}}^{\text{V}} = \Phi _{\text{M}}^{\text{semi}}$, while generally $\Phi _{\text{M}}^{\text{semi}}$ should be affected by the intrinsic wave function evanescent from metal to semiconductor, which is considered as the MIGS origin, resulting in the interface dipole formation at metal/semiconductor interface. This is the intrinsic effect affecting the work function on semiconductors (insulators as well) in the pure limit. The interface has been generally considered as ($\Phi _{\text{M}}^{\text{V}} + \text{FLP}$), but note that $\Phi _{\text{M}}^{\text{V}}$ loses the physical meaning in a metal contacting with semiconductors. Thus, we would suggest that instead of such conventional view, the MIGS-type FLP can be regarded as the metal work function modulation ($\Phi _{\text{M}}^{\text{semi}}$ instead of $\Phi _{\text{M}}^{\text{V}}$) in the Schottky limit, although the MIGS view is important in terms of the fact that $\Phi _{\text{M}}^{\text{semi}}$ is affected by the CNL in the semiconductor.

This view does not necessarily exclude extrinsic effects such as defects on the FLP. Equation (6.4) can be rewritten as

$$\begin{equation} \Phi_{\text{M}}^{\text{semi}}=S^{\text{M}}\Phi_{\text{M}}^{\text{V}}+(1-S^{\text{M}})\Phi_{\text{CNL}}^{\text{MIGS}}. \end{equation} \tag{ 6.4′ }$$

Suppose that there is another pinning origin at the interface, S^D and $\Phi _{\text{CNL}}^{\text{D}}$, and that the pinning is described by Eq. (6.2) with $\Phi _{\text{M}}^{\text{semi}}$.

$$\begin{align} \Phi_{\text{B}}&=S^{\text{D}}(\Phi_{\text{M}}^{\text{semi}}-\Phi_{\text{CNL}}^{\text{D}})+(\Phi_{\text{CNL}}^{\text{D}}-\chi)\\ &=S^{\text{D}}S^{\text{M}}\bigg\{\Phi_{\text{M}}^{\text{V}}-\frac{1}{1-S_{\text{D}}S_{\text{M}}}[(1-S^{\text{M}})S^{\text{D}}\Phi_{\text{CNL}}^{\text{MIGS}}\\ &\quad+(1-S^{\text{D}})\Phi_{\text{CNL}}^{\text{D}}]\bigg\}\\ &\quad+\frac{1}{1-S^{\text{D}}S^{\text{M}}}[(1-S^{\text{M}})S^{\text{D}}\Phi_{\text{CNL}}^{\text{MIGS}}+(1-S^{\text{D}})\Phi_{\text{CNL}}^{\text{D}}]-\chi. \end{align} \tag{ 6.5 }$$

Therefore, by denoting S and Φ_CNL as

$$\begin{align} S&=S^{\text{D}}S^{\text{M}},\\ \Phi_{\text{CNL}}&=\frac{1}{1-S^{\text{D}}S^{\text{M}}}[(1-S^{\text{M}})S^{\text{D}}\Phi_{\text{CNL}}^{\text{MIGS}}+(1-S^{\text{D}})\Phi_{\text{CNL}}^{\text{D}}], \end{align} \tag{ 6.6 }$$

Equation (6.2) is obtained again. Note that two pinning mechanisms are involved in this formula, although an interaction between two origins is not taken into account. In case that S^M ∼ 0 ≪ S^D < 1 (probably Ge case),

$$\begin{equation*} \Phi_{\text{B}}=[S^{\text{D}}\Phi_{\text{CNL}}^{\text{MIGS}}+(1-S^{\text{D}})\Phi_{\text{CNL}}^{\text{D}}]-\chi, \end{equation*}$$

$$\begin{align} &\left\{ \begin{array}{l} S=0,\\ \Phi_{\text{CNL}}=[S^{\text{D}}\Phi_{\text{CNL}}^{\text{MIGS}}+(1-S^{\text{D}})\Phi_{\text{CNL}}^{\text{D}}] \end{array} \right. . \end{align} \tag{ 6.7 }$$

Thus, it is expected that Φ_B has nothing to do with $\Phi _{\text{M}}^{\text{V}}$, and that Φ_CNL is affected by the extrinsic interface effect. Since Eq. (6.2) in itself is the phenomenological formula, more detailed analysis will not be meaningful. However, when the metal side effect on the FLP is considered as discussed above, the relationship between SBH and metal work function will become physically clearer, although the view that MIGS effect is equivalent with the work function modulation of metal at the Schottky interface should be further investigated theoretically. We think that this view might be true in case of semiconductors with relatively narrower energy band gap. This consideration discussed here may seem to be strange, because the MIGS theory is now widely accepted in this community. However, the work function modulation model may also be feasible, if it cannot be true that the work function of a metal in contact with semiconductor is as the same as that in vacuum. For more detailed discussion, the interaction of the metal with valence band electrons should be taken into consideration, which substantially determines the CNL in the semiconductor side, while it is no need in the vacuum case, although more rigorous theory is obviously needed for fully understanding metal/semiconductor interfaces.

The lower doping solubility is a big concern in Ge CMOS technology in addition to the FLP in terms of rather high contact resistance and high diffusion layer resistance. A big problem in doping into Ge is not only the active carrier concentration but also a rather larger junction leakage current often ascribed to the narrower energy band gap of Ge than that of Si. This is definitely a very weak point in the low-power CMOS application, even though the on-performance is markedly high. The ion-implantation may generate defects in Ge and possibly increase the leakage current. Defects in Ge might be different from those in Si.¹⁶³⁾

The first challenge is how to achieve carrier concentrations up to the solubility limit. In case of phosphorus, this limit is reported to be 2 × 10²⁰ cm⁻³,¹⁶⁴⁾ but the actual concentration of n⁺ region made by the ion implantation is substantially lower than that. Several engineering efforts have been carried out for enhancing the dopant activation. The passivation of vacancy defects working as acceptors was reported by co-implantation of F.¹⁶⁵⁾ It was also reported that the cryogenic ion implantation or multiple implantations and multiple annealing (MIMA) lowered the vacancy concentration.^166,167) All of those efforts are concerned with how to reduce implantation-induced vacancy formation in Ge because defects may serve as the counter (acceptor) dopants. In conjunction with H₂ annealing discussed in Sect. 3.4, we found that oxygen in Ge might reduce the n⁺/p junction leakage current.¹⁰¹⁾ Ion implantation damage in Ge was actually observed by the Raman spectroscopy for both P and Ge implanted Ge substrates even after 600 °C annealing, as shown in Fig. 93.¹⁶⁸⁾ The annealing temperature dependence of the full width at half maximum (FWHM) in the Raman peak of the implanted Ge is compared with that of the Si case in Fig. 94. The FWHM in Si was recovered to the initial FWHM value, while that in Ge was not even in annealing at 800 °C for 30 s in N₂. This fact implies that it is not easy to recover the crystalline quality in Ge after the ion implantation. Therefore, new doping methods without using ion implantation, such as the spin-on dopant¹⁶⁹⁾ and the gas-phase doping,¹⁷⁰⁾ have also been investigated. The annealing process optimization with the laser annealing (LA) after the ion implantation demonstrated higher activation over 1 × 10²⁰ cm⁻³.^171,172) Figure 95 shows the carrier concentration comparison between LA and RTA after the ion implantation. It clearly shows that LA can enhance the dopant activation, while the I_on/I_off ratio in case of LA is much worse than that in RTA.¹⁷³⁾ On the other hand, the low temperature preannealing, followed by LA, achieved a high I_on/I_off ratio.¹⁷¹⁾ Although we can optimistically say that there is room for improving the n⁺/p junction properties, there is a concern on whether a non-equilibrium process can maintain the high activation state in the following thermal process or not. In any case, the ion implantation technique poses a high hurdle against the Ge p/n junction formation. This is the big issue that further efforts are obviously needed.

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Next, let us discuss a slightly different method, the "snowplow" effect in Ge, to realize low-temperature dopant activation. The snowplow was studied in Si process technology many years ago.¹⁷⁴⁾ Dopants implanted into Si were segregated like a "snowplow" and activated at the silicide/Si interface through the silicide formation process at a relatively low temperature. We studied the snowplow process of phosphorus (P) in Ge.¹⁷⁵⁾ Ni was used as the germanide metal from the viewpoints of a low reaction temperature with Ge and the low resistivity (∼22 µΩ·cm) of its germanide (NiGe).¹⁷⁶⁾ The germanide reaction was carried out in N₂ at temperatures ranging from 200 to 500 °C. XRD patterns showed Ni or Ni₅Ge₃ phases at 200 °C and a well-crystallized NiGe phase above 300 °C. The schematic images of the snowplow process are shown in Fig. 96(a). P ions were implanted with the acceleration voltage of 50 kV and the dose of 1 × 10¹⁵/cm². A 50-nm-thick Ni film was deposited in UHV, and then Ge substrates were thermally annealed in N₂. Ni (including NiGe)/Ge junctions without P ion implantation, of course, showed the Schottky characteristic on n-Ge and an the ohmic one on p-Ge, respectively. Figures 96(b) and 96(c) show that the transition from a rectified I–V to an ohmic one on n-Ge substrate is observed between 200 and 300 °C. Note that the germanide reaction actually lowers the P activation temperature in Ge to 300 °C. Although we found the low-temperature activation of phosphorus experimentally, we did not verify the phosphorus profile. Later, it was reported that the phosphorus pile-up was not observed clearly.¹⁷⁷⁾ As a result, the snowplow was effective to lower the activation temperature, but it might not be efficient to enhance the doping density.

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Here, we would like to report another aspect of the junction leakage current in Ge. The lateral leakage path along the peripheral area is generally a concern due to the poor interface passivation and/or electric field enhancement, as schematically shown in Fig. 97. Considering the lateral leakage in addition to the water etching of GeO₂, we have so far employed Y₂O₃ passivation around the contact area in the FET fabrication process. Here, we discuss the passivation-layer dependence of n⁺/p junction leakage currents in more detail. Three kinds of passivation layers — SiO₂, Y₂O₃, and YGO — were investigated. In the gate stack, the YGO/Ge interface is the best of the three. GeO₂ was not investigated because it was easily etched by the wet process. Figure 98 shows the leakage current histogram for n⁺/p junctions with three passivation layers. For circular junctions with 100 and 200 µm in diameter, the leakage current at junctions passivated by YGO is considerably lower than those of the others. This is quite reasonable when considering the gate stack properties, but it is surprising that the leakage current is strongly dependent on the peripheral passivation.¹⁷⁸⁾ Conversely speaking, we can reduce the junction leakage current more by taking care of the peripheral passivation. We have actually achieved the on/off current ratio of more than 10⁶, at |V| = 1 V at the n⁺/p junction. Therefore, most of rather high junction leakage currents reported so far are not intrinsic but mainly result from the poor peripheral passivation. By optimizing doping and annealing processes in addition to paying attention to the lateral passivation scheme, the leakage current can be reduced much further.

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It is interesting to see that the junction leakage issue includes the same technical challenge as gate stacks and that YGO solves both challenges. In the Si technology, the passivation and gate stacks are automatically satisfied with SiO₂. This is a great point of the SiO₂/Si system now after all.

Extremely thin Ge on insulator (ET-GeOI)¹⁷⁹⁾ is analogous to ET-SOI¹⁸⁰⁾ in Si technology, and is rather promising, thanks to the junction leakage reduction as well as the DIBL suppression from the device structure viewpoint. We investigated electron and hole mobilities in the front and back channels in GeOI MOSFETs.¹⁸¹⁾ The starting substrate was a 100-nm-thick Ge(100) GeOI wafer with a very low doping (N_D < 1 × 10¹⁴ cm⁻²) fabricated by the Smart Cut™ technology on SiO₂/Si. 20-nm-thick Y₂O₃ was deposited by rf-sputtering, and phosphorus was implanted through the Y₂O₃ layer for the S/D formation. The two-step oxidation (HPO-LOA) of Y₂O₃ was employed for the gate stack formation. The gate stack structure is schematically shown in Fig. 99(a). The interface layer was not pure GeO₂ but Y-doped GeO₂. The Ge thickness was thinned down to 9 nm, as shown by the cross-sectional TEM image in Fig. 99(b). Figures 100(a) and 100(b) show well-behaved transfer characteristics (I_DS–V_GS) of 9-nm-thick GeOI n- and p-MOSFETs under V_BG = 0 V. The off leakage currents are well suppressed as expected. The peak electron mobility in a 9-nm-thick GeOI n-MOSFET was 254 cm² V⁻¹ s⁻¹, which is considerably lower than expected. Figures 101(a) and 101(b) show the Ge thickness dependences of electron and hole mobilities at N_s = 1 × 10¹² cm⁻² for both the front and back channels of GeOI n- and p-MOSFETs. The electron mobility at the front channel (GeO₂/Ge interface) decreases monotonically with the reduction in Ge thickness and drops sharply between 45 and 25 nm of Ge thickness, while the back channel (Ge/SiO₂ interface) shows the very low mobility even for thick GeOI cases. In case of hole mobility, the same trend is observed but it is much more moderate.¹⁸¹⁾

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The front channel mobility degradation clearly comes from the poor back interface of the Ge channel on SiO₂. It is also clear that the Ge crystallinity is also very poor near the back interface (Ge/SiO₂). Thus, "back interface-aware" GeOI fabrication (bonding process and/or Ge-friendly BOX material) will be required for high-performance GeOI devices. We hope that it will be possible because the gate stack technology has been dramatically improved by taking care of the Ge interface, as discussed in Sects. 2 and 3. Very recently, Yu et al. have demonstrated 3-nm-thick GeOI FET operation by taking special care of the back interface.¹⁸²⁾ Although the mobility is still not high, this work suggests that ET-GeOI FETs are potentially promising for the scaling by optimizing the back interface from the process and material viewpoints. Note that this consideration is also applicable for the local Ge channel. In case of Ge FinFETs, this optimization will not be a problem because both front and back interfaces are gate stack channels. The Ge condensation method is completely different GeOI preparation technique from the Smart Cut™ process. Those who are interested in this technique should see Refs. 183 and 184.

To reduce the parasitic resistance in source and drain regions, metal source/drain FET has long been investigated in Si. Since the Schottky barrier height is a key parameter for designing the device, the almost perfect FLP at the metal/Ge interface has been negatively considered for n-MOSFETs, while in case of p-MOSFETs in Ge, it is rather easy to make metal source/drain MOSFET on Ge¹⁸⁵⁾ because any metal can make an ohmic contact with p-Ge.

As discussed in Sect. 6.1, we know that the FLP on Ge is alleviated by inserting UTO between metal and Ge. Therefore, we applied this interface engineering method in the fabrication of metal source/drains for Ge n-MOSFETs on p-Ge.¹⁴⁰⁾ Figures 102(a) and 102(b) show a schematic view of fabricated Al source/drain Ge n-MOSFET and the cross-sectional TEM image of the tunnel contact at the Al/p-Ge interface. About 2-nm-thick GeO₂ was formed on a p-Ge substrate to achieve an ohmic contact between the Al source/drain and the electron inversion channel of Ge. As shown in Fig. 102(c), I_S–V_DS characteristics in the low-V_DS region indicate a very low parasitic resistance despite the absence of n-type impurity doping in the source region. Considering a low solubility of dopants in Ge, metal source/drain FET is a plausible candidate for the ultrashort-channel Ge FET in which the fringing field works more effectively.¹⁸⁶⁾ The present demonstration was carried out on the bulk Ge substrate, but it is obviously more favorable to fabricate on GeOI in terms of the leakage current reduction. Yamamoto et al. have recently demonstrated metal source/drain n- and p-MOSFETs using TiN contact.¹⁸⁷⁾ As discussed in Sect. 6.1, several methods have been reported to enable the metal contact to the n-Ge substrate ohmic. Thus, ultra-short channel metal source/drain n-channel Ge FETs will be more elegantly demonstrated.

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Junctionless (JL) FETs using Si nanowire FETs were proposed. The device image and operation principle are schematically shown in Fig. 103(a)¹⁸⁸⁾ and Fig. 3(b),¹⁸⁹⁾ respectively. JL-FETs have the advantages that no source/drain (S/D) formation is needed and that carrier transport is less sensitive to the channel interface. Simulations-based analysis for JL-FETs have been carried out by many researchers.^190,191)

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We tried to make JL-FETs on Ge. A heavily doped p-type GeOI wafer with 100-nm-thick buried SiO₂ was used for p-channel Ge JL-FET. The SIMS analysis showed that the p-type dopant concentration was around 10¹⁹ cm⁻³. Mesa-type Ge islands were defined by wet etching and substrate Si was used as the back-gate electrode. As the Ge thickness was decreased to less than 30 nm, the drain current was modulated by the back-gate bias as shown in Figs. 104(a) and 104(b).¹⁹²⁾ The I_on/I_off ratio of a device on 11-nm-thick Ge was larger than 10⁴ at V_GS between −40 and 40 V. The JL-FET channel is a resistor in case without the gate voltage, while the majority carriers (holes) flow through the Ge layer under a negative V_GS. When a positive V_GS is applied, holes are electrostatically depleted and drain current decreases. Therefore the depletion layer width is a critical parameter for JL-FETs to achieve the off-state. The maximum depletion layer width of Ge with an impurity concentration of 10¹⁹ cm⁻³ is estimated to be about 11 nm, considering the dielectric constant and intrinsic carrier concentration of Ge to be 16 and 2.4 × 10¹³ cm⁻³ at room temperature, respectively. The output characteristics of the 11-nm-thick Ge JL-FET are shown in Fig. 104(c). The effective mobility of 11-nm-thick Ge JL-FETs was roughly 100 cm² V⁻¹ s⁻¹ and not sensitive to the gate bias, while in conventional inversion-mode MOSFETs the minority carriers are accumulated at the semiconductor/insulator interface and the carrier mobility is sensitive to the interface. Furthermore, since in case of p-channel Ge JL-FETs, all metals make ohmic contacts with p-Ge, it is favorably considered that the contact resistance in p-channel Ge JL-MOSFETs is not affected by the unexpected doping density fluctuation in Ge. The results have obviously been much improved by employing double-gated JL-FETs.¹⁹³⁾

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We expect that Ge JL-FETs should show better performance than Si one because of the less coulombic scattering due to the higher dielectric constant of Ge. This beneficial point of Ge in the carrier mobility is more significant in the more heavily doped region. Concerning n-channel Ge JL-FETs, it is worthwhile mentioning that the electron mobility in bulk n-Ge (1000 cm² V⁻¹ s⁻¹) is one order of magnitude higher than that in n-Si (100 cm² V⁻¹ s⁻¹) with N_sub = 10¹⁹ cm⁻³. Thus, n-channel JL-FETs on Ge will be much more attractive than those on Si from the mobility enhancement viewpoint. As a matter of fact, Si JL-FETs on heavily doped SOI have shown a substantially low mobility because of the significant Coulomb scattering. Figure 105 clearly shows a significant advantage of heavily doped Ge, in which an enhancement of the bulk electron mobility ratio, μ_Ge/μ_Si was calculated using the following equation based on the Brooks–Herring model for the Coulomb scattering.¹⁹⁴⁾

$$\begin{align} \mu&=\frac{3.68\times 10^{20}\,\text{cm$^{-3}$}}{N_{\text{I}}}\frac{1}{Z^{2}}\left(\frac{k}{16}\right)^{2}\left(\frac{T}{100K}\right)^{1.5}{}\cdot F(\beta_{\text{BH}}),\\ F(\beta_{\text{BH}})&=\cfrac{1}{\biggl(\cfrac{m}{m_{0}}\biggr)^{1/2}\Biggl[\log(1+\beta_{\text{BH}}^{2})-\cfrac{0.434\beta_{\text{BH}}^{2}}{1+\beta_{\text{BH}}^{2}}\Biggr]},\\ \beta_{\text{BH}}&=\left(\frac{k}{16}\right)^{1/2}\frac{T}{100K}\left(\frac{m}{m_{0}}\right)^{1/2}\left(\frac{2.08\times 10^{18}\,\text{cm$^{-3}$}}{n}\right)^{1/2}, \end{align} \tag{ 7.1 }$$

in which β_BH is the Brooks–Herring parameter.

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Figure 106 shows well-behaved output characteristics of n-channel Ge JL-FET with 15-nm-thick Ge. The electron mobility, however, is rather low (100–200 cm² V⁻¹ s⁻¹), which is probably due to the fact that electrons may be more sensitive to the poor interface Ge quality than expected. Nevertheless, the mobility with 34-nm-thick Ge was actually increased to ∼800 cm² V⁻¹ s⁻¹,¹⁹⁵⁾ although the off-state leakage current was poor. It suggests that further interface control in the Ge channel will enable to achieve high performance Ge JL-FETs by making the best of highly doped Ge advantages.

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Heavily doped semiconductors are now used not only for source/drain but also for the JL-FET channels discussed previously. Meanwhile, it is well known that the heavy doping of impurities may modify semiconductor properties such as the energy band gap narrowing¹⁹⁶⁾ and the elastic constant modulation.¹⁹⁷⁾ These phenomena were studied several decades ago experimentally and theoretically. It is, however, still difficult to discriminate between free carrier and dopant effects. We paid attention to the fact that a back-gated GeOI FET could be used for separating the free-carrier effect from the dopant one. Optical analyses are actually available from the top surface of GeOI FETs under the back bias application, which can only change the carrier density.

Bottom-gated FETs on lightly doped GeOI wafers were fabricated with Y₂O₃ passivation on the top surface, which could reduce non-radiative surface recombination.¹⁹⁸⁾ The schematic image is shown in Fig. 107. In Fig. 108, the Raman shift in the GeOI FET is clearly seen to the lower wave number in the negative back bias (hole accumulation), while it does not change in the positive one (electron accumulation).¹⁹⁹⁾ Furthermore, since the FWHM of the Raman spectra does not change at all even in the hole accumulation (data not shown), the Raman shift will not be due to the so called Fano effect, which has often been discussed for explaining the Raman shift in heavily doped semiconductors.²⁰⁰⁾

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Microscopic photoluminescence (PL) measurements were also carried out in the same sample as a function of carrier density with a fixed dopant density. PL peak positions in GeOI FETs are shown in Fig. 109 together with the drain current.²⁰¹⁾ The PL peak position shifts to a lower energy with the increase in the number of free carriers of both polarities. This experiment enables us to characterize the free carrier effect on the energy band gap narrowing under a fixed dopant density. To our knowledge, this is the first observation that only free carriers can change the optical phonon at the Γ-point and energy band gap.

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Free carrier effects on both Raman and PL results may be intuitively understandable by considering the covalent bonding of two atoms under variable carrier density.²⁰¹⁾ The results presented here may be evidence that the rigid phonon and rigid energy band gap models are more or less violated in the highly carrier-accumulated region in Ge.²⁰²⁾ Although a more quantitative analysis will be needed to understand free carrier effects, new applications such as field-effect photonic devices might hopefully be invented.