Influence of work function variation of metal gates on fluctuation of sub-threshold drain current for fin field-effect transistors with undoped channels

Variability of transistor characteristics emerges as a critical obstacle to further scaling of the transistor dimensions.^1–5) Variability of the threshold voltage (V_t) has been characterized mainly for benchmarking the variability of transistor characteristics.^1,3,5,6) In addition to the V_t variability, care must be take for that of off-state current (I_off) which determines the stand-by power of the circuits and that of on-state current (I_on) which determines the bottleneck of the circuit performance. It was reported recently that V_t defined at the sub-threshold condition fluctuates differently from that at the strong inversion in bulk-planar metal–oxide–semiconductor field effect transistors (MOSFETs), and was characterized as fluctuation of current–onset voltage (COV).^7,8) The COV fluctuation is considered as an additional origin of I_on–I_off fluctuation together with the V_t variation itself as the main origin. The origin of the COV fluctuation was revealed to be anomalous sub-threshold leakage caused by the potential non-uniformity due to random dopant fluctuation (RDF) in the bulk-planar MOSFETs.^7,8) In case of the fully-depleted silicon-on-insulator (FD-SOI) transistors, reduced COV fluctuation is achieved by the elimination of the RDF.⁹⁾

In order for suppressing short channel effects (SCE) of bulk-planar MOSFETs which is the major obstacle against the transistor scaling together with the variability issue, fin field-effect transistors (FinFETs) have been considered to be effective,^10–14) and the FinFETs are actually introduced from 22 nm technology.¹⁵⁾ Thanks to the double gate structure with superior SCE immunity even with an undoped channel, the FinFETs with metal gates (MGs) are effective to suppress the variability caused by the RDF.¹³⁾ The dominant origin of the V_t variability for the MG-FinFETs with the undoped channel is recognized as the work function variation (WFV) caused by the grains of the polycrystalline MG.^13,16) The WFV can be suppressed by using an amorphous MG.¹⁷⁾ It has been demonstrated that the FinFETs with the amorphous MG exhibit well-suppressed V_t variability^18,19) and also suppressed COV fluctuation.²⁰⁾ In this work, the COV fluctuation was examined comprehensively for the undoped channel FinFETs with MGs having different WFV. By comparing the results of the COV fluctuation analysis between polycrystalline TiN and amorphous TaSiN MGs both for the n- and pMOS FinFETs, origin of the COV fluctuation in the MG-FinFETs is discussed in detail.

As the material of the amorphous MG for the FinFETs, TaSiN was used because of its thermal stability and suitability for a gate-first process.^21–23) As reported in Refs. 21 and 22, the TaSiN film was deposited by sputtering a TaSi₂ target with Ar/N₂ plasma, and the deposited TaSiN film was confirmed to be amorphous by X-ray diffraction (XRD) analysis and plane-view transmission electron microscopy (TEM) even after rapid thermal annealing (RTA) equivalent for source/drain (S/D) dopant activation.¹⁸⁾ A polycrystalline TiN gate, which is commonly investigated as a gate-first MG,^6,24–26) was also used as the MG of the FinFETs for the comparison. These MG-FinFETs were fabricated by a gate-first process flow (Fig. 1) for the variability analysis. Fin channels with (110)-oriented sidewalls were fabricated from a (100) SOI wafer, followed by growth of a 2-nm-thick thermal oxide as gate dielectrics. The TaSiN MG was deposited by sputtering with N₂/Ar flow of 4%.^18,19) The TiN MG was deposited by sputtering with N₂/Ar flow of 17%.²⁵⁾ The thickness of both the TaSiN and TiN MGs is set at 10 nm on the fin sidewalls. N⁺-doped polycrystalline Si was deposited on the MGs and was used as a hard mask in the gate patterning process. The process conditions after the gate patterning are identical for the TaSiN and TiN MG cases. Cross section of the fin channels with the TiN and TaSiN MGs and the nano-beam diffraction patterns for the MGs are shown in Fig. 2. Unlike the TiN MG with the morphology and the diffraction spot pattern reflecting the polycrystalline nature, the TaSiN MG exhibits the amorphous diffraction pattern and the film morphology more homogeneous on the fin sidewalls.

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Variability of the electrical characteristics was examined for the FinFETs with the identically designed gate length (L_g) of 70 nm. The channel width (W_g), which equals to twice the fin height (H_fin), is designed to be 100 nm. Fluctuation in the drain current versus gate voltage (I_d–V_g) characteristics for n- and pMOS FinFETs are compared between the TiN and TaSiN MG cases as shown in Fig. 3. Sample number of the FinFETs for the variability analysis is 48 for each condition of the L_g design, the MG and the channel type. The amorphous TaSiN MG exhibits smaller fluctuation of I_d–V_g curves than the TiN MG does both for the n- and pMOS FinFETs. The Pelgrom plot¹⁾ is obtained by measuring V_t fluctuation for variously designed L_g (Fig. 4). The V_t mismatch for the paired transistor is used to evaluate the local variability.^1,5) The amorphous TaSiN MG suppresses the V_t variability effectively thanks to the suppressed WFV. The n- and pMOS FinFETs exhibit almost identical amount of the variability for both the case of TiN and TaSiN. Namely, the V_t variability does not depend on the channel type but on the WFV of the MGs. The slope of the Pelgrom plot (A_Vt), which is commonly used as the indicator of the variability robustness against the scaling^{1,3,5–8,13,16,18,19,26–30)}, is summarized in Fig. 5. The TaSiN MG significantly suppresses the A_Vt value in comparison to the TiN case and achieves A_Vt = 1.34 mV µm for the nMOS and V_d = 50 mV case, which is the smallest one reported for MG-FinFETs.^{13,16,26–30)} The saturation condition (|V_d| = 1 V) gives increased A_Vt values with regard to those at |V_d| = 50 mV. The increased A_Vt is explained that the contribution of drain-induced barrier lowering (DIBL) fluctuates and increases the V_t variation as reported in Ref. 6.

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In order to analyze the COV fluctuation, V_t is defined in the saturation I_d–V_g characteristics as shown in Fig. 6. Representing the sub-threshold condition, V_t is defined by constant current criteria [V_g at I_d = (W_g/L_g) × 10⁻⁸ A] and is denoted as V_tc.⁸⁾ Representing the strong inversion condition, the V_g intercept of the tangent line with the maximum slope of $I_{\text{d}}^{1/2}$–V_g curve is used and denoted as V_tex. The amount of the COV is defined as V_CO = V_tex − V_tc. Correlation between V_tc and V_tex for the identical design (L_g = 70 nm) and for the saturation condition (|V_d| = 1 V) is shown in Fig. 7. The TiN-MG nMOS case exhibits significant deviation of the plots from the regression line in comparison to the other cases. Namely, the V_t values defined at the sub-threshold condition and at the inversion condition fluctuate differently for the TiN nMOS case. In order to analyze the deviation quantitatively, the statistics of the COV fluctuation are summarized in Fig. 8. In case of the TiN MG, the nMOS FinFETs exhibits significantly larger fluctuation of the COV than the pMOS FinFETs do. In case of the TaSiN MG, on the other hand, the COV fluctuation is suppressed at the identical level both for the n- and pMOS FinFETs. Namely, only the TiN-MG nMOS FinFETs exhibit the anomalously increased fluctuation of the COV.

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The origin of the anomalous COV fluctuation for the TiN nMOS case is discussed as follows. Since the COV is obtained from the saturation I_d–V_g curves, the DIBL fluctuation may affect the COV fluctuation. The correlation between the COV and DIBL fluctuation was examined as shown in Fig. 9. There is no significant correlation between the COV and DIBL for all the cases, namely regardless the gate materials and the channel types. Thus, we consider that the DIBL is not the origin of the different behavior of the COV fluctuation. As reported for bulk-planar MOSFETs, a localized potential valley in the channel reflecting the non-uniformly distributed dopants causes anomalous leak current in the sub-threshold condition, resulting in COV fluctuation.^7,8) In the case of the undoped channel FinFET with the suppressed influence of the RDF, the WFV and the interface trap charges are responsible for the potential non-uniformity in the channel.³¹⁾ Interface trap density (N_it) in the fin channel was evaluated by a charge pumping method³²⁾ for the TiN and TaSiN MG cases, and the amount of N_it for the TiN and TaSiN MGs was confirmed to be almost identical.^18,19) Thus, the difference in the potential non-uniformity in the channel is dominantly caused by the difference in the WFV between the TiN and TaSiN MGs.

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The orientation of the polycrystalline TiN films deposited by the same condition as that for the TiN MG of the FinFETs was examined by XRD as shown in Fig. 10. The grains in the TiN film have dominant (100) orientation. It was also reported that TiN films deposited by sputtering are composed of dominant (100) grains having work function (WF) of 4.6 eV together with sub-dominant (111) grains having WF of 4.4 eV.^33,34) Figure 11 shows the schematic explanation for the anomalous COV fluctuation of the TiN-MG nMOS FinFETs. In the nMOS case, the sub-dominant grains having lower WF form a localized potential valley for electrons at the source edge, resulting in the anomalous leak current. In the pMOS case, the dominant grains having higher WF determine the bottom of potential for holes and the localized potential increase due to the sub-dominant low-WF grains negligibly affects the leak current. The anomalous leak current for the nMOS case causes the additional fluctuation of V_t at the sub-threshold condition, resulting in the increased COV fluctuation. At the strong inversion condition, on the other hand, V_t reflects the averaged potential in the channel^7,8) and is less affected by the potential non-uniformity. In the case of the amorphous TaSiN MG with the well-suppressed WFV, the leak current is negligibly influenced by the potential non-uniformity both for the n- and pMOS cases. Thus, thus COV fluctuation is suppressed at the identical level both for the n- and pMOS FinFETs with the TaSiN MGs.

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Benchmarking of the COV fluctuation with regard to the bulk planar MOSFETs⁸⁾ is summarized in Fig. 12. Generally, the MG FinFETs with the undoped channel exhibit smaller COV fluctuation due to the RDF reduction than the bulk planar MOSFETs do. In the case of the undoped channel FinFETs with suppressed influence of the RDF, influence of the WFV in the gate material significantly emerges as the dominant source of the COV fluctuation. Anomalous COV fluctuation due to the WFV of the polycrystalline MGs can be suppressed significantly by using the amorphous MGs with the well-suppressed WFV.

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The COV fluctuation, which reflects anomalous fluctuation of the sub-threshold drain current, is analyzed for the undoped-channel FinFETs with polycrystalline TiN and amorphous TaSiN MGs. The TiN-MG nMOS FinFETs exhibits anomalously large fluctuation of the COV in comparison to the other cases. This COV fluctuation is caused by the WFV due to the polycrystalline grains of TiN and is effectively suppressed by using the amorphous MG with well-suppressed WFV.