Mobility enhancement in heavily doped 4H-SiC (0001), (110), and (100) MOSFETs via an oxidation-minimizing process

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have attracted much attention as high-efficiency power devices. ^1–4) However, the performance of SiC MOSFETs has been far from their full potential, which is determined by the physical properties of SiC, because of the low channel mobility due to the high density of states at the SiC/SiO₂ interface ^5–13) and the low drift mobility in the inversion layer. ^14–27) Although the channel mobility can be improved by annealing in nitric oxide (NO) after the formation of a gate stack, the high channel resistance still dominates the total on-resistance for medium-voltage (∼1 kV) SiC MOSFETs. To overcome this problem, most commercial SiC MOSFETs utilize a very short channel structure. However, for a sub-micron channel length, short-channel effects may occur depending on the acceptor concentration in the p-body region. ^28–32) Further reduction in on-resistance cannot be achieved only by reducing the channel resistance through shortening the channel length. Thus, a reduction in the interface state density (D_it) is necessary for further improvement of on-resistance in SiC MOSFETs. ^33–36)

We have recently found that oxidation of SiC induces interface defects and that H₂ etching prior to oxide film formation is a key to obtaining a high-quality 4H-SiC (0001)/SiO₂ interface. ^37–39) Three factors are important for obtaining a high-quality interface: (i) H₂ etching of SiC surface, (ii) SiO₂ formation without oxidation of SiC, and (iii) interface nitridation. A very low D_it (2–6 × 10¹⁰ cm⁻² eV⁻¹) and high channel mobility (>80 cm² V⁻¹ s⁻¹) have been obtained using a process that includes these steps.

Although the above process reduces the density of interface defects and enhances channel mobility, the acceptor concentration (N_A) of the p-body for the reported MOSFET was 1 × 10¹⁵ cm⁻³, which is extremely low compared with that used for practical MOSFETs. In addition, MOSFETs on other faces than (0001) have not been investigated. High channel mobilities (>90 cm² V⁻¹ s⁻¹) have been obtained for (11$\bar{2}$0) and (1$\bar{1}$00) MOSFETs with the gate insulator formed by oxidation and NO annealing. ⁴⁰⁾ These faces are promising for the vertical sidewalls of trench-type SiC MOSFETs.

In this study, we investigate the effects of the process that minimizes oxidation of SiC on the channel mobility of heavily doped 4H-SiC (0001), (11$\bar{2}$0), and (1$\bar{1}$00) MOSFETs (1 × 10¹⁷–5 × 10¹⁸ cm⁻³). As in the case of the (0001) face, this process effectively reduced D_it for the SiC/SiO₂ structure fabricated on (11$\bar{2}$0) and (1$\bar{1}$00) faces. The fabricated (0001), (11$\bar{2}$0), and (1$\bar{1}$00) MOSFETs showed a marked improvement in channel mobility.

For characterization of D_it, n-type MOS capacitors were fabricated on n-type 4H-SiC (0001), (11$\bar{2}$0), and (1$\bar{1}$00) epilayers on n-type substrates. The SiC (11$\bar{2}$0) and (1$\bar{1}$00) substrates were prepared by vertically slicing ingots grown on (000$\bar{1}$). The doping concentrations of the epilayer were 5 × 10¹⁵ − 3 × 10¹⁶ cm⁻³. After RCA cleaning, samples were etched in H₂ ambient at 1350 °C and 0.1 MPa for 8–15 min. The gate oxides were formed via plasma-enhanced chemical vapor deposition (PECVD) at 400 °C, which resulted in an oxide thickness of 30–35 nm. For comparison, we also prepared MOS capacitors with oxides formed via dry oxidation at 1300 °C. Finally, NO annealing (1250 °C, 70 min) was performed. Here, "H₂-CVD-NO" denotes samples with a gate oxide formed via H₂ etching, SiO₂ deposition, and NO annealing, and "Ox-NO" denotes samples with a gate oxide formed via thermal oxidation and NO annealing. The gate material was Al.

Lateral n-channel MOSFETs were fabricated on p-type 4H-SiC (0001), (11$\bar{2}$0), and (1$\bar{1}$00) epilayers. The N_A values for the p-type epilayers were 1 × 10¹⁷ cm⁻³ and 1 × 10¹⁸ cm⁻³ for (0001) and (11$\bar{2}$0) and 3 × 10¹⁷ cm⁻³ and 5 × 10¹⁸ cm⁻³ for (1$\bar{1}$00). The gate oxide was formed in the same manner as that for the MOS capacitors (thickness: 30–35 nm). Al electrodes were deposited onto the source and drain regions and ohmic contact annealing was conducted for 4 min at 400 °C. Gate electrodes were formed by Al deposition. The channel length and width of the MOSFETs were 100 μm and 170 μm, respectively.

Figure 1 shows the energy distributions of D_it near the conduction band edge (E_c) extracted using the high (1 MHz)-low method for the (0001), (11$\bar{2}$0), and (1$\bar{1}$00) MOS capacitors. Compared with the D_it for the Ox-NO samples, that for the samples fabricated using the H₂-CVD-NO process was significantly lower for all three faces. The D_it values (energy range of E_c − 0.2 eV to E_c − 0.5 eV) are as low as about 4–8 × 10¹⁰ cm⁻² eV⁻¹ for (0001) and 1–5 × 10¹⁰ cm⁻² eV⁻¹ for (11$\bar{2}$0) and (1$\bar{1}$00). In the figure, the obtained D_it values obtained on (1$\bar{1}$00) and (11$\bar{2}$0) are close to the detection limit of the high-low method (1–2 × 10¹⁰ cm⁻² eV⁻¹), and the D_it difference between on these faces observed in Fig. 1 is not conclusive.

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The typical gate characteristics and field-effect mobility for the fabricated (0001) MOSFETs are shown in Fig. 2. The applied drain voltage was 0.1 V. The peak mobilities for the H₂-CVD-NO devices are approximately twice as high as those for the Ox-NO devices for N_A values of 1 × 10¹⁷ cm⁻³ and 1 × 10¹⁸ cm⁻³, although the threshold voltage of the H₂-CVD-NO devices is slightly lower.

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The typical gate characteristics and field-effect mobility of the fabricated (11$\bar{2}$0) and (1$\bar{1}$00) MOSFETs are shown in Figs. 3 and 4, respectively. As in the case of the (0001) MOSFETs, the channel mobility was improved by the H₂-CVD-NO process. The channel mobility reached 125–130 cm² V⁻¹ s⁻¹ for the (11$\bar{2}$0) MOSFETs and 80–112 cm² V⁻¹ s⁻¹ for the (1$\bar{1}$00) MOSFETs. Compared with the Ox-NO process, the H₂-CVD-NO process resulted in the channel-mobility enhancement by a factor of about 1.5 for the (11$\bar{2}$0) and (1$\bar{1}$00) MOSFETs with N_A values of 1 × 10¹⁷ cm⁻³ and 3 × 10¹⁷ cm⁻³, respectively. The difference in the channel mobility between the Ox-NO and H₂-CVD-NO MOSFETs greatly increases with increasing N_A of the p-body. The channel mobility improvement is 6-fold for (11$\bar{2}$0) MOSFETs (N_A = 1 × 10¹⁸ cm⁻³) and 100-fold for (1$\bar{1}$00) MOSFETs (N_A = 5 × 10¹⁸ cm⁻³).

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To investigate the main factor causing the mobility enhancement in the H₂-CVD-NO process, the gate characteristics of the (0001) and (11$\bar{2}$0) MOSFETs (N_A = 1 × 10¹⁸ cm⁻³) were measured at 160 K and the results are shown in Fig. 5. For a quantitative discussion, the threshold voltage (V_th) is defined as the gate voltage at which the drain current reaches 1 × 10⁻⁷ A. It is known that the gate characteristics of the SiC (0001) MOSFETs with NO treatment show a clear increase in the threshold voltage and a decrease in channel mobility at lower temperature due to pronounced electron trapping at the SiC/SiO₂ interface. ⁴¹⁾ The V_th shift for the Ox-NO (0001) MOSFET from room temperature to 160 K was 2.8 V, the result of which is similar to the previous report. ⁴¹⁾ In contrast, for the H₂-CVD-NO (0001) device, the V_th shift was as small as 0.6 V. The peak channel mobility for the Ox-NO device decreased from 12 to 8 cm² V⁻¹ s⁻¹ with lowering the temperature, whereas that for the H₂-CVD-NO device slightly increased from 25 to 26 cm² V⁻¹ s⁻¹. The fabricated (11$\bar{2}$0) MOSFETs showed a trend similar to that for the (0001) MOSFETs. The V_th shift was 0.9 V for the Ox-NO device and 0.2 V for the H₂-CVD-NO device. The channel mobility markedly increased, from 125 to 145 cm² V⁻¹ s⁻¹ as the device was cooled from room temperature to 160 K, for the H₂-CVD-NO device. These results indicate that D_it near E_c is substantially reduced in H₂-CVD-NO MOSFETs, which is consistent with the results shown in Fig. 1.

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The superior mobility in SiC(11$\bar{2}$0) and (1$\bar{1}$00) MOSFETs compared with that in SiC (0001) MOSFETs fabricated with the conventional process (Ox-NO: oxidation followed by annealing in NO) is well known and has been ascribed to the lower D_it near the conduction band edge. ⁴⁰⁾ A similar logic will be valid in the case of the proposed process (H₂-CVD-NO), as indicated in Figs. 1 and 5. The D_it values near the conduction band edge on SiC (11$\bar{2}$0) and (1$\bar{1}$00) with the proposed process are very low, being in the low 10¹⁰ cm⁻² eV⁻¹ range (Fig. 1) and the shift in the subthreshold characteristics by cooling the MOSFET is extremely small compared with SiC(0001) MOSFETs (Fig. 5). It is, however, difficult to explain the surprisingly large difference in the channel mobility between "H₂-CVD-NO" MOSFETs and "Ox-NO" MOSFETs fabricated on heavily-doped (11$\bar{2}$0) and (1$\bar{1}$00) simply by the observed D_it difference in the energy range from E_c − 0.2 eV to E_c − 0.5 eV (Fig. 1). The D_it difference may be more striking in the energy range closer to E_c. (The D_it for MOS structures formed by the conventional process may be much higher.) As another potential reason, the roughness scattering in (11$\bar{2}$0) and (1$\bar{1}$00) MOSFETs fabricated with the proposed process may be reduced, since the surface of SiC (11$\bar{2}$0) and(1$\bar{1}$00) epilayers is very flat in an atomistic scale, owing to the absence of the substrate off-angle. ⁴²⁾ With the proposed process, this very flat surface can be easily maintained, leading to high channel mobility in heavily-doped (11$\bar{2}$0) and (1$\bar{1}$00) MOSFETs. However, this discussion is still speculative and further investigations on the channel mobility by conducting MOS-Hall effect measurements are required.

In summary, we investigated the effects of a process that minimizes oxidation of SiC on the channel mobility of (0001), (11$\bar{2}$0), and (1$\bar{1}$00) MOSFETs with high N_A of the p-body (>1 × 10¹⁷ cm⁻³). The proposed process substantially improves the channel mobility. For the (0001) MOSFETs (N_a = 1 × 10¹⁸ cm⁻³), the channel mobility reached 25 cm² V⁻¹ s⁻¹, which is about twice that for Ox-NO MOSFETs. For the (11$\bar{2}$0) MOSFETs (N_a = 1 × 10¹⁸ cm⁻³) and (1$\bar{1}$00) MOSFETs (N_a = 5 × 10¹⁸ cm⁻³), the channel mobility reached 125 and 80 cm² V⁻¹ s⁻¹, respectively, which are about 6 and 100 times higher than that for the Ox-NO MOSFETs, respectively.

Acknowledgments