Recent progress of Ga₂O₃ power technology: large-area devices, packaging and applications

Power semiconductor devices are key to delivering high-efficiency energy conversion in power electronics applications such as electric vehicles, data centers, electric grids, renewable energy processing, and consumer electronics. ¹⁾ The market size of power semiconductor devices has reached $40 billion and is fast growing. ^1,2) The advances in power devices hinge on innovations in semiconductor materials and device architectures. From the material perspective, power devices based on silicon (Si), silicon carbide (SiC), and gallium nitride (GaN) have been commercialized. ^2,3) Several emerging materials with bandgaps larger than SiC and GaN, i.e. ultra-wide bandgap (UWBG) semiconductors, are being extensively researched, including gallium oxide (Ga₂O₃), aluminum nitride, aluminum gallium nitride, diamond, and boron nitride. ⁴⁾

Among these UWBG materials, Ga₂O₃ has shown particular promise as the Ga₂O₃ device technology has recently achieved several critical milestones for power applications. Power devices are used as solid-state switches to modulate considerable power flow in applications. Despite the wide range of specifications, industrial power devices are all packaged; they usually can conduct at least several amperes of current in the on-state, block at least tens or hundreds of volts in the off-state, and switch at a frequency of at least tens of kilohertz. During these operations, the junction temperature has to maintain below a safety limit (e.g. 150 °C–175 °C). In addition, power devices are required to possess good robustness against fault events (e.g. overvoltage, overcurrent, and surge energy ⁵⁾). These requirements define critical development milestones for any power device technology, i.e. the demonstration of (1) ampere-class devices with decent breakdown voltage (V_br), (2) packaging and thermal management, (3) switching operation in converter applications, and (4) reliability and robustness.

Ga₂O₃ is featured by a high critical electric-field (projected to be up to 8 MV cm⁻¹), controllable n-type doping with shallow dopants (10¹⁴ ∼ 10²⁰ cm⁻³), and the availability of large-diameter wafers by the melt growth. ^6–10) Low-cost beta-phase gallium oxide (β-Ga₂O₃) wafers have recently reached the 4-inch commercial milestone and are on track for the 6-inch wafer scale production by 2027. ¹¹⁾ This has paved the road for developing ampere-class devices. Since the first report of Ga₂O₃ transistors by Higashiwaki et al. in 2012–2013, ^12,13) Ga₂O₃ power devices have witnessed fast progress not only in the innovation of device architectures but also in the scaling of power levels. Recently, large-area Ga₂O₃ power devices with a current of up to 135 A ¹⁴⁾ or V_br of up to over 2000 V ¹⁵⁾ have been demonstrated. Beyond the die-level, packaging has been applied to large-area Ga₂O₃ devices and enabled a junction-to-case thermal resistance down to 0.5 °C W⁻¹. ¹⁶⁾ Excellent switching characteristics such as fast switching speed ^17,18) and minimal reverse recovery ¹⁹⁾ have been achieved in power converters. Impressive surge-current ²⁰⁾ and overvoltage ruggedness ¹⁵⁾ have been reported in large-area Ga₂O₃ devices.

To the best of our knowledge, Ga₂O₃ is the only UWBG material that has made the above critical milestones for power applications. This suggests that the commercialization and application of Ga₂O₃ power devices are within reach. This prospect is well supported by the development of a reference power device technology slightly ahead of Ga₂O₃, the vertical GaN technology. Its development shows a similar trajectory from small-area devices to large-area diodes ^21,22) and transistors ^23–28) fabricated on large-diameter wafers. After a further breakthrough in avalanche ^29–32) and short-circuit robustness, ^33–35) vertical GaN devices rapidly evolve into industrial manufacturing and start to be deployed in various power applications. ³⁶⁾

This article presents a timely review of the recent progress on large-area Ga₂O₃ power devices, with the scope covering their electrical performance, packaging and thermal management, converter operations, as well as robustness. This review also assists in identifying the gaps and immediate research needs. To date, despite several review papers on Ga₂O₃ devices, ^7,37) such a review on the application prospects is lacking for Ga₂O₃ power devices. The literature is vast, and space is limited. For a tight focus, only ampere-class Ga₂O₃ power devices with a conduction current over 1 A are discussed in this paper.

This article is organized as follows. Section 2 discusses the static performance of large-area Ga₂O₃ devices. Section 3 presents their packaging and thermal management. Sections 4 and 5 discuss their switching characteristics in power converters and circuit-level robustness, respectively. Section 6 identifies the immediate research needs and concludes the paper.

Currently, the reported ampere-class Ga₂O₃ rectifiers all deploy the vertical architecture with various junction structures including the Schottky barrier diodes (SBD), junction barrier Schottky (JBS) diodes, and p-n heterojunction diodes (HJD). As compared to the conventional p-n diode, the HJD relies on the p-n junction formed by n-type Ga₂O₃ and a distinct p-type material. The progress of these vertical Ga₂O₃ rectifiers is fast, and various edge termination designs have been reported to achieve high V_br. For transistors, the only ampere-class Ga₂O₃ power transistor reported in the literature is the lateral Ga₂O₃ MOSFET with a saturation current over 2.5 A and V_br over 400 V. ^17,18) Schematics of the Ga₂O₃ vertical SBD, JBS diode and HJD, as well as lateral MOSFET, are shown in Fig. 1.

Zoom In Zoom Out Reset image size

Figures 2(a)–2(c) benchmark the forward current versus V_br, the forward current versus the differential specific on-resistance (R_on,sp), and the R_{on ,sp} versus V_br of these ampere-class Ga₂O₃ power rectifiers and transistors. ^{14,15,17,19,20,38–49)} A more complete set of performance parameters of the representative devices are summarized in Table I. For power diodes, the forward current is extracted at a forward voltage (V_F) equal to 1.5 V higher than the turn-on voltage (V_on); R_on,sp is the differential resistance after the diode is fully turned on. It is observed that both V_br and R_on,sp show a decreasing trend as the forward current increases. This suggests that the non-uniformity in material properties and fabrication process, as well as a considerable defect density, are still the dominant performance limiting factors of V_br in large-area Ga₂O₃ devices. On the other hand, the smaller R_on,sp achieved at high current levels is a positive sign that implies the superior conduction capability in large-area devices.

Zoom In Zoom Out Reset image size

For the trade-off between the differential R_on,sp and V_br in Ga₂O₃ unipolar rectifiers, the Ga₂O₃ HJDs generally outperform the SBD counterparts, with some devices approaching the unipolar limit of SiC devices. This superior trade-off between the differential R_on,sp and V_br does not necessarily lead to a superior trade-off between the conduction and switching loss, as the turn-on voltage of the HJD devices (2–2.5 V) is usually 1–1.5 V larger than that of SBDs and JBS diodes. ^50,51) On the other hand, the SBDs and JBS didoes show the inferior V_br with nearly no large-area devices exceeding 600 V. These comparisons reflect the pros and cons of using p-n junction in power diodes. Developing more advanced devices is necessary to simultaneously deliver the forward characteristics of SBDs and the reverse blocking capability of HJDs.

It is also interesting to scrutinize the max junction E-field (E_max) in these devices at their V_br, which may suggest if the high critical E-field (E_C) in Ga₂O₃ has been exploited in large-area devices. Here E_max can be calculated from the 1-D Poisson equations for the non-punch-through (NPT) and punch-through (PT) designs, ^52,53) which represents the average junction field

$$\begin{eqnarray}&&\mathrm{NPT}\,{E}_{\max }=\sqrt{2q{N}_{{\rm{D}}}\left({V}_{\mathrm{bi}}+{V}_{\mathrm{br}}\right)/\left({\varepsilon }_{n}{\varepsilon }_{0}\right)}\end{eqnarray} \tag{ 1 }$$

$$\begin{eqnarray}&&\mathrm{PT}\,{E}_{\max }={V}_{\mathrm{br}}/{W}_{{\rm{D}}}+\left(q{N}_{{\rm{D}}}{W}_{{\rm{D}}}\right)/\left(2{\varepsilon }_{n}{\varepsilon }_{0}\right),\end{eqnarray} \tag{ 2 }$$

where W_D and N_D are the thickness and net donor concentration of the drift region, respectively, q and ε₀ are electronic charge and permittivity of vacuum, respectively, ε_n = 12.4 is the dielectric constant of β-Ga₂O₃ with the orientation of (001). ^6,54,55)

Figure 3(a) shows the V_br versus the calculated E_max for the reported large-area vertical Ga₂O₃ rectifiers. Most of the reported Ga₂O₃ SBDs and JBS diodes show an E_max below 3 MV cm⁻¹, which is below the E_C of GaN and SiC as well as the E_max of the state-of-the-art GaN/SiC devices. A few Ga₂O₃ HJDs show an E_max above 3.4 MV cm⁻¹, suggesting the promise of the Ga₂O₃/NiO heterojunction junction to exceed the blocking field limit of GaN/SiC devices. Figure 3(b) plots the V_br as a function of E_max ² for large-area Ga₂O₃ diodes reported so far. The data points are found to roughly align with a linear relation with a slope of (5.5 ± 0.5)×10⁹ V cm⁻², suggesting that most large-area devices (even with the PT design) have not significantly surpassed the NPT limit. Interestingly, this slope agrees with the calculated 2qN_D/ε_n ε₀ = 5.8 × 10⁹ V cm⁻² with an N_D ∼ 2 × 10¹⁶ cm⁻³, which is consistent with the usual epitaxy from the commercial vendor Novel Crystal Technology.

Zoom In Zoom Out Reset image size

Among the ampere-class Ga₂O₃ diodes, the highest V_br is 2040 V, which is obtained in the beveled-mesa NiO/Ga₂O₃ HJD reported by Zhou et al. ⁴⁰⁾ This device has a large on-state current of 20 A at ∼10.5 V (1.5 A at V_F = V_on + 1.5 V) and also exhibits the lowest R_on,sp of 2.26 mΩ·cm² with a record Baliga's figure-of-merit of 1.84 (2.87) GW·cm⁻² from DC (pulse) measurements. On the other hand, the highest current demonstrated in vertical Ga₂O₃ diodes exceeds 100 A. Ribhu et al. ¹⁴⁾ reported the 115 mm² vertical Ga₂O₃ SBD with the highest on-state current of 135 A at 6 V (44 A at V_F = V_on + 1.5 V) with a relatively low V_br of around 240 V.

The JBS diodes hold the potential to combine the SBD's advantage of low turn-on voltage and the HJD's advantage of the enhanced reverse blocking capability. To date, p-NiO is a favorable p-type material for the HJD. Wu et al. ³⁹⁾ have fabricated 9 mm² beveled field-plate (FP) JBS diodes, showing the largest V_br of 1060 V with the forward current of 5.1 A at V_F = V_on + 1.5 V. Wei et al. ⁴¹⁾ have reported a novel FP vertical Ga₂O₃ JBS diode with periodically distributed NiO/Ga₂O₃ heterojunction. The large-area 9 mm² (16 mm²) devices exhibit the largest forward current of 37 A (51 A) at 6 V and 10 A (15 A) at V_F = V_on + 1.5 V, the R_on,sp of 11 mΩ·cm² (15 mΩ·cm²), and V_br of 550 V (500 V). Even though, the reverse leakage current level in JBS diodes is still much higher than that of the HJDs, especially under low reverse bias. Thus, advanced designs are needed to further improve the electrical performance of JBS diodes.

For Ga₂O₃ power devices, an inevitable by-product of the superior electrical performance is the need to dissipate a higher density of heat due to the smaller device area. In addition, the concurrence of high current density and E-field could produce very high local heat flux, leading to non-uniform temperature distributions and local thermal runaway. What makes heat dissipation more challenging is the low thermal conductivity (k_T) of Ga₂O₃, i.e. 11–27 W m⁻¹·K⁻¹. ^56,57) To address these challenges, thermal management at both the device and package levels is essential. ⁵⁸⁾ At the device-level, substrate thinning and hetero-integration with high-k_T substrates, such as SiC and diamond, have been reported. ^59–62) Improved device characteristics up to 230 °C were demonstrated in Ga₂O₃ devices on SiC. ⁶⁰⁾ At the packaging level, junction- and double-side heat extraction with advanced cooling are essential for Ga₂O₃ devices. ^63,64) Regardless of these thermal management approaches, their effectiveness has to be evaluated in packaged, large-area power devices as characterized by indispensable datasheet parameters such as the junction-to-case thermal resistance (R_θJC).

Wang et al. ¹⁶⁾ first demonstrated the double-side packaging of 600 V/15 A Ga₂O₃ SBDs with nanosilver sintering as the die attach and then employed the packaged devices to evaluate the R_θJC under the junction- and bottom-side cooling [Fig. 4(a)]. The junction-side cooling allows for heat extraction directly from the device junction instead of through the Ga₂O₃ chip. From the thermal impedance curves obtained under two thermal interface materials, the R_θJC of the packaged device was extracted to be 1.4 K W⁻¹ and 0.5 K W⁻¹ for the bottom-and junction-side-cooling, respectively [Fig. 4(b)]. The R_θJC of the junction-side-cooled Ga₂O₃ SBD is smaller than similarly-rated, TO-packaged commercial SiC SBDs, manifesting the effectiveness of the junction-side cooling to overcome the low k_T of Ga₂O₃.

Zoom In Zoom Out Reset image size

Building on R_θJC, the authors also simulated the junction to ambient thermal resistance (R_θJA) of Ga₂O₃ SBDs under different external cooling strategies [Fig. 4(c)]. The results confirmed the need for junction-side cooling and suggested deployment of the external cooling with a heat transfer coefficient (HTC) over 10³ W m⁻²·K⁻¹, which can be achieved by the forced water. Double-side cooling can further reduce the R_θJA by 30%–40% at the price of the increased complexity, cost, and thermomechanical stress.

For device-level thermal management, despite many simulation studies, ⁶⁵⁾ experimental works on the large-area, packaged Ga₂O₃ devices have not been reported until very recently. Willhelmi et al. measured the R_θJC of large-area Ga₂O₃ SBDs with a substrate thickness thinned down to 200 μm. ⁶⁶⁾ These Ga₂O₃ SBDs were assembled in standard TO-247 packages by soldering and wire bonding and were cathode-side cooled. The thermal measurements and simulations show that the substrate thinning reduces the device R_θJC by more than half as compared to the standard substrate thickness (500 μm). Later simulation results by the same authors ⁶⁷⁾ revealed the flip-chip assembly for junction-side cooling could further reduce R_θJC to be comparable to commercial SiC devices. These results supported the experimental results from Wang and Xiao et al. ¹⁶⁾

By combining the junction-side-cooling package and substrate thinning, Gong et al. ⁴⁸⁾ demonstrated low R_θJC in a 335 V/20 A Ga₂O₃ SBD [Fig. 5(a)]. Under the junction-side-cooling, the flip-chip Ga₂O₃ SBD with the thinned substrate (70 μm) showed a R_θJC (1.48 K W⁻¹) lower than the device with the 550 μm Ga₂O₃ substrate (2.71 K W⁻¹) [Fig. 5(b)]. In addition to the steady-state R_θJC, the transient R_θJC of two devices was measured down to a μs-level time scale. This result suggests that, even with an effective junction-side heat extraction, the substrate thinning may still enhance thermal management by boosting heat extraction through the other side of the chip. The package-level and die-level thermal management need to be co-designed and co-optimized for Ga₂O₃ power devices. ⁶³⁾

Zoom In Zoom Out Reset image size

A challenge for the package-die thermal co-design is the lack of a modeling framework that interfaces the package- and device-level simulations. ⁶³⁾ Typical package-level finite element analysis (FEA) simulations assume a uniform power dissipation over the device junction neglecting the electrothermal effects (e.g. lattice heating in the sub-micron device structure). Conversely, the typical physics-based device simulations simplify the packaging into a normal boundary thermal resistance or HTC. Recently, Albano et al. ⁶⁸⁾ investigated a series of models to integrate the physics-based TCAD model with a package-level FEA model for the packaged Ga₂O₃ power devices, which demonstrated a superior trade-off between the simulation accuracy and computation load. This paves the road for package-die, electrothermal co-design, and co-optimization for Ga₂O₃ power devices.

Switching performance evaluation and converter demonstrations are key to identifying the market value of the Ga₂O₃ power device technology. Up to now, the relevant switching studies have been reported in both vertical Ga₂O₃ diodes and lateral Ga₂O₃ MOSFETs.

Vertical Ga₂O₃ diodes have good potential for various applications such as power factor correction (PFC) and active clamp flyback circuits. An essential test for power diodes is the reverse recovery measurements, as the reverse recovery time (t_rr) is a key limiting factor for the switching speed and loss. It should be mentioned that serious reverse recovery tests should be performed on large-area devices. Otherwise, the waveform could be dominated by the RC discharging time; the large resistance of small-area devices could blind the true reverse recovery process. To date, several research groups have made progress in the switching characterization of large-area vertical Ga₂O₃ diodes.

Yang et al. ³⁸⁾ reported that the t_rr of 1 mm² Ga₂O₃ SBD was ∼30 ns for switching from +2 V to a relatively small reverse voltage (−5 V). They later reported a 0.785 mm² Ga₂O₃ rectifier with V_br of 760 V. ⁶⁹⁾ The device showed a t_rr of 64 ns when switched from 1 A to −300 V with a minimal temperature dependence of t_rr up to 150 °C. This temperature independence is expected for unipolar conduction.

Gong et al. ¹⁹⁾ evaluated the dynamic switching performance of 9 mm² Ga₂O₃ HJD and SBD by utilizing the double-pulse-test (DPT) measurements [Fig. 6(a)]. When switched from a forward current of 1.6 A to a reverse bias of 100 V with a fast di/dt of 500 A μs⁻¹, the HJD and SBD exhibit similar switching performance with a t_rr of 11 ns and a reverse recovery charge (Q_rr) of 13 nC, which is comparable to commercial SiC SBD and far outperforms the Si fast-recovery diode (FRD) [Fig. 6(b)]. Even when the device is switched from a high forward current of ∼6.5 A, the HJD still shows almost zero reverse-recovery with a low t_rr of 12.0 ns [Fig. 6(c)]. This is attributed to the short minority carrier lifetime (4.5 ns) in n-Ga₂O₃ even at high-level injection. A similar nearly-zero reverse recovery was also reported in GaN native p-n junctions. ³⁵⁾ The small t_rr suggests that the Ga₂O₃ HJD could possess the benefits of the bipolar conduction, such as higher current capability and superior robustness, but do not suffer from the t_rr increase, i.e. the adverse consequence of the bipolar conduction in Si and SiC.

Zoom In Zoom Out Reset image size

Similarly, Zhou et al. ^15,40) reported a short t_rr of 16.4 ns and a reverse recovery charge of 34 nC in the 1 mm² beveled-mesa Ga₂O₃ HJD assembled in the TO-220 package. Furthermore, the overall correction capability of this device was evaluated in a 500 W PFC converter with long-term continuous operation [Fig. 6(d)]. This device showed good stability in continuous operation and enabled a high power-conversion efficiency of 98.5% and 97.4% at the switching frequency of 0.1 and 0.5 MHz, respectively, which outperformed Si FRDs [Fig. 6(e)]. Figure 6(f) demonstrates that the HJD exhibited a low case temperature of 62 °C at 0.3 MHz/500 W steady-state operation, approximately 11 °C lower than that of commercial Si FRD. Similar converter tests were also performed by Gong et al. ⁴⁸⁾ on the thin-substrate Ga₂O₃ SBD as described in Sect. 3 (see Fig. 5). A record high power efficiency of 98.9% at a switching frequency of 0.1 MHz was achieved by the device, which is higher than the device with the standard substrate thickness (and inferior thermal performance) [Fig. 5(c)].

Guo et al. demonstrated a DC-DC converter with the 2 A/467 V Ga₂O₃ SBDs assembled in a TO-220 package. ⁷⁰⁾ The t_rr of 8.8 ns with a Q_rr of 8.33 nC was achieved when the device was switched from 1 A to −100 V with a di/dt of 400 A μs⁻¹. The converter showed a high conversion efficiency of up to 95.62% at the input voltage of 200 V and an operating frequency of 100 kHz, which is comparable to that based on a similarly-rated commercial SiC SBD. Later, the same group reported a t_rr of 26.8 ns in a 5 A/1060 V Ga₂O₃ JBS diode. ⁷¹⁾ They further used this device to demonstrate a four-stage hybrid half-wave Cockcroft-Walton voltage multiplier. The hybrid circuit using the Ga₂O₃ JBS and SiC SBD showed a multiplication factor of 3.81, being comparable to the factor of all SiC SBD circuits. A high circuit efficiency of 86.07% was also demonstrated. The above results show the gigantic potential of vertical Ga₂O₃ power diodes for low switching loss, high conversion efficiency, and high-temperature power electronics applications.

Static characteristics and switching performance of lateral Ga₂O₃ MOSFET have also been investigated. ^17,18) J. Böcker et al. reported a large-area lateral Ga₂O₃ MOSFET with a R_on of 5 Ω and forward saturation current up to 2.5 A, as shown in Fig. 7(a). ¹⁸⁾ DPT setup shown in Fig. 7(b) is employed to evaluate the high-voltage switching dynamics. Figure 7(c) shows the hard-switching performance under different gate resistances. The voltage slope during turn-on increased from 35 to 50 V ns⁻¹ by reducing the gate resistance from 91 to 36 Ω at an input voltage of 300 V. The dynamics R_on under different DC voltages, load currents and load conditions, as well as the increased blocking time, were investigated to determine the impact and origin of the charge trapping effect [Figs. 7(d)–7(f)]. The R_on was found to increase obviously by applying a DC voltage for 1 s before the DPT. Only a small further increase was observed after 1 μs blocking and the following turn-on process [Fig. 7(d)]. The increased blocking time also resulted in R_on increase during the repetitive DPT [Fig. 7(e)]. Figure 7(f) showed that the R_on dynamic increase could be mitigated by increasing the turn-on driver voltage. These results suggested that the charge trapping during the blocking process in the gate region mainly resulted in the dynamics R_on increase.

Zoom In Zoom Out Reset image size

Afterward, the same group reported the hard-switching characteristics of large-area lateral MOSFET with a bus voltage increased up to 400 V. ¹⁷⁾ A higher turn-on speed of 78 V ns⁻¹ was demonstrated by utilizing the FP structure and improving the fabrication process. Similar dynamics R_on issues were found during the hard-switching operation. Hence, device innovation and process improvement should be focused on future research to mitigate the current dispersion and dynamics R_on increase under the dynamic switching.

Power devices are required to possess ruggedness against abnormal operations outside the safe operating area for a sufficient time before the protection circuitry intervenes. Such abnormal operations involve overvoltage and overcurrent far exceeding the rated values. The corresponding ruggedness for power diodes mainly includes (1) the avalanche or overvoltage ruggedness, ^5,72,73) which measures the device capability to withstand transient surge energy or overvoltage in the off-state, and (2) the surge current ruggedness, ³⁵⁾ which measures the device capability to withstand transient overcurrent in the on-state. For power transistors, in addition to the avalanche/overvoltage ruggedness, the short-circuit ruggedness measures the device capability to withstand the transient overcurrent not only in the on-state but also in the high-bias blocking state. ³⁴⁾ Meanwhile, gate ruggedness is also important for power transistors. ⁷⁴⁾

The ruggedness is a critical concern for Ga₂O₃ power devices due to the high junction E-field and low k_T of Ga₂O₃. As most ruggedness involves the electrothermal, transient, non-equilibrium process, it has to be characterized on large-area, packaged devices in circuit tests. The measurement results for on-wafer, small-area devices are usually less meaningful, as there are no straightforward scaling laws to use these results to project the ruggedness of practical devices. Very recently, thanks to the progress on Ga₂O₃ large-area devices, a few groups have experimentally investigated the surge current and overvoltage ruggedness of Ga₂O₃ diodes. Meanwhile, simulation investigations have been reported on the short-circuit ruggedness of Ga₂O₃ transistors.

Surge current is an essential ruggedness metric listed in any power diode's datasheet. A surge-current test circuit usually produces a 10 ms wide half-sinusoidal current waveform based on the JEDEC standard. Buttay et al. ⁷⁵⁾ first studied the surge current capability of Ga₂O₃ diodes using the device model and the SPICE network model; junction-side cooling was identified to be an effective pathway to boost the surge ruggedness. Following this theoretical study, Xiao and Wang et al. ²⁰⁾ reported the first experimental studies of the surge current ruggedness of Ga₂O₃ SBDs assembled in the bottom-side and double-side cooling package. As shown in Figs. 8(a)–8(c), a 1 mm thick Ag plate was deployed to confine the heat diffusion during the 10 ms transient and thus eliminate the impact of the outer solder, DBC, and wire bonds. The surge-current tests revealed a critical surge current of 37.5 A for the bottom-side-packaged Ga₂O₃ SBD and 68 A for the double-side-packaged Ga₂O₃ SBD [Fig. 8(d)].

Zoom In Zoom Out Reset image size

The higher surge current capability of the double-side-packaged Ga₂O₃ SBD is attributable to the effective heat removal through the junction and the resultant migration of the peak temperature location. This was illustrated by the results of the electrothermal, device-circuit, mixed-mode TCAD simulations. ²⁰⁾ At the high surge current transient, in a double-side-packaged Ga₂O₃ SBDs, the simulated heat flux contour reveals that most heat is removed through the junction [Fig. 9(a)], and the peak temperature location moves from the Schottky junction into the bulk Ga₂O₃ [Fig. 9(b)]. As the bulk semiconductor is usually more thermally robust as compared to the heterogenous interface, a higher peak temperature (and higher surge current capability) can be accommodated.

Zoom In Zoom Out Reset image size

The other interesting finding in Ref. 20 is that the packaged Ga₂O₃ SBDs show a superior surge current capability as compared to the similarly-rated commercial SiC SBDs. In addition to the effective junction-side heat removal, a key enabling mechanism is the smaller temperature coefficient of the differential on-resistance (α) in Ga₂O₃ SBDs (α ∼ 0.73) as compared to that in SiC SBDs (α > 2.5), which suppress the positive feedback of the increase in on-resistance and junction temperature. The critical role of α on the surge current capability was also confirmed in GaN, where the negative α of GaN p-n diodes enables a high surge current. ³⁵⁾ The physical mechanism of the low α of Ga₂O₃ SBDs could be related to the deep donors but requires further investigation. ²⁰⁾ The authors in Ref. 20 also used the calibrated simulation models to explore the approaches to further improve the surge current capability of Ga₂O₃ SBDs [Fig. 9(c)]. The Ga₂O₃ integration with the high-k_T substrate, in the combination with the double-side-cooling package, is predicted to be the most effective way.

Gong et al. ¹⁹⁾ recently reported the surge current ruggedness of Ga₂O₃ HJDs and SBDs assembled in the TO-220 package. The Ga₂O₃/NiO HJDs exhibit a higher surge current capability than SBD, possibly due to the negative α observed in HJDs. These results suggest the Ga₂O₃/NiO p-n junction possesses the functionality to boost the surge current ruggedness similar to the homogenous p-n junction in GaN and SiC. Later, the authors ⁴⁸⁾ reported the surge current capability of the junction-side-packaged Ga₂O₃ SBDs with the thinned substrate [see Fig. 5(a)]. A critical surge current (59 A) much higher than the TO-packaged Ga₂O₃ SBD (38 A) ¹⁹⁾ was demonstrated, further manifesting the importance of packaging on the surge current ruggedness of Ga₂O₃ devices.

Avalanche is a desirable capability for power devices to withstand overvoltage stresses, as it relies on impact ionization and multiplication to allow devices to pass a high current at the non-destructive V_br. ⁵⁾ However, not all power devices come with the avalanche capability: it is absent in commercial GaN high-electron mobility transistors ⁵⁾ but equipped in most Si and SiC devices as well as some other GaN bipolar devices. ^21,29–32) As the avalanche in Si, SiC and GaN devices all rely on native p-n junctions, it could be very difficult to realize the avalanche-capable Ga₂O₃ devices due to the lack of the p-type Ga₂O₃. Hence, for the overvoltage ruggedness of Ga₂O₃ devices, a very good reference is the GaN HEMT. Recent studies of the GaN HEMT overvoltage ruggedness converge on several key conclusions: (1) the device relies on the overvoltage margin and output capacitance to withstand the overvoltage stress without the capability to dissipate the surge energy, ^5,73,76) (2) the overvoltage ruggedness can be characterized by the unclamped inductive switching (UIS) circuit, ⁵⁾ and (3) the V_br in short switching transient (i.e. dynamic V_br) could be very different from (usually larger) that measured on the curve tracer (i.e. static V_br). ^76–78)

Recently, Zhou et al. ¹⁵⁾ reported the overvoltage ruggedness of large-area Ga₂O₃/NiO HJDs using single-pulse and repetitive UIS circuits. The Ga₂O₃ HJD exhibits a static V_br of 1.95 kV and a dynamic V_br of 2.23 kV, suggesting an increased overvoltage margin in dynamic switching. In addition, the Ga₂O₃ HJD shows no parametric shifts after 1 million cycles if UIS stresses with a peak overvoltage of 1.2 kV. This result demonstrates the good overvoltage ruggedness with a withstanding physics similar to GaN HEMTs in Ga₂O₃ power devices.

Very recently, Lu et al. ⁷⁹⁾ reported a numerical simulation on the short-circuit ruggedness of a kV-class vertical Ga₂O₃ power FinFET at the blocking voltage of 800 V. The FinFET is an emerging power transistor first developed in GaN ^1,23,24) and later demonstrated in Ga₂O₃ ^80,81) with state-of-the-art performance in Ga₂O₃ power transistors. The forward conduction and breakdown mechanism both hinge on the fin channel design, ^82–84) and switching performance also depends on the inter-fin designs. ⁸⁵⁾ The short-circuit analysis of vertical Ga₂O₃ FinFETs suggests the strong impact of the inter-fin architectures on the device short-circuit withstanding time (SCWT). ⁷⁹⁾ The full-gate structure has the worst SCWT due to electrostatics; the split-gate structure can increase the SCWT at the price of V_br degradation. The simulation predicts that the split-gate design with the inter-fin source coverage could provide the best trade-off between the short-circuit ruggedness and V_br in vertical Ga₂O₃ power FinFETs.

This paper provides a timely review of the state-of-the-art of the large-area Ga₂O₃ power devices. The key takeaways include:

• 1)  
  Ampere-class Ga₂O₃ power diodes (SBDs, JBS diodes, and HJDs) and MOSFETs have been widely reported with V_br up to >2 kV and 400 V for diodes and MOSFETs, respectively. The performance of most devices is superior to the Si counterparts but still inferior to the SiC and GaN ones. The junction field of several large-area Ga₂O₃ HJDs has surpassed the E_C of SiC or GaN, fulfilling the superior electrical properties of Ga₂O₃.
• 2)  
  Junction-side packaging and cooling are essential for the thermal management of Ga₂O₃ power devices, and they can overcome the low-k_T limitations of the Ga₂O₃ material to deliver a low device R_θJC. Die-level thermal management such as heterogenous integration and substrate thinning are desirable to be further combined with the junction-side or double-side packaging.
• 3)  
  Ga₂O₃ SBDs and HJDs have shown minimal reverse recovery and have been applied in a variety of power converters to achieve high power-conversion efficiency. Ga₂O₃ MOSFETs have exhibited fast switching speed in inductive power switching.
• 4)  
  The surge current capability and overvoltage ruggedness of Ga₂O₃ SBDs and HJDs have been demonstrated to be comparable or even superior to some SiC and GaN counterparts. Device architectures (e.g. channel design), packaging and cooling, and material properties (e.g. deep dopants) all impact the ruggedness of Ga₂O₃ devices in an interdependent way.
• 5)  
  The NiO/Ga₂O₃ heterogenous p-n junction exhibits promising characteristics for power devices, including good current and voltage scalability, minimal reverse recovery, and excellent surge-current and overvoltage ruggedness. It could become an important building block for many advanced Ga₂O₃ diodes and transistors.

Despite the exciting progress, the research of large-area Ga₂O₃ power devices is still in the early stage. We envision the following immediate research gaps that need to be addressed for advancing Ga₂O₃ into industrial power electronics applications.

• 1)  
  P-n junctions form the blocking block for nearly all power devices with avalanche capability and overcurrent robustness. Despite the numerous advantages offered by the UWBG material, the absence of p-type Ga₂O₃ conductivity may make it difficult to fully utilize these advantages. Although Ga₂O₃ p-n heterojunction has emerged as an alternative bipolar design to deliver superior performance than the SBD counterparts, the fundamental challenge is the mismatch of bandgap and critical electrical field strength that may hinder the electric-field handling capability. Another important consideration is the interface engineering in such heterojunctions, where interfacial traps and impurities would degrade the electrical performance and reliability robustness.
• 2)  
  Defect reduction is key to boosting the performance of large-area devices. Deep-level defects/traps within Ga₂O₃ bulk and interfacial regions generally act as carrier generation-recombination (G-R) centers, which are the dominant sources to degrade device performance and reliability. Defects may be unintentionally-introduced impurities or intrinsic crystalline defects (dislocations or stacking faults) that are energetically formed and inhomogeneously distributed during material growth. Therefore, the fundamental challenge in the material aspect, reducing defects and dislocations, is crucial to enhance carrier transport and improve device performance.
• 3)  
  Junction capacitance and switching charges are critical for power devices; to enable advantages in practical power devices, the low R_on,sp has to be converted to the realization of smaller capacitances and charges. ¹⁾ However, the relevant studies are quite scarce in Ga₂O₃. Very recent work reported the capacitance, charges, and switching figure-of-merits (FOMs) of Ga₂O₃ SBDs for the first time, ⁸⁶⁾ while the switching FOM is still inferior to the commercial SiC SBDs. A rigorous study of the impact of the low carrier mobility in Ga₂O₃ on the switching FOMs of Ga₂O₃ devices for different applications (e.g. soft-switching, hard-switching) is highly desirable to understand Ga₂O₃'s true application space in power electronics.
• 4)  
  Device innovations are highly desirable to further improve the junction E-field in large-area Ga₂O₃ devices and ensure it would not compromise in devices with the upscaled current and voltage ratings. While the average junction E-field calculated in many papers of small-area Ga₂O₃ devices could be a good indicator of the material limit, it does not mean any true advantage in power device performance, particularly for devices with low V_br. Currently, the junction E-field in ampere-class, high-voltage Ga₂O₃ devices is still much lower than that reported in small-area Ga₂O₃ devices with low V_br.
• 5)  
  The fundamentals of the Ga₂O₃ heterogeneous p-n junction in power switching, particularly the carrier dynamics under the non-equilibrium, transient switching conditions, are important for understanding the device switching and ruggedness characteristics. In addition, the feasibility of avalanche in heterogeneous p-n junction remains an open question. The avalanche capability, if achievable in heterogeneous junctions, could be a strong boost to not only the ruggedness but also the performance of Ga₂O₃ power devices (as the V_br margin required for a specific voltage rating could be much smaller for avalanche-capable power devices).

We envision that Ga₂O₃ power devices hold tremendous potential for penetration into power electronics applications if these gaps can be addressed in the next few years.

We appreciate the in-person discussions with Ga₂O₃ researchers in IWGO2022. The work at Virginia Tech is in part supported by National Science Foundation under Grants ECCS-2100504 and ECCS-2230412 and in part by the Center for Power Electronics Systems High Density Integration Industry Consortium.