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Enhancement of Two-Bit Performance of Dual-Pi-Gate Charge Trapping Layer Flash Memory

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Published 22 November 2012 ©2012 The Japan Society of Applied Physics
, , Citation Min-Feng Hung et al 2012 Appl. Phys. Express 5 121801 DOI 10.1143/APEX.5.121801

1882-0786/5/12/121801

Abstract

This work demonstrates a dual-pi-gate TaN–Al2O3–Si3N4–SiO2–silicon (TANOS) flash memory with nanowires (NWs) channel. Simulation under modulated Fowler–Nordheim (MFN) tunneling indicates that the source-side tunneling oxide of the dual-gate (DG) TANOS NVM has an electric field larger than 6 MV/cm. A novel 2-bit operation of DG TANOS NVM can thus be performed by MFN programming and band-to-band tunneling-induced hot–hole injection (BTBTHHI) erasing. Additionally, the DG TANOS memory shows better program/erase characteristics and clearer distinguishability than a single-gate (SG) device under 2-bit operation. In reliability results, the DG TANOS memory shows better retention and endurance than the SG device.

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10.1143/APEX.5.121801