Vertical Surrounding Gate Transistors Using Single InAs Nanowires Grown on Si Substrates

We report on the fabrication and characterization of vertical InAs nanowire channel field effect transistors (FETs) with high-k/metal gate-all-around structures. Single InAs nanowires were grown on Si substrates by the selective-area metalorganic vapor phase epitaxy method. The resultant devices exhibited n-channel FET characteristics with a threshold voltage of around -0.1 V. The best device exhibited maximum drain current (I DSmax/w G), maximum transconductance (g mmax/w G), on–off ratio (I ON/OFF), subthreshold slope (SS) of 83 µA/µm, 83 µS/µm, 104, and 320 mV/decade, respectively, for a nanowire diameter of 100 nm.

We report on the fabrication and characterization of vertical InAs nanowire channel field effect transistors (FETs) with high-k /metal gate-allaround structures. Single InAs nanowires were grown on Si substrates by the selective-area metalorganic vapor phase epitaxy method. The resultant devices exhibited n-channel FET characteristics with a threshold voltage of around À0:1 V. The best device exhibited maximum drain current (I DS,max =w G ), maximum transconductance (g m,max =w G ), on-off ratio (I ON=OFF ), subthreshold slope (SS) of 83 A/m, 83 S/m, 10 4 , and 320 mV/decade, respectively, for a nanowire diameter of 100 nm. # 2010 The Japan Society of Applied Physics DOI: 10.1143/APEX. 3.025003 E pitaxially grown semiconductor nanowires (NWs) are very promising as the building blocks of future device applications, such as field effect transistors (FETs), laser diodes, photovoltaic devices, and so on. [1][2][3][4][5] For instance, several groups have reported on lateral NW FETs that use horizontally scattered NWs as a channel, [6][7][8][9][10][11] and some of them remark on the superior properties of these FETs to conventional FETs. 10,11) In contrast, there are very few reports on vertical geometry channel NW FETs because of the complicated three-dimensional device processes. [12][13][14][15][16] However, epitaxially grown free-standing NWs are geometrically suitable for achieving a surrounding gate structure in vertical FETs, which effectively suppresses short channel effects through excellent gate controllability.
To date, we have succeeded in controlling the position and direction of the growth of a III-V NW array on a Si substrate by using catalyst-free crystal growth techniques. These arrays have potential for a wide variety of applications, such as monolithic integration of high performance III-V logic devices and optoelectronic devices on a Si platform. 17,18) For FETs, InAs NWs are particularly promising since their small effective electron mass leads to high electron mobility and their property of strong Fermi level pinning on conduction bands leads to good Ohmic contact with various kinds of metals. From these viewpoints, InAs NW vertical surrounding gate transistors (NW-VSGTs) on Si substrates have the potential to surpass conventional complementary metaloxide-semiconductor devices. In this letter, we report on the fabrication and characterization of NW-VSGTs using InAs NWs grown on Si substrates. InAs NWs were grown by selective-area metalorganic vapor phase epitaxy (SA-MOVPE). [17][18][19][20][21] First, a 20-nmthick SiO 2 film was formed on an n-type Si(111) substrate by thermal oxidation. Subsequently, 100 Â 100 m 2 square masks with only one circular opening at the center were defined by electron beam lithography and wet chemical etching. Next, single InAs NWs were selectively grown on the partially masked substrate in a low-pressure horizontal-MOVPE system, supplying trimethylindium (TMIn) and arsine (AsH 3 ) as source materials. The growth conditions were as follows: partial pressure of TMIn, [TMIn], was 4:87 Â 10 À7 atm; partial pressure of AsH 3 , [AsH 3 ], was 1:25 Â 10 À4 atm; growth temperature was 550 C; and growth time was 20 min. To achieve vertical III-V NWs on the Si substrates, special care was taken to prepare As-terminated (111) surfaces on the Si substrates prior to the growth. Details of the growth processes are reported elsewhere. 17) A scanning electron microscope (SEM) image of a typical InAs NW array grown on a Si substrate is shown in Fig. 1. The length of each NW was 2.5 m, and their diameters (d NW ) were 100 nm, which is almost the same as the mask opening size.
We fabricated InAs NW-VSGTs using single InAs NWs grown on Si substrates with high-k/metal surrounding gates. Process of device fabrication was as follows. First, after the growth [ Fig. 2(a)], the whole surface and NWs were covered with 20-nm-thick Hf 0:8 Al 0:2 O x formed by atomic layer deposition for a high-k gate dielectric [ Fig. 2(b)]. Second, tungsten gate metal and its contacting pads were formed by plasma sputtering and photolithography [ Fig. 2(c)]. Low-k benzocyclobutene (BCB) resin (Dow Chemical CYCLOTENE) was spin-coated once and then etched back to the desired thickness ($300 nm) by reactive ion etching (RIE) [ Fig. 2(d)], followed by dry and wet etching of the metal and high-k remaining on the top portions of the NWs. At this step, the BCB layer worked as a protection mask for etching, whose thickness defined the gate length, L G [ Fig. 2(e)]. Next, the device was spin-coated again with BCB to obtain an electrical separation layer between the gate and top drain electrode and then etched back by RIE to a thickness such that only the top portions of the NWs were exposed [ Fig. 2(f)]. Subsequently, the drain and source metals (Ti/Al) were evaporated on the top of NWs and bottom side of the substrate, respectively [ Fig. 2(g)]. Finally, the gate contacting pads were exposed by RIE [ Fig. 2(h)]. A schematic cross-sectional structure and cross-sectional SEM image of NW-VSGT are shown in Figs. 3(a) and 3(b), and one can see that the FET structure was formed as expected.
DC characteristics for a single InAs NW-VSGT were measured using a parameter analyzer (Agilent 4156). The measured device showed the characteristics of an n-type InAs NW-FET with unintentionally doped NW channel, similar to many other reported InAs NW-FETs. 12,13) The output and transfer characteristics for the device showing the best performances at room temperature are shown in Figs. 4(a) and 4(b), respectively. Note that the substrate is grounded and used as a common source. The measured FET properties were as follows: maximum drain current I ds,max ¼ 25 A (at V DS ¼ 1 V), peak transconductance g m,max ¼ 25 S (at V DS ¼ 1 V), subthreshold slope SS ¼ 320 mV/decade (at V DS ¼ 1 V), on-off ratio I ON=OFF ¼ 10 4 (with V G window of 2 V), and threshold voltage V TH ¼ À0:1 V. I ds,max and g m,max were normalized with the gate circumference, w g ¼ d NW , and given to be 83 A/m and 83 S/m, respectively. On the basis of the measured transconductance g m , the field effect mobility FE was calculated using the formula FE ¼ g m L G =C OX w G ðV G À V TH Þ and we obtained a FE of 22 cm 2 V À1 s À1 , where C OX , the gate oxide capacitance of a cylindrical shape, was given by C OX ¼ 2" 0 " high-k =d NW lnð1 þ 2t ox =d NW Þ. " high-k is relative permittivity, and t ox is the thickness of the high-k dielectric. This value falls far behind that of bulk InAs electron mobility, which is 33,000 cm 2 V À1 s À1 at room temperature. We think there are two main reasons for the deterioration of FE . One is interface states at InAs/HfAlO. The other is in a high source resistance, which originates from the band offset at the interface of Si/InAs NWs. In fact, for the latter, we noticed that the current-voltage characteristics between source and drain were asymmetric with respect to V DS ¼ 0 V, particularly for large V G , where the channel resistance is smaller. To minimize this effect, it is necessary to optimize the doping density of the Si substrate and InAs NW by band engineering, or it might be necessary to form a source electrode directly on the bottom of the NWs.  To further evaluate the performance of the present NW-VSGT, we simulated the gate voltage-drain current characteristics for V DS ¼ 0:5 V based on the drift-diffusion equation; the results are plotted in Fig. 2. In the simulation, the same structural parameter (d NW , L G , d high-k ), a donor doping density of 10 17 cm À3 , electron mobility of 10,000 cm 2 V À1 s À1 , and the radial symmetry of the NW were assumed, and velocity saturation effect was taken into account. Here we would like to focus on two points. First, the SS was about 65 mV/decade, while it was 320 mV/decade in the experiment. We believe this discrepancy is mainly attributable to the high interface state density between InAs and the high-k dielectric (HfAlO), which has not been investigated in detail so far. Possible ways to minimize interface state density is to remove native oxides completely before high-k deposition and/or to make a coreshell structure at the in situ MOVPE growth step for the passivation or the interface-control layer. Second, drain current and transconductance of simulation values were much superior to experimental ones. This is due to too large mobility used in the simulation, but it is noted that the current does not scale with the value of mobility in the simulation. This suggests that the importance of velocity saturation in short channel device. This makes the estimation of actual value of mobility difficult. In addition, the field effect mobility was deduced neglecting the series resistance including access resistance by hetero potential barrier at Si/InAs interface, as mentioned in the previous paragraph. Existence of interface states further results in the reduction of transconductance and lowers the estimated value of field effect mobility. Therefore, we think obtained value of FE is the lower bound of the mobility in our structure. For the core-shell NW approach, using an ndoped wider gap material as a shell structure also functions as an electron supplying layer, so we can achieve a modulation-doped InAs core channel, resulting in a high electron mobility transistor (HEMT). In simulation, we obtained intrinsic cut-off frequency, f T of over 150 GHz, which was comparable to planer InP HEMT with gate length of 100 nm. Moreover, optimization of the design of the whole transistor structure, including scaling of the gate length, the diameter and doping density of the NWs, is also necessary to further improve the performance of NW-VSGTs.
In summary, we successfully fabricated and demonstrated InAs NW-VSGTs on Si substrates by using the SA-MOVPE growth method. The devices were n-type single NW channel FETs having nonlinear characteristics due to the Si/InAs NW hetero band offset. The FET properties were comparable to other reported InAs NW-FETs, but there is still much scope for improvement.