Near-zero hysteresis and near-ideal subthreshold swing in h-BN encapsulated single-layer MoS₂ field-effect transistors

The monolayer MoS₂-based FET consists of a graphene layer as a back-gate electrode, the bottom thick h-BN (h-BN_b) as a gate insulator, a monolayer MoS₂ as a channel and the top thick h-BN (h-BN_t) as a passivation layer (see figure 1(a) for the illustration of the FET). The optical image of the device is displayed in figure 1(b) and the fabrication process can be found in the experiment section and figure S1 (supporting information (stacks.iop.org/TDM/5/031001/mmedia)). The peaks corresponding to graphene, h-BN, and MoS₂ were observed in the Raman spectrum of the graphene/h-BN_b/MoS₂/h-BN_t stack (see figure S2). The monolayer nature of MoS₂ was confirmed from the wavenumber difference of 18 cm⁻¹ between A_1g (~403 cm⁻¹) and $E_{2{\rm g}}^{1}$ (~385 cm⁻¹) peaks (see inset in figure S2) [32]. Atomic force microscopy (AFM) measurements were conducted after the sample annealed at 300 °C for 5 h in an H₂/Ar atmosphere (H₂/Ar ratio of 50/200 sccm) to ensure a clean MoS₂ channel. We observed the formation of a few air bubbles near the edge of MoS₂ flake. However, the interface of MoS₂ channel remained clear of any bubbles (see inset in figure 1(c)). Figure 1(c) shows the I–V characteristics of our monolayer MoS₂ FET for an h-BN gate dielectric thickness of ~8 nm (leakage current is shown in figure S3). Along with an on/off ratio of 10⁹, the monolayer MoS₂ FET was nearly free from hysteresis with only 0.15% (ΔV/V_g) over the entire range of current (ranging from 10⁻¹⁴ to 10⁻⁵ A) (figure 1(d)), which is the smallest value reported in 2D FETs so far. In addition, despite h-BN low dielectric constant of ~4, the FET exhibited a remarkably steep subthreshold swing of 63 mV/dec, very close to the thermal limit (60 mV/dec) and an average subthreshold swing (SS) of 69 mV/dec over four orders of current (figure 1(d)). The device was also measured under ambient condition, low vacuum (10⁻² Torr) and high vacuum (10⁻⁶ Torr), there is no significant difference in I–V characteristic between measurements (figure S4).

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The high performance of our FET is attributed to the ultra-clean interfaces of graphene/h-BN/MoS₂/h-BN heterostructure at the channel area which is not influenced by trapped adsorbates. To see the effect of bubbles on the properties of MoS₂, we conducted Raman and photoluminescence (PL) measurement at the flat area and bubbled area before annealing (inset in figure 1(e)). We found the redshifts at $E_{2{\rm g}}^{1}$ peak in Raman spectrum in the bubbled area (figure 1(e)), although the peak shift in A_1g is negligible. The PL intensity is also reduced (figure 1(f)) and the A exciton peak shows the redshift (inset in figure 1(f)), possibly from the domination of negative trions. These indicate that the n-doping is applied in the bubbled area [33, 34]. Doped molecules trapped in the bubble (H₂O, O_2...) are origins of the trap states which increase hysteresis or subthreshold swing. The removal of bubbles is, therefore, necessary to preserve intrinsic properties of MoS₂ to enhance the performance of the device.

To study the surface roughness of heterostructure which is an important factor in the charge transport in the channel, atomic force microscope (AFM) measurements were conducted. Before annealing samples, we observed rich air trap bubbles formed during the transfer process with the sizes less than 1.5 mm in diameter at the heterointerfaces (white dots in figure 2(a)). These bubbles are distributed homogeneously over the entire channel with the thickness variation from 0 to 20 nm. These bubbles induce a large root mean square surface roughness (R_rms) of 4.2 nm (figure 2(b)) and a large profile roughness (R_a) of 3.0 nm (figure 2(c)). While the rough surface will cause the charge scattering and therefore reduce the mobility, adsorbates in the bubbles result in large hysteresis and subthreshold swing. In order to remove the trapped adsorbates to improve quality of the heterointerfaces, samples were then annealed with the same condition as mentioned above. During the thermal annealing process, the bubble residues are decomposed and desorbed from the surfaces, at the same time, because of high kinetic energy under high temperature, the tiny bubbles at the heterointerfaces are able to migrate and merge with adjacent bubbles to form bigger bubbles via Ostwald ripening process, which are eventually out-diffused into the edge of the channel, leaving a large and flat area in the channel (inset in figures 1(c) and 2(d)). As shown in figures 2(d)–(f), the surface roughness is significantly reduced after annealing, the R_rms and R_a are reduced to 0.6 and 0.4 respectively, 7 times less than those of samples before annealing. We also note that the samples can be damaged in some cases because of extremely vigorous movement of the bubbles.

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To investigate the effect of annealing on the device performance, we measured I–V characteristics of the FETs with no passivation, passivation with the top h-BN, as well as passivation and annealing (figures 3(a)–(c)). A large hysteresis is observed when there is no passivation (figure 3(a)). The hysteresis is then significantly reduced after h-BN passivation but not completely removed due to the remaining air or adsorbates within the bubbles (figure 3(b)). After annealing, the bubbles are removed and consequently, almost no hysteresis is observed, as shown in figure 3(c). Figure 3(d) illustrates the hysteresis in the device as a function of current extracted from the I–V curves. The hysteresis is predominantly suppressed over the entire range of current after annealing due to the formation of a clean interface as discussed earlier. We tested 5 more devices to confirm the consistency. All the samples showed reduction of bubble portion in MoS₂ channel after annealing and improvement of electrical characteristics, four samples showed the subthreshold swing less than 71 mV/dec and hysteresis of  <0.2% (figure S5) and one sample showed the subthreshold swing of 105 mV/dec and hysteresis of 2% (figure S6) with partially remained bubbles on the channel area. The shifting of the threshold voltage toward the positive gate bias (figures 3(a)–(c)) reveals the reduction of n-doping in the MoS₂ channel, consistent with the PL and Raman data in figures 1(e) and (f). The subthreshold swing is also improved significantly after passivation and being close to the thermal limit (60 mV/dec) after annealing (figure 3(e)). This originates from the reduction in the air bubbles density at the interface as displayed in figures 2(d)–(f). The improvements in the interface also result in the increase by 4 times in the charge carrier mobility, from 10 to 40 cm² V⁻¹ s⁻¹ at V_g−V_th of 6 V (figure 3(f)). The enhancement of mobility is attributed to reducing the trap state at the interfaces as well as improving the contact resistance after encapsulation and annealing. The output characteristic and mobility calculation are provided in supporting information (figures S7, S8 and Note 1).

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The interfacial trap states are the origin of the hysteresis in 2D FETs, thus, removing these trap states is key to suppress the hysteresis. The interfacial trap density (N_it) and interfacial trap density distribution per energy (D_it) can be calculated from the hysteresis and subthreshold swing, respectively (see Note 2, supporting information for details). Due to the clean interface, there was a significant reduction in the N_it (D_it) for nearly 40 times after encapsulation and annealing (figure 4(a)).

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To further investigate quantitatively the interfacial traps, we conducted a low-frequency noise measurement [35], with the frequency ranging from 1 Hz to 1000 Hz (figure 4(b)). The noise spectral density S_I shows a general 1/f trend from the subthreshold regime to high accumulation regime, thereby revealing that the trap states are uniformly distributed in the momentum and real space. The noise source may arise from carrier-number fluctuation (CNF) or mobility fluctuation in the channel. The data from low-frequency noise analysis were well described by the carrier-number fluctuation and correlated mobility fluctuation (CNF  +  CMF) model instead of the CNF model only. By fitting the measured noise data at 10 Hz with (CNF  +  CMF) model [35, 36], we confirm that the trap states are induced at the h-BN/MoS₂ interface (figure 4(c) and Note 3, supporting information). We have also extracted the charge trap density using the CNF  +  CMF model. Our device exhibits a charge trap density of 5.2  ×  10⁹ cm⁻² eV⁻¹, thousand times less than that of previous reports using 2D transition metal dichalcogenides (TMD) on other substrates [37–40]. We attribute the low charge trap density to arise from the clean vdW interfaces without the presence of the trapped molecules and the lacking of dangling bonds between h-BN and MoS₂ layers.

With the presence of large trap states at the interfaces, the hysteresis strongly depends on the external factors such as sweeping direction, sweeping rate, and sweeping range [17]. We measured the I–V with different sweeping directions (figure 4(d)), sweeping rates (figure 4(e)), and sweeping ranges (figure 4(f)) of the gate bias. All threshold voltages are almost identical (figures 4(d)–(f)) and the hysteresis is less influenced by sweeping rate and sweeping range of the gate bias (insets in figures 4(e) and (f)). These imply that the I–V characteristic is nearly independent of those external factors in our samples by the low trap density at the interfaces.

Although a thin h-BN film appears to be desirable for gate controllability and achieving a low subthreshold swing, gate leakage current can arise from the direct tunneling of charge carriers through the thin h-BN barrier. To examine the dependence of electrical characteristics of the FET on the h-BN thickness, we fabricated MoS₂ FETs with various h-BN thicknesses ranging between 2 to 20 nm and measured the break-down voltage V_bd at leakage current of 1 nA (Note 4, figure S9, supporting information). The breakdown electric field increases from 0.0001 V nm⁻¹ to ~0.6 V nm⁻¹ and saturates at an h-BN thickness of ~8 nm (figure 5(a)). This transition occurs because of a transition from direct to Fowler–Nordheim tunneling [41]. Figure 5(b) shows the dependence of the h-BN thickness on the on-current, off-current and on/off current ratio at a source-drain voltage of 0.5 V and a gate bias sweeping from  −5 to 5 V. The on/off ratio increases from 10² to 10⁹ when the h-BN thickness is ~8 nm, mostly due to a drop off in the off-current. The off-current is generated by the tunneling leakage current, which is reduced to less than 10⁻¹⁴ A (limited by the range of our source measurement unit) for an h-BN thickness  >8 nm, while the on-current slightly decreases due to the reduction in the gate electric field. Based on these measurements, we conclude that the h-BN thickness is optimal at ~8 nm. A low threshold voltage is essential for the low power consumption of the device. The threshold voltage V_th can be scaled down with a small operating voltage of less than 1 V while still maintaining a high on/off ratio of 10⁸ at the h-BN thickness of ~8 nm (figures S10 and 5(c)). Since the dielectric constant of h-BN is quite small (ε  ≈  4) compared to other high-k materials such as Al₂O₃ (ε  ≈  9), HfO₂ (ε  ≈  18) or ZrO₂ (ε  ≈  25), the small subthreshold swing as well as negligible hysteresis presented in our device is attributed to the clean interfaces without dangling bonds of 2D materials rather than the dielectric constant value. We compare our device performance (in terms of subthreshold swing and on/off ratio) with previous literature reports on MoS₂ devices [4, 8, 9, 19, 42–46]. Our device exhibits the highest on/off ratio, as well as the smallest subthreshold swing among the conventional MoS₂ FETs fabricated using different dielectric gates (figure 5(d)).

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The graphene/h-BN/MoS₂/h-BN stack was fabricated with a bottom-up assembly method involving multiple wet and dry transfers [23, 47, 48]. In the first step, graphene flakes (which act as the back-gate electrode) were synthesized using chemical vapor deposition (CVD). The graphene was transferred onto a Si substrate with a 300 nm-thick SiO₂ coating by the wet bubble transfer method. In the next step, we prepared poly (methyl methacrylate) (PMMA)/poly (vinyl alcohol) (PVA)/300 nm SiO₂/Si substrates and separately exfoliated h-BN, MoS₂ flakes onto the substrate via mechanical exfoliation with a Scotch tape. The exfoliated h-BN flakes (serving as the gate dielectric layer (h-BN_b)) with thicknesses in the range of 3–20 nm were selected for deposition on top of graphene. The thicknesses of the h-BN_b were confirmed by AFM after electrical measurements. After the dissolution of PVA in hot water, the h-BN/PMMA film was detached from the substrate and floated on the water surface. We used a special holder with a hole to pull out h-BN/PMMA film and load it onto micro-manipulator in a reverse manner. Then, the desired h-BN flake was aligned with the target graphene on 300 nm SiO₂/Si substrate and held in contact for 15 min at 140 °C to ensure that PMMA film was entirely isolated from the holder. A similar process was employed to transfer the MoS₂ monolayer flake on top of the h-BN_b. The source (S), drain (D), and gate (G) were fabricated using a combination of e-beam lithography followed by the deposition of Cr/Au (10/50 nm). Finally, another h-BN flake (h-BN_t) was transferred on top of the graphene/h-BN/MoS₂ stack, thereby forming a passivated MoS₂ channel structure. In the last step, all samples were annealed at 300 °C for 3 h in a H₂/Ar atmosphere (H₂/Ar ratio of 50/200 sccm). The complete sequence of the whole fabrication is illustrated in figure S1 with the help of optical microscope images.

The AFM images of the samples were recorded using an SPA400 (SEIKO) atomic force microscope. Raman spectrums were measured using the Witec system (532 nm wavelength). All electrical transport measurements were performed in high vacuum (10⁻⁶ Torr) unless it is mentioned with a probe station and source/measure units (Keithley 4200 and Agilent B2900A).