Encapsulation of graphene transistors and vertical device integration by interface engineering with atomic layer deposited oxide

Figure 1(a) schematically shows the process of our ALD device encapsulation. Initially a wafer containing an array of globally back-gated two terminal CVD graphene channels on doped-Si/SiO₂ (dielectric thickness t_ox = 300 nm) was fabricated by e-beam lithography, using oxygen plasma etching to define channels with a length and width of L = W = 10 μm, respectively, and sputtered Ni (70 nm) contacts. The field effect characteristics of a typical as-fabricated device are shown in figure 1(b) where the graphene channel conductivity σ is related to the current I_d by σ = (L/W)*(I_d/V_sd), with applied source-drain voltage V_sd = 10 mV unless stated otherwise, which is plotted as a function of gate electric field E_BG = V_BG/t_ox. The gate voltage is swept from negative to positive values (up sweep) and then back to negative values (down sweep) with a rate of dE_BG/dt = 0.37 MV cm⁻¹ s⁻¹ (dV_BG/dt = 11 V s⁻¹). In line with previous literature at room temperature and under ambient conditions significant unintentional p-type doping is observed where the conductivity minimum associated with the charge neutrality point E_CNP is observed at high positive gate voltages [16]. For the device shown in figure 1(b) we measure a peak field effect hole mobility μ_h, for the up sweep, to be 620 cm² V⁻¹ s⁻¹. Such a value is typical for polycrystalline CVD films [33], the grain size here being ∼10 μm as determined by scanning electron microscopy (SEM) [25], and it is important to note that this two-terminal mobility value is reduced by including contact resistances [19].

Zoom In Zoom Out Reset image size

For a number of device applications ambipolar transport in graphene devices is desirable. As such, the unipolar (p-type) behaviour observed in as-fabricated devices needs to be converted to ambipolarity and, importantly, this must be stable during device operation and storage in ambient conditions. Hence, we tune the ALD encapsulation layers using three different growth conditions to determine the interface quality required for stable ambipolar device performance. The total thickness of the Al₂O₃ was kept constant at 90 nm for all samples to separate interface effects from water vapour/atmospheric transmission effects. The three growth conditions were as follows: (1) direct deposition of 90 nm Al₂O₃ at 120 °C using H₂O/TMA precursors; (2) a pretreatment of ten pulses of O₃ followed by 10 nm growth of Al₂O₃ interface layer using O₃/TMA at 80 °C followed by an additional layer of 80 nm using H₂O/TMA growth at 120 °C; (3) a pretreatment of ten pulses of H₂O at 120 °C followed by 90 nm of growth using H₂O/TMA precursors at 120 °C, as shown schematically in figure 1(c). During pretreatment the oxidant pulse and purging time were the same as those of the subsequent growth. Consequently, the pretreatment time is typically on the order of a few minutes. The ten pulses of both the oxidants during pretreatment were selected to achieve sufficient surface saturation on graphene to promote nucleation, based on previous reports [26, 31]. A detailed study of the parameter space of gaseous pre-treatments and their effects on nucleation can be found in [27]. For long term stability the barrier properties of the encapsulating ALD layer is crucial to obtain low gas transmission rates which would begin to affect the graphene over time [11]. Hence, devices were encapsulated with 90 nm of Al₂O₃ which has been demonstrated to be sufficient to enable long term stability [10]. We stress, however, that if the barrier properties of the film are further optimised this thickness requirement is likely to be reduced. To obtain ambipolar behaviour with minimal residual doping the deposition temperature was kept to 120 °C, as higher temperatures have been shown to result in n-type devices [34]. During O₃ exposure the temperature was kept to 80 °C to prevent damage to the graphene [29, 35].

Figure 1(b) summarises the electronic performance of these three encapsulation techniques which are found to have a significant effect on the graphene—oxide (2D—3D) interface. Electrical transport measurements were taken under ambient conditions following a further lithography step to expose and etch through the Al₂O₃ above the probing pads as detailed in the methods section. For direct deposition without pretreatment we observe some reduction in residual doping levels and an increase in mobility to μ_h = 830 cm² V⁻¹ s⁻¹. However, significant hysteresis of ΔE_CNP = 0.3 ± 0.085 MV cm⁻¹ is still observed, where we define ΔE_CNP = E_CNP(down) − E_CNP(up). Using a simple capacitor model, with the gate capacitance per unit area C_G, we can estimate the corresponding change in carrier density due to trapped charges to be Δn = C_G t_ox ΔE_CNP/e = 6.5 × 10¹¹ cm⁻². This suggests that a large density of trap states remain at the interface after the encapsulation. In contrast, the device characteristics for the two encapsulated samples using gaseous pretreatments are dramatically different with minimal hysteresis. Indeed, for the H₂O pretreatment we observe a highly reproducible average residual doping level of 3 × 10¹¹ cm⁻² (p-type), with a standard deviation of 4 × 10¹¹ cm⁻², as shown for 30 devices in figure 1(d). Some devices show low levels of n-type doping due to negative charges in the Al₂O₃ matrix [36]. Importantly, levels of hysteresis are significantly reduced to 0.033 ± 0.085 MV cm⁻¹ and 0.017 ± 0.085 MV cm⁻¹ for O₃ and H₂O pretreatments, respectively. For the H₂O pretreated encapsulation this corresponds to a remarkably low hysteresis induced by carrier trap density of Δn ∼ 3.6 × 10¹⁰ cm⁻². This value is comparable to the best performance devices reported in [10], but achieved while halving the number of encapsulation process steps. Similarly, [8] achieved comparably low levels of hysteresis using short (≤1 μs) gate pulses whereas our measurements are performed under DC conditions. In addition, the values of μ_h for the devices shown in figure 1(b) increase to 920 cm² V⁻¹ s⁻¹ and 950 cm² V⁻¹ s⁻¹ for O₃ and H₂O pretreatments, respectively. This mobility improvement can be linked to the reduction in charge traps in the vicinity of the graphene as such charged interface states are known to act as scattering centres [37]. Further improvements of mobility can be obtained through increasing the grain size of the graphene film (figure S1) [25]. Thus, in particular for the H₂O pretreated sample, the up and down sweeps are almost indistinguishable. We can therefore conclude that the growth of 90 nm of Al₂O₃ directly on graphene using an H₂O pretreatment can provide thorough passivation of graphene FETs and almost doping-free ambipolar behaviour whilst maintaining, or indeed enhancing, carrier mobility under ambient conditions.

As reported previously [7] the level of hysteresis is strongly dependent on a number of measurement factors, in particular gate sweep rate and sweeping voltage range (sweep magnitude). By observing the hysteresis in graphene FETs under pulsed electrical measurements it has been shown that when gate voltage pulses are applied shorter than the characteristic trapping time constants of interface traps, typically ≤1 μs, hysteresis is suppressed [8]. This characteristic trapping time constant also results in a sweep rate dependence of DC measurements which is often particularly strong in the commonly used device testing regime [7–10]. Figure 2(a) shows a comparison of the sweep rate dependence of hysteresis for encapsulated graphene devices using the three processes described above. The sweep rate was varied, dE_BG/dt = 0.01–0.74 MV cm⁻¹ s⁻¹ (0.3–22 V s⁻¹), by maintaining a constant step size and sweep magnitude of 3.33 MV cm⁻¹ (V_BG = ±50 V) whilst varying the time delay between steps. As expected, hysteresis decreases with increase in sweep rate. Device encapsulation using direct deposition results in large hysteresis (ΔE_CNP = 0.7–0.5 MV cm⁻¹) and is found to be strongly dependent on sweep rates below 0.24 MV cm⁻¹ s⁻¹. By comparison the O₃ pretreated encapsulation provides a reduced level of hysteresis where ΔE_CNP = 0.3–0.1 MV cm⁻¹, however this remains strongly rate dependent at low sweep rates. Once again, the H₂O pretreated encapsulation enables the lowest levels of hysteresis, down to just ΔE_CNP = 0.07–0.03 MV cm⁻¹, which is only very weakly rate dependent. Note that whilst the magnitude of the hysteresis changes depending on the interface the relative frequency dependence is similar for all the processes, indicating the same type of charge traps are involved [12]. Using a fixed sweep rate of 0.133 MV cm⁻¹ s⁻¹ (4 V s⁻¹), figure 2(b) shows that these trends continue as we vary the sweep magnitude. The most striking example is from the direct growth encapsulation where at large magnitudes the Dirac point hysteresis spans almost a quarter of the voltage range. The O₃ and H₂O pretreated encapsulations provide a greatly reduced variation, consistent with a lower density of charge trap sites.

Zoom In Zoom Out Reset image size

The presence of charge traps in the vicinity of graphene and its effect on the device performance is closely linked to reliability and reproducibility. We have investigated the device characteristics for a number of successive measurement cycles in order to quantify this effect and compared the advantages of optimised gaseous pretreatments on device stability. Figures 2(c)–(e) shows the first and last of 100 successive measurement cycles over the course of 30 min in ambient conditions for each encapsulation technique. Encapsulation using direct deposition, in addition to pronounced hysteresis, shows a substantial difference in the device characteristics and deterioration in the performance between sweep 1 and sweep 100 (figure 2(c)). A large shift in E_CNP is observed over time equivalent to an effective carrier density change of n₁₀₀ − n₁ ∼ 6.5 × 10¹¹ cm⁻². Such an effect is rarely commented on in the literature to date but is clearly highly undesirable for any applications requiring reproducible stable device characteristics over a number of measurement cycles. While the levels of hysteresis and device stability is greatly improved using O₃ pretreated encapsulation, a smaller but still finite shift of n₁₀₀ − n₁ < 1 × 10¹¹ cm⁻² is observed. No shift in E_CNP is observed within measurement uncertainties for the H₂O pretreatment over 100 measurements. This emphasises the potential for H₂O pretreatments in ALD growth to achieve stable and reproducible graphene device characteristics.

Clearly the ultimate quality of the device is strongly linked to the quality of the SiO₂–graphene–Al₂O₃ interfaces. To gain a more in depth understanding of these interfaces and the role of gaseous pretreatments we probed the nucleation of Al₂O₃ during the first few nm of growth. It is important to note at this point that the three growth conditions we have focused on are representative of a rich parameter space offered by ALD [27]. As a model system we study nucleation of Al₂O₃ on the surface of highly oriented pyrolytic graphite (HOPG). Wetting on the pristine surface of graphite is notoriously difficult [38]. On the other hand graphene grown by CVD and transferred using polymer support layers typically has grain boundaries, wrinkles and sources of contamination which should assist wetting and hence ALD nucleation. In addition, it has been shown that the wettability of CVD graphene is strongly dependent on the supporting substrate [38] and air exposure over time [39], thus we take mechanically exfoliated HOPG, within minutes of exfoliation, as the extreme case. Figure 3 shows the schematic nucleation replicas we follow based on SEM images of a nominally 2 nm thick deposition (20 ALD cycles) of Al₂O₃ on thick (>100 layer) mechanically exfoliated HOPG on an SiO₂ substrate using direct growth, or O₃, H₂O pretreatments as shown in figures 3(b)–(d), respectively. Following direct deposition very sparse dendritic growth of Al₂O₃ is observed in the SEM as areas of light contrast in figure 3(b). We observe preferential deposition along energetically favourable step edges. Given that the O₃ pretreatment ALD process is optimised to deposit nm scale thicknesses [31] we find, as expected, that this provides the highest overall coverage (figure 3(c)). However, across the sample areas of nanoscale pores can be seen which result in a relatively low overall film density. For H₂O pretreated growth, a greatly improved coverage compared to direct deposition is observed (figure 3(d)). Due to the use of higher deposition temperature relative to O₃ pretreatment, the areas which are covered are already showing the signs of dense film growth resulting in a much more complete passivation once full coverage is obtained.

Zoom In Zoom Out Reset image size

We can relate the three nucleation scenarios to the final device performance. In the first case of direct deposition very inhomogeneous growth results in a minimal passivation of SiOH⁻ groups at the SiO₂ surface. It assists in reducing the residual doping allowing observation of charge neutrality points within the operating voltages, but large hysteresis values are maintained. For the O₃ pretreatment, a strong reduction in hysteresis is observed, although a complete surface passivation is not achieved in spite of the relatively homogeneous nucleation. During the pretreatment, the O₃ carries along a significant amount of O₂ which, in the presence of trace amounts of H₂O, will drive the O₂/H₂O redox reaction toward reactive hydroxide species: ${{\rm{O}}}_{2}\,+\,2{{\rm{H}}}_{2}{\rm{O}}+4{e}^{-}\,\leftrightarrow \,4{\text{OH}}^{-}.$ In addition, the use of O₃ as oxidant in ALD has been known to result in oxygen-rich Al₂O₃ layer due to the presence of formate and carbonate species from incomplete reactions [40–42], which may later decompose into hydroxyl species and act as additional charge trap sites at the top interface. While a denser and more stoichiometric interface layer could be obtained at 120 °C, this may create defective graphene [29, 35]. Furthermore, the presence of nanoscale pores in the interface layer prevents complete surface passivation. On the other hand, the lower hysteresis obtained by H₂O pretreatment may first appear counterintuitive as H₂O increases the surface concentration of SiOH⁻ groups on SiO₂ surface [43] and at 2 nm the coverage of H₂O pretreatment growth is incomplete. However, surface saturation by H₂O drives the O₂/H₂O redox reaction toward H⁺ leading to the depletion of reactive hydroxyl and peroxide species [34, 44]: ${{\rm{O}}}_{2}\,+\,4{{\rm{H}}}^{+}\,+4{e}^{-}\,\leftrightarrow \,2{{\rm{H}}}_{2}{\rm{O}}.$ In addition, the remaining hydroxyl species are consumed more readily by TMA than the formate species [41], resulting in further removal of charge trap sites.

To demonstrate the advantages that this optimised approach for device manufacturing we fabricate a vertically integrated device stack, i.e. two levels of devices on the same chip which may operate either independently or in communication with one another, a concept outlined in figure 4(a). Without appropriate encapsulation, transferring another layer of graphene on top of a set of devices and performing several additional lithography steps will severely deteriorate the properties of the underlying graphene. We begin with a set of globally gated graphene devices encapsulated using 90 nm of H₂O pretreated Al₂O₃. After testing (figure 4(b)), a second layer of CVD graphene is transferred. A top layer of devices was fabricated both in isolation, for modulation using the global back gate as in figure 4(c), and layered directly above the initial devices such that interlayer gating was possible (figure 4(d)). The top layer of graphene devices was then encapsulated with a further 90 nm of H₂O pretreated Al₂O₃. Figure 4(b) shows that even after 2 months and several processing steps the bottom encapsulated layer of graphene shows only a minimal shift in E_CNP from slightly n-doped to almost undoped, and no significant change in μ. Figure 4(b) and c shows that each layer has a E_CNP close to 0 MV cm⁻¹ and very low hysteresis values consistent with the results described above. Additionally, we can use the vertical device structures to have a graphene-gated graphene FET shown in figure 4(c). Perhaps the most exciting possibility enabled by this technique is to manufacture interlayer devices where, for example, within the same footprint in a chip multiple functionalities can be contained (figure 4(a)). By taking advantage of ambipolar transport in both layers, a combined graphene FET and inverter vertical device structure is realised as shown in figure 4(e). As expected, inverting voltage characteristics were obtained indicating that the graphene in the vertical structure maintains the homogeneity and low doping suitable for device operation [45, 46]. These results highlight that H₂O pretreated Al₂O₃ deposition not only achieves a high quality graphene—oxide interface but that the barrier properties of the Al₂O₃ film are sufficient to allow long term stability under common lithography conditions.

Zoom In Zoom Out Reset image size

The advantages of ALD oxides for device encapsulation are widely accepted and routinely employed at an industrial scale. Process parameters were adjusted, for example in organic light emitting diode and photovoltaic applications, by considering the specific requirements of the active materials, i.e. organic semiconductors or Si respectively. So it is that for graphene, being a relatively new 2D material facing unique integration challenges such as its extremely high surface-area-to-mass ratio, these ALD processes parameters need to be understood and refined following a material specific methodology. Initial success has been achieved in past few years by the assistance of ex situ nucleation sites on graphene. Specifically, 2–3 nm of metal and metal oxide seed layers deposited by e-beam evaporation have been shown to be highly effective, but this additional process step spans several hours, a time which is equal to the growth time of a high quality ALD oxide layer. This also typically involves the devices being transferred from vacuum to ambient conditions, potentially compromising the quality and reproducibility of the interface. Hence, in the present study we use gaseous oxidant species as in situ pretreatments to promote nucleation within the ALD chamber and achieve a one-step encapsulation process. Previous reports [26, 31] have used H₂O and O₃ pretreatments, respectively, and discussed their importance in obtaining uniform coverage of Al₂O₃. In the present study, we carried forward this concept to determine their compatibility for large area CVD monolayer graphene devices, where we show the clear benefits of using H₂O over O₃ pretreatments for SiO₂ supported graphene and device encapsulation. The time required for the gaseous pretreatment was only a few minutes, which makes it highly scalable with fast processing compared to many ex situ pretreatments [10]. The doping, hysteresis and charge trap density values obtained here are amongst the best in the literature showing that neither the quality of graphene nor the encapsulation layer was compromised. It is worth noting that we achieve this effective encapsulation whilst using comparatively small grain size graphene with a polymer supported transfer technique and despite having no additional cleaning or annealing steps beyond acetone and isopropyl alcohol. The voltage sweep rate dependent study also revealed the cause of the hysteresis is due to same charge trap species as discussed in the literature and its removal and encapsulation can be stongly governed by the use of gaseous pretreatments. This may open new avenues for neuromorphic memory applications where researchers are seeking to obtain controllable, finite levels of hysteresis in graphene devices [47], but often struggle to achieve reproducible characteristics. Two layers of graphene device encapsulation were realised on the same chip, each showing the performance required for vertical device integration. Whilst we do not observe a voltage gain in the graphene gate-graphene channel integrated inverter, which is expected to be the case for graphene with such a thick oxide dielectric [45], the interaction between two layers of graphene demonstrates the feasibility of future 3D chip fabrication using graphene and other 2D materials.

To conclude, we have demonstrated a scalable and simple approach towards encapsulating and passivating high quality CVD graphene electronic devices by using a gaseous H₂O pretreatment to allow direct ALD of dense Al₂O₃ films on graphene. Using this technique, contained within a single piece of equipment, we eliminate the additonal time consuming processing steps and tools required to deposit the metal or metal oxide seed layers most commonly used to promote ALD growth. The obtained graphene doping levels and DC hysteresis values are amongst the lowest values reported to date by any technique. Moreover, we also achieve the desired characteristics for multi-level, vertically stacked devices. These results highlight the importance of not only the quality of the ALD grown top dielectric but also the material specific choice of growth parameters required. We hope that this work will motivate further device performance enhancements for new generations of low dimensional materials by using in situ gaseous pretreatments within the large parameter space offered by ALD.

Graphene growth and device fabrication

ALD Al₂O₃ layer

Transport characteristics

This work was supported by the EPSRC (Grant Nos. EP/K016636/1, GRAPHTED and EP/L020963/1) and the ERC (Grant No. 279342, InsituNANO). JAA-W acknowledges a Research Fellowship from Churchill College, Cambridge. JS acknowledges support from NUDT. ZAVV acknowledges funding from ESPRC grant EP/L016087/1. ACV acknowledges the Conacyt Cambridge Scholarship and the Roberto Rocca Fellowship. RW acknowledges EPSRC Doctoral Training Award (EP/M506485/1).