Upgrade of the CMS tracker

The LHC machine is planning an upgrade program which will smoothly bring the luminosity up to or above 5 × 1034 cm−2s−1 sometimes after 2020, to possibly reach an integrated luminosity of 3000 fb−1 at the end of that decade. The foreseen increases of both the instantaneous and the integrated luminosity by the LHC during the next ten years will necessitate a stepwise upgrade of the CMS tracking detector. During the extended end-of-year shutdown 2016-2017 the pixel detector will be exchanged with a new one. The so-called Phase1 Pixel foresees one additional barrel layer and one additional end-cap disk, a new readout chip, reduction of material, and the installation of more efficient cooling and powering systems. In the so-called Phase2, when LHC will reach the High Luminosity (HL-LHC) phase, CMS will need a completely new Tracker detector, in order to fully exploit the high-demanding operating conditions and the delivered luminosity. The new Tracker should have also trigger capabilities. To achieve such goals, R&D activities are ongoing to explore options and develop solutions that would allow including tracking information at Level-1. The design choices for the CMS pixel and outer tracker upgrades are discussed along with some highlights of the R&D activities.


Introduction
The first data taking period (Run 1) at LHC, which ended in 2013, was very successful. The LHC delivered about 30 fb −1 of proton-proton collisions at center-of-mass energies of √ s = 7 − 8 TeV and at a peak instantaneous luminosity of up to 7.7 × 10 33 cm −2 s −1 , and the CMS experiment run smoothly with efficiencies better than 95% for each of the subdetectors thus providing fundamental physics results that culminated in the discovery of the Higgs boson [1]. Despite the performance of the CMS Tracker, which exploits an all silicon technology with a pixel and a strip detector, has so far been excellent, the foreseen increases of both the instantaneous and the integrated luminosity by the LHC during the next ten years will ask for a stepwise upgrade of the CMS tracking detector. During the currently ongoing Long Shutdown 1 (LS1), work is taking place at LHC to allow the design center-of-mass energy of 14 TeV to be achieved. For what concerns the CMS Tracker, consolidation of the cooling and dry air systems is taking place, to enable operation of the tracker at nominal temperatures. Data taking will resume in 2015 and last until Long Shutdown 2 (LS2) in 2018. For this Run 2 a peak luminosity of about 2 × 10 34 cm −2 s −1 is expected. The pixel detector is the first part of the tracker that will show limitations in high-rate and therefore will be upgraded already during the extended winter technical stop 2016-2017 [2]. This is referred to as the "Phase1 Pixel Upgrade". The new detector will feature 4 barrel layers and 3 forward discs, yielding on average one more spatial point measurement per track compared to the present system, in the whole acceptance range. Optimized engineering of mechanics and services, together with two-phase CO 2 cooling, will provide a substantial reduction of material in the tracking volume, while upgraded front-end ASICs will enhance the robustness of the system at high rate.
No tracker upgrades are foreseen for LS2, but a replacement of the innermost layer of the pixel detector might be required after 250 fb −1 , thus the new pixel detector together with the current outer strip tracker will provide optimal tracking performance to CMS through 2020.
After the upgrade of the accelerator complex foreseen for the beginning of the next decade in the Long Shutdown 3 (2020-2022), the LHC is expected to turn into the HL-LHC in which it  Figure 1. Performance of the current pixel detector (blue squares) and upgrade pixel detector (red dots) for tt events: (a) tracking efficiency and (b) fake rate as function of the average pileup. Results take into account the expected ROC data loss. is planned to deliver an instantaneous luminosity of 5 × 10 34 cm −2 s −1 . The quoted luminosity corresponds to approximately 100 pileup events per bunch crossing if the operating frequency is 40 MHz, while the number of pileup events would be larger than 200 if the same luminosity will be achieved with 20 MHz operation, which represents a much more demanding condition for the detectors. For such scenario, CMS will eventually collect up to 3000 fb −1 , after several years of operation, and its tracking system will have to be improved in terms of radiation resistance, readout granularity and ability to contribute information to the Level-1 trigger. A whole new Tracker system, both pixel and outer tracker, is hence needed, which will be installed during LS3. This is referred to as the "Phase2 Upgrade" of the CMS tracker.
In this paper, the Phase1 Pixel Upgrade and the Phase2 Upgrade of the outer tracker are discussed.

The Phase1 Pixel Upgrade
The present CMS pixel detector [3], conceived over 10 years ago, is a first generation hybrid pixel detector. It consists of three cylindrical barrel layers (BPIX) in the central region supplemented by two forward disks (FPIX).
The main motivation for an upgraded pixel [4] detector is justified by the sizable reduction of the data loss which the current system will suffer. At the design luminosity (10 34 cm −2 s −1 ) the buffer size and readout speed of the current pixel Read Out Chip (ROC) will lead to a dynamic inefficiency in the pixel detector of 4% (16%) with 25 ns (50 ns) bunch spacing. The inefficiency increases exponentially with luminosity. At 2 × 10 34 cm −2 s −1 with 25 (50) ns bunch spacing the ROCs in the inner region will suffer an inefficiency of 16% (50%) leading to an overall degradation of tracking performance. With both the effects of dynamic data loss and the high pileup expected for 2 × 10 34 cm −2 s −1 (25 ns crossing time), the loss in tracking efficiency for the current detector is about 10% (16%) for tt (muons), while for the upgraded detector it is reduced to 1.5% (3.7%) for tt (muons), as shown in figure 1 (left). The track fake rate, also shown in figure 1 (right), rapidly increases with pileup but is about a factor of two lower for the upgrade pixel detector.
In addition, the radiation hardness of the detector is not sufficient for operation to the end of Phase1, when the LHC luminosity will exceed the design value. The current detector contains  also significant passive material that degrades measurements due to multiple scattering, photon conversions and nuclear interactions. Last but not least the three-hit coverage of the detector is not completely hermetic, leading to 10 ÷ 15% inefficiencies at |η| < 1.5 and larger inefficiencies in the region 1.5 < |η| < 2.5.
Therefore the pixel detector will be replaced already in the winter shutdown 2016-17, requiring careful minimization of the impact on data taking. The goal of the upgraded Phase1 pixel detector is to be fully efficient at a luminosity of 2 × 10 34 cm −2 s −1 , with less material and with four hit coverage up to |η| < 2.5. For this reasons a new pixel detector with a fourth barrel layer, an extra disk on each side and a new ROC has been proposed. The layout of Phase1 pixel detector compared to the current one is shown in figure 2. The barrel layers are at radii of 3.0, 6.8, 10.2, and 16.0 cm, and the disks at positions of ±29.1, ±39.6, and ±51.6 cm from the interaction point. The amount of passive material has been significantly reduced by moving readout electronics and connectors further out. Bi-phase CO 2 cooling will also replace the C 6 F 14 single phase cooling currently used, allowing smaller heat exchanger pads and pipes. The reduction in material inside the pixel tracking volume is shown in figure 3. Despite the increase in the number of pixels, a factor 2.4 reduction in the weight of the BPIX is foreseen and a 40% reduction for the FPIX. This reduction in the amount of passive material will have a large impact on the track reconstruction efficiency as well as electron and photon identification and resolution, thus playing an important role in the reconstruction of final state signatures involving electrons and photons.
The new "PSI46dig" ROC is made in 250 nm CMOS technology as the present chip (PSI46) and is heavily based on it. Both chips feature a column drain architecture. To reduce data losses, the depths of data and time stamp buffers have been increased. Simulations indicate that data losses in the first layer will decrease from 16.0% (50%) to 2.4% (4.8%) for a bunch spacing of 25 ns (50 ns) at 2.0 × 10 34 cm −2 s −1 . Test beam results show that stable and low noise operation is possible with a threshold of 1300 electrons, a significant improvement with respect to the present value of 2800 electrons. The readout protocol was changed from analog-coded to digital and the ROC readout speed was increased from 40 to 160 Mbit/s. The second version PSI46digV2 is currently under test. One more iteration is foreseen to fix remaining minor issues before moving to the final production.
The redout channels will increase by a factor 1.9, thus implying an increase of power losses on the supply cables by a factor of about 4. Since the present cables and power supplies are to be -3 - reused, a powering scheme based on DC-DC converters has been developed [5], where the power is supplied at a higher voltage and lower current.
The improvements of the Phase1 Pixel detector have a net effect on the expected performances: pattern recognition, track parameter resolution, vertexing, and b-tagging performance of the upgraded detector are expected to be significantly better than in the current detector. To estimate the foreseen improvements, full GEANT4 based simulations have been carried on. An iterative tracking algorithm has been used for the track reconstruction which uses triplet seeds and quadruplet plus triplet seeds for the current geometry and for the upgraded geometry, respectively [2]. Tracking efficiency in a simulated tt sample with 50 pile-up events is found to be improved by about 10-20% depending on pseudo-rapidity and momentum range. Also significant reduction in the rate of fake tracks, due to the reduced multiple scattering, especially for low momentum tracks, is found. Fake tracks are caused by the incorrect association of hits and are much more likely in regions with more passive material. Similar studies have been done also using muon gun events. Indeed a number of important physics channels involve final states with high energy isolated muons, like the CMS golden channel H → 4µ. At 50 pile up events, the current detector suffers a 15% drop in efficiency w.r.t. the upgraded detector over the whole momentum range.
The new pixel detector shows a significant improvement, of the order of 30-40%, in the transverse and longitudinal impact parameter resolutions as well as in primary and secondary vertex resolutions (about 20% improvement).
The improvement in tracking efficiency, fake rate, impact parameter resolution, and vertexing all contribute to significantly increase the b-tagging performance of the new detector. The tagging of b jets is a key ingredient of many physics analyses: indeed, b-jets are often produced in association with the Higgs boson or in its decays, and final states involving b-jets are also expected in many New Physics models. Improving the b-tagging capability is, hence, of crucial importance. Figure 4 shows the fraction of c-jets and (light) dus-jets that are misidentified as a b-jet as a function of the efficiency for identifying a b-jet correctly as a b-jet. The results show that the b-tagging performance is significantly better for the upgrade pixel detector even at zero pileup when the performance of the current pixel detector is neither degraded by dynamic data loss nor by high pileup. , when the current pixel detector suffers due to the increase in dynamic data loss and to the higher number of pileup events, the difference in b-tagging performance is further amplified for the upgrade pixel detector. At a light quark jet b-mistag rate of 1% the b-tagging efficiency for b-jets in the upgrade detector is better by a relative 28% than for the current detector, while at a light quark jet b-mistag rate of 0.1% the performance for the upgrade detector is higher by a relative 46%. At high pileup the upgraded detector is able to almost regain the performance of the current detector at 0 pileup.

The PhaseTracker Upgrade
The Phase2 upgrade involves the replacement of the whole Tracker. The upgraded tracker will have to provide improved tracking performance in a more challenging environment, while producing at the same time fast information for the Level-1 trigger. The tracking should be robust enough in order to sustain operation with up to 200÷250 collisions per bunch crossing in the worst-case scenario of 20 MHz operation, thus increased granularity is required to maintain the occupancy at the level of a few percent. The detector should provide satisfactory performance up to an integrated luminosity of about 3000 fb −1 , to be compared with the original figure of 500 fb −1 ; this requires the selection of more radiation hard silicon sensor material, especially for the innermost regions, as well as more stringent criteria in the qualification of electronics and mechanical assemblies. The amount of material is the most severe limitation on the performance of the present tracker [7] and it is dominated by electronics and services (notably in the region between barrel and end-cap), thus to improve tracking performance at low transverse momentum, p T , the new tracker should foresee a significant reduction of the material. This fact together with the request for an increased granularity drove the choice of technologies for sensors, readout, powering and cooling. A binary readout is -5 -required to pack more data in the same available band-width. Power should be delivered at a higher voltage to reduce ohmic losses in the services and then converted to the required low voltage inside the tracking volume. DC-DC converter technologies under development for the Phase1 Pixel upgrade will certainly be useful also for the Phase2 upgrade. Finally a CO 2 evaporative cooling system, again based on the experience developed for the Phase1 Pixel upgrade, is foreseen, which allows to deliver more cooling power through the same pipe section. In addition, more radiationtolerant sensors are mandatory. Intense R&D activities are going on to identify the most suitable sensors for the Phase2 Tracker. Wafers of different materials, polarities and thickness, equipped with test structures and test sensors with different strip lengths, pitches and strip widths have been tested and irradiated both with protons and neutrons. Results show that the preferred option for very high fluences is p-type sensors with a thickness of 200 µm. At HL-LHC, the combinatorial background poses also problems to the Level-1 trigger, to the point where it is not possible to keep the trigger rate within the nominal range with reasonable cuts on the trigger variables. The CMS collaboration plans to improve the trigger, for example by installing a fourth layer of the Cathode Strip Chambers muon detector and re-designing the Level-1 trigger hardware. Nevertheless these improvements will be insufficient for the HL-LHC luminosity. A large event rate reduction factor is currently achieved in the High-Level software Trigger by using information from the Tracker. Including this information in the Level-1 processing would allow a much better rejection of combinatorial background. The collaboration is therefore studying the option of sending tracking information in real time to the Level-1 trigger. To reduce the volume of the trigger data, low p T tracks are locally rejected. So-called "p T modules" will perform the discrimination between high and low p T tracks. Level 1 tracks with p T above a certain threshold (e.g. 2 GeV/c) are then formed at the back-end.

Track trigger and p T modules
In order to transmit tracking information to the trigger processor, the amount of data to be shipped needs to be reduced. This could be achieved by performing an on-module p T selection, exploiting the CMS 4 T magnetic field to correlate hits in two closely-spaced sensors. If a threshold of 1 GeV/c to 2 GeV/c is achieved a reduction factor of one order of magnitude in the trigger rate is expected, which would allow to transmit each event's data at the collision frequency. The basic concept consists of correlating signals in two closely-spaced sensors: the distance between the hits in the x-y plane is correlated with the particle p T , allowing the p T discrimination to be made. A pair of hits that fulfils the selection cut is called a "stub" (see sketch of figure 5).
For a given p T , the distance between the hits forming the stub is larger at larger radii; moreover, if the module is placed in end-caps, the same discriminating power is obtained with a larger spacing between the two sensors, compared to a barrel module placed at the same radius. The effective p T cut provided by the modules in the different locations can be optimized by tuning both sensor spacing and acceptance window. The coordinates of stubs selected by the p T modules are sent to the trigger electronics at the back-end, where they have to be combined to form Level-1 tracks. The target is to reconstruct with high efficiency tracks of particles with p T > 2 GeV/c, which will allow to perform isolation cuts on calorimeter clusters. Two alternative approaches have been considered so far: hierarchical processing in FPGA or parallel processing in associative memories. Two types of p T modules are under development to instrument the radial region below (PS modules) and above 40 cm (2S modules).

2S-modules
The 2S module constitutes the simplest p T module assembly, being a sandwich of two strip sensors read out at the edges by the same set of front-end ASICs that implement the correlation logic. Figure 6 (top) shows a sketch of a 2S module: two sensors of about 10 × 10 cm 2 with 5 cm long strips and a pitch of 90 µm are mounted on a mechanical structure that provides support and cooling, and connected at the edges on the two sides of a high-density substrate carrying the ASICs. The sensors are wire-bonded from top and bottom to the readout hybrids, which each carry eight CMS Binary Chips (CBCs) plus a Data Concentrator chip. The estimated power consumption for the readout electronics, including the correlation logic, is below 2W, comparable to the lowest values in the present tracker. The main limitation of this type of module is the lack of segmentation in the z direction: in order to implement effective isolation cuts on calorimeter clusters, the Level-1 tracks must also have a reasonable precision in the z coordinate. In addition, the relatively long strips limit the use of this module to the radial region above 40 cm, because of occupancy.

PS-modules
To overcome the limitations of the 2S module, another p T module concept is under study, based on the assembly of one strip and one pixel sensors, called a PS-module and shown in figure 6 (bottom). The PS module is half as large as 2S module. The upper sensor carries short strips with dimensions of 2.5 cm×100µm, which are wire-bonded to hybrids with readout chips. The lower sensor is structured with large pixels of dimensions 1.5 mm×100µm, and is bump-bonded to dedicated readout chips.
Compared to the 2S module, this concept offers a sufficiently precise measurement of the z coordinate from the pixellated sensor, while the 2.5 cm long strips allow the module to be used down to 20 ÷ 25 cm radius. On the other hand the power consumption is expected to be more than 4W, dominated by the pixel ASICs: a four-fold increase in power density compared to the 2S module, which translates to a higher estimated density of material.
Both 2S and PS modules carry a DC-DC converter and a GBTX chip plus opto-electrical converters on service hybrids. R&D on the CBC [8] is well advanced. The 2 × 127 channel chip is fabricated in 130 nm CMOS technology and features unsparsified binary readout. The chip receives -7 - data from both sensors. After amplification and hit detection, clusters are formed. Following a cluster width discrimination step, clusters from the lower and upper sensor within a programmable window and with programmable channel offset are correlated. Stubs are formed and passed to the Data Concentrator. Tests with the second version of the chip (CBC2), using mini-modules with two CBC2s, a prototype hybrid and two test sensors, have shown that the chip works well. Stubs are correctly found both using test pulses and with cosmic muon data.

Tracker layout
A standalone dedicated software package ("tkLayout") has been used to quantitatively evaluate the different options and geometries for the tracker upgrade [9]. The software generates detector layouts starting from a reasonably small set of parameters, and also provides simple and flexible implementation of material densities for active and inactive volumes, including the routing of the services. The software calculates, as a function of pseudorapidity, the expected tracking precision and the performance potential for the Level-1 track reconstruction, as well as the fraction of converted photons and interacting pions. The package has been validated by modelling the present tracker, demonstrating an excellent agreement between the predicted performance and the one measured from the real detector. Detailed studies of several different layouts have been carried out. A classical layout with six barrel layers and five end-cap disks (see figure 7) has been chosen as baseline for further studies.
Compared with the alternative long-barrel geometry, it provides excellent performance at lower power, material and cost. The inner region with r < 60 cm will be instrumented with PS modules, while 2S modules will be installed further outside. Examples of the improvements in performance achievable with the new tracker compared to the current one are shown in figure 8:  The region with r < 60 cm will be instrumented with PS modules (blue), while 2S modules (red) will be installed further outside. Also shown is the Pixel detector and a possible extension with forward disks covering the region in pseudo-rapidity up to 4, currently under study. -9 -current detector, while in the bottom the p T resolutions for single muons are shown for the outer upgrade and the current tracker. Currently the upgrade of the pixel detector for Phase2 is not at the same level of maturity as the one for the outer tracker. All the simulation studies done so far include as pixel detector the one under construction for Phase1. Recently, a feasibility study with a layout which foresees an extended coverage, up to a pseudo-rapidity of about 4, of the pixel detector has been started but still there are several open questions regarding the sensor technology, the redout chip technology as well as the possibility to include the extended pixel information into the Level-1 trigger.

Conclusions
A two phase upgrade of the CMS Tracker system is foreseen to fully exploit the potential of the Physics program offered by the stepwise increase in LHC luminosity.
The Phase1 pixel upgrade, to be installed in the extended shutdown 2016-17, has already entered in the production phase.
The Phase2 tracker upgrade foreseen a replacement of the whole tracker. The design of the new outer tracker is well advanced. Model designs that offer precise tracking capability in the harsh HL-LHC environment while also providing L1-trigger capabilities have been identified. R&D activities are ongoing both on sensors, mechanics and electronics. Studies to define the layout of the new pixel detector have been recently started. The requirement to contribute information to the trigger represents an unprecedented challenge for the tracker and detailed studies will be done for the Technical Proposal foresees for the second half of 2014.