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GOSSIPO-4: an array of high resolution TDCs with a PLL control

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Published 24 January 2012 Published under licence by IOP Publishing Ltd
, , Citation F Zappon et al 2012 JINST 7 C01081 DOI 10.1088/1748-0221/7/01/C01081

1748-0221/7/01/C01081

Abstract

GOSSIPO-4 is a prototype chip featuring an array of high resolution Time to Digital Converters with a PLL control that has been taped out the 9th of August 2011. This prototype is the successor of GOSSIPO-3 test chip and the precursor of the 65k pixel chip TimePix3. The prototype is being developed to test a set of new features that will be used in TimePix3, including a 8 pixel structure sharing one fast oscillator with a new topology, a PLL to provide the control voltage to the oscillators, a custom fast counter and a new small-area cell library.

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10.1088/1748-0221/7/01/C01081