Abstract
A novel approach to first-level hardware triggering in the LHC experiments has been studied and a prototype system built. Calorimeter trigger primitive data ( ∼ 5 Tb/s) are re-organised and time-multiplexed so that a single processing node (FPGA) may access the data corresponding to the entire detector for a given bunch crossing. This provides maximal flexibility in the construction of new trigger algorithms, which will be an important factor in ensuring adequate trigger performance at the very high levels of background expected at the upgraded LHC.
A test system that incorporates all the key technologies for a final system and demonstrates the time-multiplexing and algorithm performance is presented.
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