Secondary particle acquisition system for the CERN beam wire scanners upgrade

The increasing requirements of CERN experiments make essential the upgrade of beam instrumentation in general, and high accuracy beam profile monitors in particular. The CERN Beam Instrumentation Group has been working during the last years on the Wire Scanners upgrade. These systems cross a thin wire through a circulating beam, the resulting secondary particles produced from beam/wire interaction are detected to reconstruct the beam profile. For the new secondary shower acquisition system, it is necessary to perform very low noise measurements with high dynamic range coverage. The aim is to design a system without tuneable parameters and compatible for any beam wire scanner location at the CERN complex. Polycrystalline chemical vapour deposition diamond detectors (pCVD) are proposed as new detectors for this application because of their radiation hardness, fast response and linearity over a high dynamic range. For the detector readout, the acquisition electronics must be designed to exploit the detector capabilities and perform bunch by bunch measurements at 40MHz. This paper describes the design challenges of such a system, analysing different acquisition possibilities from the signal integrity point of view. The proposed system architecture is shown in detail and the development status presented.


Introduction
A beam wire scan is an interceptive method for transverse beam profile measurements. The working principle of wire scanners consists on the passage of a very thin carbon wire (∼30um) through the particle beam. The secondary particle shower generated by the beam/wire interaction, during the wire passage, is detected outside of the beam pipe and transformed into an electrical current proportional to the loss intensity. The beam profile is reconstructed by plotting the losses intensity versus the wire position (figure 1 left). Using the measurements of these devices the beam emittance, and therefore the accelerator luminosity are calculated.

Beam wire scanners at CERN
Currently at the CERN complex, 32 beam wire systems are located along the injector chain and in the Large Hadron Collider (LHC). These devices are used on a regular basis by the accelerators operators to assess the characteristics of the beams produced by the injector chain before reaching -1 - the LHC. In many cases wire scanners are used as a reference for the calibration of other profile monitors such as the Beam gas ionization profile monitors (BGI). Accuracy, performance and availability of wire scanners are key factors.
In terms of mechanics, three different systems, optimized for each accelerator, are used: "Linear Scanners" for LHC and SPS, "Rotating" for SPS and "Rotating Fast" for PSB and PS [1]. These systems share some common characteristics, such as the movement transfer air/vacuum through bellows and scan speed limitations. Bellows have a limited number of cycles and could compromise the accelerators vacuum in case of breakage, and current scan speeds do not allow to measure high intensity beams due to wire sublimation [2]. Moreover the use of complex mechanics leads to a mechanical play that reduces the systems accuracy performance. Secondary particles are detected by an organic/inorganic scintillator attached to a wheel of optical filters, after; a photo multiplier tube (PMT) transforms the optical signal into an electrical one. Finally, a pre-amplifier drives long CK50 cables (up to 250m) to the surface electronics, where the digitalization is performed (see figure 1 left). The beam characteristics must be known before doing a scan to set-up the system, selecting the proper filter and PMT gain, to avoid the electronics saturation and reach a suitable resolution. On this architecture, the dynamic range in any configuration is limited by the pre-amplifier, the Gaussian tails are sometimes shadowed by noise and the PMT saturation effect can lead to incorrect profile measurements.

Wire scanners upgrade
The development of a new scanner type is motivated by the need to measure smaller beam sizes at higher beam intensities. The basic concept is to combine the high velocity of the rotating fast scanners at 20ms −1 , to avoid wire damage, with an accurate and direct wire position determination without bellows. The expected beam profile measurement accuracy is set to 2µm.
For reaching such specifications and overcome previous systems limitations, a new mechanical design (compatible for PS, SPS and LHC), where all the mobile parts are located inside the vacuum chamber and share the same shaft, has been adopted [3] (see figure 1 right).
The upgraded secondary shower acquisition system aims to use polycrystalline chemical vapour deposition (pCVD) diamond detector. New electronics are therefore needed to cover high dynamic range without tuneable parameters, providing very low noise measurements for beam -2 - Gaussian tails determination or halo visualization. The design of such system must be compatible with any CERN accelerator and beam wire scanner location.

System architecture analysis
The design of such electronic system could be done in two different ways: maintaining the long cables up to the surface where the digitalization is performed, designing a very simple amplification chain in the tunnel (with the inherent signal quality degradation issues that long lines have with high bandwidth signals), or making profit of the latest radiation-hard developments at CERN. This last option implies the design of a front-end, where the diamond detector signal is digitalized on the tunnel and sent digitally to the surface through optical fibre. The following sections analyse different aspects to take into account for the system architecture selection.

Radiation environment studies
A life expectancy of ∼10 years was specified for the upgraded wire scanner readout electronics. Radiation at the LHC and its injector chain can give rise to stochastic and cumulative effects, causing radiation induced failures of exposed electronics.
The figure 2 left, shows the total ionization dose (TID) per year of two different periods at the SPS and PS beam wire scanners locations, according to the CERN radio protection group reports [4]. The dosimeters were placed close to the magnets and on the cable trays. Fluka simulations performed by the CERN radiation to electronics project [5] shows a factor 10 of TID reduction at ground levels, and a factor 100 on shielded areas with respect to the magnets position (see figure 2 right). These estimations allow us to define 100Gy/year for systems located on shielded areas of PS, and at some distance from the SPS and LHC beam pipes. For the total operational life, it is aimed a TID of 1kGy on 10 years.

Dynamic range coverage estimations
It is important to estimate the maximum charge that the pCVD diamond detector is going to detect at the beam wire scanner locations to avoid electronics saturation. For beam wire scanners, higher intensity losses are produced at the locations where the beams are thinner. This is the case for the LHC and SPS, with typical profile sigma from 300um and up to 8mm for nominal beams. The   figure 3 shows the pCVD charge estimations when the scanner wire is at the centre of the bunch on 5 SPS beam wire scanners locations based on their typical beam sigma [6].
For such calculations, Fluka simulations were performed, studying the dose deposited in a 1cm 2 x 500um pCVD diamond detector per interacting particle at 2m downstream of the interaction point. The particle interaction is evaluated taking into account the total number of particles of a bunch, the beam sigma and the wire diameter. Finally, using the material properties, the dose to charge conversion factor is extracted. In order to exploit the detector capabilities, the system must be designed to cover few tens of minimum ionizing particles (MIPs), Q pcvd(MIP) =3.6fC [7], up to about 1nC, which means a dynamic range around 1e6, including a safety factor of approximately one order of magnitude with respect to the SPS estimations.

CK50 Cable modelling and signal degradation
To study the detector bunch signal degradation on long cables, a CK50 cable model was developed in Matlab. This analytical model can be used later to check the impact of the bunch pulses degradation on the beam size determination. For model validation, measurements were taken on 176m of this cable, installed between surface and SPS underground tunnel, extracting its frequency and step responses. On the figure 4 left, the model Bode plot is shown on continuous blue, while the blue dots correspond to measurements. The temporal response, on the right picture, shows an agreement of the model against measurements as close as 92%.
Aditional measurements, to identify potential noise coupling, were performed during the long shutdown 1 (LS1). A LeCroy scope with input impedance 50ohms was connected on one side of the cable, while the other extreme was loaded at 50ohms. The noise recorded had normal distribution with an amplitude up to 1.25mVpp and a sigma value of 0.33mV, the main frequency component was located at the 330KHz band, the noise source remains unknown.

Scan simulations and beam width measurement error sources
Wire scan simulations were performed using the cable model obtained previously. A train of bunches (pulses), with longitudinal Gaussian intensity profile, was used to emulate the LHC/SPS nominal beam structure (bunch sigma: 1ns, bunch separation: 25ns). In addition, odd and even bunches were modulated separately with known Gaussian profiles, this emulates the wire passage through a beam that contains two profiles. The train of pulses is fed into the cable model (at 250m), and its output is then integrated on 25ns windows. Finally odd and even bunches integrals -4 -  are separated on two sets of data and Gaussian fits are performed to study the profiles width error.
Observations on the cable model output signal at 250m allowed us to confirm bunch pile-up, which finally leads to bunch profile cross-talk as shown on the following pictures.
For 10m of cable with 0.8 odd/even bunches profiles width ratio, the width error is in the order of 0.01%. However when 250m of cable are used, the profiles cross-talk leads to a width determination error of 2.5% (see figure 5 left), due to bunch pile-up. These errors are not only dependent on cable length, but also on consecutive bunches width relationship, the larger is the difference between consecutive bunches profiles; the larger is the error due to profile cross-talk, as shown on the figure 5 right.

Proposed system architecture
Due to the potential bunch profile coupling and the noise impact on the Gaussian tails measurements, it is proposed to acquire the pCVD diamond detector signal as close as possible from its source. This implies using the new Rad-Hard digital and analogue technologies developed at CERN for signal integration and data transmission.
-5 - The system architecture proposed is shown in figure 6. This is a front-end/back-end based architecture. The front-end system will be placed in the tunnel at ∼10m from the diamond detector (or shielded locations) to reduce the cable impact. The goal is to design a radiation hard front-end to perform charge integration at 40MHz, synchronous with the beam and with a very high dynamic range, and send this data through single mode optical fibre (SMF) using CERN's GBT optical link at 4.8Gbps [8] to the back-end. The front-end synchronization, data transmission and control will be performed through the optical link. For the back-end system the VME FMC Carrier board (VFC) [9] will be used. The back-end will manage the link synchronization with the bunch crossing frequency and will receive the data for processing and storage. The VFC SFP+ optical transceivers are planned to be used for the optical link (one VFC board can drive up to 4 front-end boards).

pCVD Diamond detector and signal splitting chain
Diamond detectors are basically a solid state ionization chamber. When a charged particle is passing the diamond bulk, the created charges are separated by the high voltage applied on its electrodes, and a current proportional to the deposited energy is then generated. These detectors, developed and characterized by the RD42 collaboration [10], have shown very good performances for single particle detection and for very intense losses, maintaining always a good linearity. Their performance in terms of temporal resolution and radiation hardness show better characteristics than silicon detectors. Moreover, pCVD diamond used as beam loss monitors [11] have demonstrated that they could also be used for the beam wire scanners applications.
In our design all the analogue part, up to the readout ASICs, will be adapted at 50 ohms to avoid undesired reflections. For the dynamic range coverage, several channels with different gains/attenuations will be acquired in parallel. The detector signal splitting will be performed with passive standard high power wideband DC-coupled RF splitters.

Readout ASICs
The pCVD diamond detector signal is planned to be integrated over temporal windows of 25ns. Several LHC experiments at CERN are carrying out an upgrade on their front-end electronics developing Rad-Hard ASICS. ICECAL [12] and QIE10 [13] were identified to be compatible with -6 - our application and candidates to be evaluated for the pCVD readout, their specifications are summarized in table 1.

GBT Optical link at 4.8 Gbps
The base solution for driving the optical link is based on the Rad-Hard GBTx ASIC [9] in combination with the VTRx module [14]; both are specially designed to be used on front-end systems exposed to radiation. However due to GBTx unavailability during the initial developments a backup solution, based on its emulation, was required. A flash-based Microsemi Igloo2 FPGA was selected for this, being the first 68nm Flash-based device with integrated SERDES. CERN has positive experiences with this technology in front-end systems and the initial irradiation tests are showing promising results [15].
It was necessary to adapt the official firmware offered by the GBT project, from Xilinx Virtex 6 to our specific FPGA (that was not supported). The code was successfully migrated, and made available for other users from LHCb and CMS under the name GBT-On-Igloo2.

Characterization of GBT implementation on Igloo2
GBT standard is based on frames of 120 bits of data sent every 25ns at 4.8Gbps. Each frame contains headers, payload and forward error correction. The front-end system must be synchronous with the beam to provide bunch by bunch data; this synchronization is provided through the optical link. The back-end system manages the downstream link speed to be on synch with the LHC/SPS 40 MHz clock, this makes the downlink to follow the frequency variations during the accelerators ramp. The acquisition on the front-end will use the recovered 40 MHz clock from the link, therefore deterministic latency and clock phase is needed.
The Igloo2 implementation splits the frames in 6 words of 20 bits, the word clock frequency is 240MHz. On the front-end, the received word clock (rx word clk) locks on the bit stream, leading to 20 different possible phases over its period, corresponding to each bit of a word. These possible -7 - phases for locking produce a displacement on the bits of the received frame (Rx BitSlipNumber), recognised and corrected by the system header checker. The recovery of LHC/SPS 40MHz clock, from rx word clk, on the front-end with deterministic phase is reached by using the frame header detection. The rising edge is triggered with the detection of the word containing the header. Later, the phase is adjusted according Rx BitSlipNumber to compensate uncertainty of the 20 possible locking phases of rx word clk. This phase adjustment is reached through delay lines on the Igloo2 clock conditioning circuit. Several tests were done on a couple of Igloo2 kits to characterize the clock recovery performance and latency.
Link latency: the time required for a control signal to travel from the Back-End to being recognised on the Front-End was analysed. Figure 7 left shows that the link latency has a good correlation with Rx BitSlipNumber. The test determined a link latency uncertainty ±0.7ns.
LHC/SPS Clock phase recovery: the 40MHz clock phase difference between back-end clock (reference for the link) and recovered clock on the front-end (aligned) was studied. The tests showed an uncertainty on phase recovery around ±0.055π rad, which means ±2.8% of uncertainty for the 40 MHz clock (see figure 7 right). This is also correlated with Rx BitSlipNumber.
Link Stability during acceleration ramp: during ramp, the LHC and SPS clock frequencies will vary up to 2.5ppm and 800ppm respectively for protons. To emulate the link frequency variations during the ramp, the back-end board reference clock was changed from the nominal frequency up to an offset of 8000ppm. During the test, the link remained stable, and very few errors on data were observed. However, further investigations are needed to characterise the link behaviour during the acceleration ramp.

Front-End prototype development
For proof-of-concept, three printed circuit boards will be used, a motherboard will drive the optical link, and two mezzanine boards, one per ASIC, will digitalize the pCVD signal. This modular system allows exchanging boards and re-using resources, saving time.

Igloo2 UMd Mezzanine
The Igloo2 UMd Mezzanine board, developed by CMS for the HCAL upgrade [16] (see figure 8 left), has been designed to emulate the GBTx ASIC by using the GBT-On-Igloo2 firmware. This radiation-hard board contains all the needed components to drive the GBT optical link trough an Igloo2, offering a direct connection with the Rad-Hard VTRx module and standard SFP+ modules. The board can be interfaced using LVDS pairs through its 240 pins Samtec high speed connector and needs to be powered externally with 2.5 and 3.3V.

QIE10p5 Mezzanine board
Two parallel QIE10 channels are placed on the mezzanine board to be used for extended dynamic range coverage or redundancy (see figure 8 right). The board has been designed to be interfaced with the Igloo2 UMd board through its mating Samtec connector, providing the external 2.5 and 3.3v needed. The board has been developed with COTS components characterized under radiation. Programmable delay lines have been included to tune the acquisition 40MHz clock in order to match properly the clock phase (integration window) to the incoming pCVD bunch signals.

ICECAL V3 Mezzanine Board
This board is designed following the same strategy as the QIE10, sharing the same connector, linear regulators and LVDS drivers/receivers. In this case only one ICECAL ASIC is installed and its four channels will be used, reaching our required 1e6 dynamic range. The analogue signals from ICECAL will be sampled with Rad-Tol ADCs.

Conclusion
Different aspects of the acquisition system design have been studied to select an architecture that fits our specifications. For the secondary shower acquisition system, a front-end/back-end architecture with pCVD diamond detector will be used. The signal digitalization will be performed in the tunnel and digital communication through the GBT optical link will be used for data transmission, control signals and synchronization. For the first front-end prototype, the digital link will be managed by a flash Based FPGA (Igloo2). The firmware implementation has been validated for the systems and -9 -the initial prototype is in the design phase for proof-of concept evaluation. Regarding back-end systems, VFC boards, designed by BI, are planned to be used.