The VFAT3-Comm-Port: a complete communication port for front-end ASICs intended for use within the high luminosity radiation environments of the LHC

This paper presents the VFAT3 Comm-Port (V3CP), which offers a single port for all communication to and from a front-end ASIC within the HL-LHC environment. This includes synchronization to the LHC clock, slow control communication, the execution of fast control commands and the readout of data.

. The connection between the VFAT3 chip and the GBTX chip in the CMS GEM Data-acquisition system [6].
• Removes the need for an additional slow control interface such as I 2 C. This in itself removes the need for an addition slow control path on the board and its interface chip, simplifying the system design.
• Much faster Slow-Control communication, which is useful for system set-up and calibration processes.
2 General architecture

Basic principle
The V3CP is designed to operate with the e-links running at 320 Mbps. 320 Mbps allows the use of 8 bit serial codes to be delivered to chip, each code representing a particular command per LHC bunch crossing. Figure 2 shows the codes as arbitrary command functions EC0, BC0.. (full list of control commands can be found in section 3.2.1). These codes are decoded to individual command signals synchronous to the LHC machine clock to be acted upon within the chip. For this to happen, frame synchronization of the link must first be achieved. This is done by the detection of comma characters in code sequence which are phase insensitive -they cannot appear in any combination of normal codes. At the same time an internal 40 MHz sampling clock is derived from the 320 MHz clock delivered by the GBTX. It is phase aligned to the LHC clock via the comma character detection. Once synchronization is achieved all the other codes can be detected. Communication with the slow control is done by using two codes, one which represents a logic "zero" to be sent to the slow control block and one which represents a logic "one" (SC0 and SC1). The functions of the V3CP can therefore be summarized as: • Reception of 320 Mbps serial data and synchronization to the 40 MHz LHC clock.
• Detection and decoding of synchronous control commands.
• Separation and prioritized interleaving of data types, detector data and slow control data.
• Transmission of data to the GBTX.
-2 -  The incoming 320 Mbps serial data stream is shifted into a shift register and de-multiplexed into 8 bit words. In addition, a 40 MHz internal clock is derived through division of the 320 MHz clock received on the "Clock" input. Phase alignment to the 40 MHz machine clock is achieved by detection of a 24-bit synchronization pattern which is composed of three consecutive comma characters (CC-A -table 1). After detection of the synchronization pattern, the phase adjustment of the 40 MHz clock starts. The 40 MHz clock is stopped and held for the period of one up to seven clock cycles of the 320 MHz clock. Such a phase synchronization technique makes sure that no glitches would occur in the blocks driven by that clock. The timing relationship for this process is shown in figure 3.

JINST 10 C03019
The synchronization process also provides frame alignment of the incoming data stream such that phase aligned 8 bit words are latched correctly into the 40 MHz domain.
Verification that the internal 40 MHz clock is properly phase aligned is possible via a separate comma character (CC-B). Once the CC-B pattern is recognized, the V3CP checks the phase of the 40 MHz clock. If the clock is synchronized properly V3CP signals that by transmitting the synchronization acknowledge header to the DAQ system.

Encoding/decoding of input data
Typical of most front-end systems is an asymmetry in the bandwidth requirements for the data paths to and from the front-end ASIC. Relatively few commands are required to be transmitted to the front-end ASIC (downlink) whilst maximum bandwidth must obtained in the uplink. Since the GBTX operates with equal bandwidths for both down and up link data, there is a redundancy on the downlink path.
This downlink redundancy can be put to good use by encoding the commands sent to the frontend. The GBTX provides the fixed-latency path. This permits 8 bits to be transmitted per bunch crossing when using the 320 MHz e-link.
The uplink however does not require encoding and the full bandwidth can be exploited. Two different encoding schemes were considered for the V3CP downlink, namely: 7-to-8 bit encoding [7] and 4-to-8bit encoding [8].
The 7-to-8 bit encoding scheme provides one comma character, 128 possible data words and DC balancing.
The 4-to-8 bit encoding provides two comma characters, 16 data words, DC balancing possible and in addition it provides Single-Error-Correction (SEC) and Double-Error-Detection (DED) capabilities.
The number of commands required in the downlink to VFAT3 is less than 16. Therefore, the 4-to-8 bit encoding could be used with the advantage of providing SEC and DED when operating with a 320 MHz e-links as currently foreseen for the GEM system. This encoding scheme hence increases the robustness to input data errors that can appear on the transmission lines and also increases robustness to Single Event Effects (SEEs) after data are latched and processed inside a chip.
Please note, that only the decoding process is implemented in the V3CP. The encoding should be performed in the device which transmits data to the chip. It can be implemented in software, firmware or hardware.

VFAT3 downlink codes
The complete set of downlink codes (FSCCs) is listed in table 2. Idle characters could be A and P which should be sent alternately.

Communication with the Slow Control
The Data Controller handles communication with the Slow Control, the Control Logic and the Data Formatter of the VFAT3 chip. The architecture of V3CP is presented in figure 4.
The user communicates with the Slow Control via the HDLC protocol [9] which sits at a higher level to the encoding/decoding of Fast Synchronous Control Commands. Each "logic 0" -4 -  and "logic 1" of the HDLC protocol is encoded to SC0 and SC1 8 bit codes before transmission to VFAT3. After decoding within the V3CP, the Data Controller routes the SC0 and SC1 bits to the Slow Control unit.
The same is true for the Slow control response in that each bit from the Slow Control unit is encoded to 8 bit SC0 and SC1 codes before transmission from VFAT3. This allows the user to have an effective bandwidth of 40 MHz communication with the Slow Control unit which is significantly faster than the commonly used slow communication protocol of I 2 C.
The VFAT3 Slow Control system allows the Data Controller to perform seamless prioritized interleaving between the different types of data. This is because the HDLC data stream can be interrupted and resumed without any consequence.
There are two different modes of operation controlling the prioritizing of data types; "Run Mode" and "Slow Control Only" (SCOnly) mode. In "Run Mode", tracking data from the Data Formatter has the priority over the data coming from the Slow Control unit. Operation in "Run Mode" is aimed at normal operation. The SCOnly mode, as the name suggests, forces communication to and from the Slow Control unit ignoring data from the Data Formatter. This is the default mode after power-on of the chip.

Transmission of data from V3CP to GBTX
There are two types of data transmitted. These are tracking data, which comprise information on detector channels hit, and Slow Control data. The transmission of data from VFAT3 is through a serial bit stream of 320 Mbps. This bit stream is frame aligned through the use of 8 bit headers. Table 3 shows the list of headers transmitted from VFAT3.
Following the initial chip synchronization procedure a SyncAck header is sent. Frame alignment in the DAQ system can be achieved either by detecting this header or aligning to the filler headers F1 and F2 which are continually transmitted from the chip alternately when there is no other information to transmit.  Headers are also used for the transmission of SC0 and SC1 bits as explained in the previous section.
During "Run Mode" the tracking data has priority. Following "LV1A" triggers, VFAT3 constructs data packets for each trigger within the Data Formatter. The data packets (an illustration of data packet can be found in figure 5) are self contained consisting of a header, tracking data, time tag information and a CRC check code. These data packets are programmable in content and not further explained here. They are transmitted without encoding to allow use of the full bandwidth of the link.

Conclusion
The VFAT3-Comm-Port (V3CP) is a complete communication port, designed to provide bidirectional communication of all data types to and from front-end ASICs, particularly VFAT3. It is designed for operation in demanding radiation environments and to be compatible with the GigaBit Transceiver (GBTX) chip. The port provides a communication protocol which enables synchronization of a chip within a large system and adds robustness against SEEs and SEUs that can occur during transmission. Its specific implementation within VFAT3 allows communication with the Slow Control with an effective bandwidth of 40 Mbps, which can decrease the time that is needed for the chip characterization, system setup and system calibration. For robustness against SEUs and SEEs, the V3CP logic was designed using Triple Module Redundancy.