Power System Harmonic Elimination to Improve Power Quality

An improvised RLC interface filter for a Dynamic Voltage Restorer (DVR) is proposed. The RLC filter is connected in the front end between the IGBT based Voltage Source Inverter (VSI) and the injection transformer and is able to eliminate voltage harmonics in the system and also switching harmonics generated from VSI. The voltage at the sensitive load end is pure sinusoidal. In this method, the DVR produced Pulse Width Modulation (PWM) voltage with voltage harmonic canceling the voltage harmonic generated from the supply main. The VSI handles harmonic power. The low order switching harmonics generated by the IGBT based VSI is suppressed. The DVR has greater voltage injection capability. Good dynamic and transient results recorded and Total Harmonic Distortion (THD) at the sensitive load end is minimized. The voltage at the sensitive load is sinusoidal and at 1.0 pu. PSCAD/EMTDC is used to validate the performance of the interface filter and the DVR. Simulated results are presented.

Current ripple of PWM inverter is reduced with large inductor however, the voltage drop across it is increased [12]. The disadvantages of large inductor are the cost, weight and also increase voltage stress on the inverter switches. Several controller schemes were proposed to control the DVR such as PI controller and park's transformation [13], DVR with Sliding Mode Control [14], Indirect Control of Capacitor Supported DVR [15], instantaneous p-q theory [16], synchronous d-q theory [17] and fuzzy logic controller [18]. Majority of the proposed controller algorithms were based on the Synchronous Rotating Frame Theory (SRFT) or d-q theory while the remaining controllers were too complex to implement as significant computing time was required. It is observed that many researchers addressed the problems of power quality and special attention is given to the voltage sag/swell but few research papers are published on multilevel converters based DVR. The developed controllers are also complex to implement and required more number of components. The total harmonic distortion (THD) of the load side voltage obtained by some research papers is above IEEE-519 Standards. Also the results obtained for the RMS of the load side voltage of some researchers is shown to be lower than the desired level and as there is not much published literature on multilevel based DVR, it is necessary to establish the compensating performance of seven-level cascade multilevel based DVR by proposing new controlling techniques.
This paper proposes an improvised smoothing filter design method with minimum transient current overshoot problem without decreasing the active damping performance of inverter systems. The VSI model is a 7-level H-Bridge as shown in Figure 1. The number of H-bridge cells in a Cascaded H-Bridge (CHB inverter) is determined by the inverter operating voltage, harmonic requirements, and cost. A phase-shifted carrier-based modulation scheme is used for the multilevel inverter. The main advantage of PWM control based DVR control is including fast switching speed of the power switches beside PWM technique offers simplicity and good response and high switching frequencies can be used to improve on the efficiency of the converter without incurring significant switching losses [19]. The basic idea of PWM based multicarrier phase shift modulation technique is varying the ON or OFF switching periods of the IGBTs switches of multilevel converter at a constant frequency so that the ON periods are longest at the peak of the wave. The control of switch duty ratio adjusts the output voltage level. The multilevel inverter with s voltage levels requires (s -1) triangular carriers. In the phase-shifted multicarrier modulation, all the triangular carriers have the same frequency and the same peak-to-peak amplitude, but there is a phase shift between any two adjacent carrier waves, given by θcr = 360°/(s -1). S12 S11 2 2 2 2 S11 S12 2 2 2 2 S14 S13 2 2 2 2 S13 S14 2 2 2 2 S16 S15 2 2 2 2 S15 S16  Phase shifted multicarrier modulation model in PSCAD is shown in Figure 2. The three phase structure of seven level cascaded inverter is illustrated in Figure 1. Each dc source is connected to a three phase inverter. Each inverter level can generate three different voltage outputs, +Vdc, 0, and -Vdc by connecting the dc source to the ac output by different combinations of the four switches. The ac outputs of each of the different full bridge inverter levels are connected in series such that the synthesized voltage waveform is the sum of the inverter outputs. From Figure 2, when switch S15 is at 240 0 , the phase shift of S16 is at 60 0 . Similarly S13 at 120 0 , phase shift of S14 is at 300 0 , S11 is 0 0 and S12 is 180 0 .

RLC FILTER SYSTEM
The single-phase one leg equivalent circuit of an inverter system is shown in Figure 3. From the Figure, Considering and R f is small as compared to L , then the ripple component of the filter inductor current is = (5) and the average value of output voltage is Einv = + R f ix+ L f (6) The capacitor voltage harmonic, with reference to Figure 3; ic = ix-iL (7) Splitting the capacitor and inverter output currents into the average and harmonic components,

LC FILTER VALUES
The reactive power of the LC filter is P rec = (14) where, = 2 and f s is fundamental frequency, and are rms value of the fundamental component of the inductor current and load voltage. The harmonic components is much smaller than the fundamental components and eq. 14 is simplified as P rec = (15) The rms value of the current through the inductor is Splitting the current Ix in terms of real and imaginary, eq. 15 is rewritten as P rec = 2 ] + (16) Capacitance is given as Inductance is given as where, k is the modulation index.
From extensive simulation, the value of R f is selected at 2.0 ohm giving good dynamic performance, actively damps the resonance oscillations, during voltage disturbances. The value of L and C component is determined to minimize the reactive power in these components. From eq. 17 and 18, the capacitance and inductance values are 75 μF and 0.09 mH, respectively for this model. In this proposed control strategy as shown in Figure 4, the synchronous angular frequency of the supply voltage is detected by using phase locked loop (PLL). The generated reference angular frequency is used to generate the zero sequence component of the system voltage based on eq. 19.

PROPOSED CONTROL SCHEME
By applying the inverse of the park transformation under consideration of (V d = 0, V q = V Smax , V 0 = V zero sequence ), the desired system voltages are generated as shown in (20). Position of d-q vector is shown in Figure 5.
The reference compensation voltages to control DVR are generated by comparing the calculated desired system voltages in (20) and the measured load side voltages, and then the error signals are subjected to a phase shift multicarrier PWM controller in order to determine the desired switching pattern for the IGBTs of DVR.

RESULTS AND DISCUSSION
The model is connected to three-phase at 415 V, 50 Hz, power source, as shown in Figure 6. The sensitive load is three-phase R-L circuit rated at (R = 8.0 ohms, L = 0.05 mH) with a parallel connected 3-phase diode bridge rectifier series with a 0.9 mH reactance, as nonlinear load. Voltage harmonics distortion is introduced when a three-phase diode Bridge rectifier is connected at the main supply.

Compensation of voltage harmonics
Voltage harmonics is initiated at the source side between (t = 0ms to 300ms), distorting both source and voltage at sensitive load as presented in Figure 7. THD level recorded at source side is 12.56 %. Figure 7 also shows voltage at the sensitive load and the injected voltage by DVR.
As can be seen from Figure 7, the proposed DVR is able to inject the appropriate three-phase voltage component to correct the supply voltage anomalies due to three-phase harmonic distortion. Under normal operation the DVR is doing nothing. It quickly injects the necessary voltage components to smoothen the load voltage upon detecting voltage harmonics. The load voltage waveform is sinusoidal maintained at 1.0 pu. The source and load current waveform is shown in Figure 8. As seen from the figure, the load current is compensated and is sinusoidal. When the DVR is connected, the voltage THD is considerably reduced from 12.56 % to 1.793 % at sensitive load end as shown in Figure 9. This is a significant improvement. The system parameters used in the model are shown in Table 1.

CONCLUSION
This project presents a new model of DVR based Seven-level cased multilevel converter and, the controller. The simulation results show that voltage imperfection mitigation, and the enhancement of voltage stability has been achieved. The performance comparison of the proposed DVR and its controller with some previously reported DVR modules shows that it is more efficient in terms of cost, component, power consumption and losses. It is also found that the absolute beneficial of DVR can be achieved with connection of the distributed generation sources such as solar cells, wind generation system etc in the DC side of the proposed DVR model. The simulation results have demonstrated excellent suppression of voltage harmonic capabilities of DVR using the proposed new RLC filter carrier based PWM technique. The DVR is an attractive custom power device for power quality improvement specifically to suppress voltage harmonics and also to mitigate voltage sag and combination both as a hybrid unit.