Approximate analytical channel potential model of poly-Si thin film transistors operated in the strong inversion region under the high gate and low drain biases

An approximate analytical channel potential model of polycrystalline silicon thin film transistors operated in the strong inversion region under the high gate and low drain biases is proposed. Thus, the linear relationship between the channel potential and the drain voltage is derived in the strong inversion region under the above bias condition when the polysilicon layer is ultrathin. This model agrees with the two-dimensional-device simulation results under different gate voltages, different drain voltages and different channel lengths. By comparing the relative errors between the model and the simulation results, it presents that this model is more suitable under the higher gate voltage Vg or the lower drain voltage Vd, regardless of the channel length. And this approximate analytical model is helpful in solving the two- dimensional-device problem by one-dimensional Poisson's equation since the drain bias is taken into account in the channel potential.


Introduction
In recent years, polycrystalline silicon thin film transistors (poly-Si TFTs) have been the essential electronic devices in flat panel displays (FPDs) [1]. For their applications, an indispensable circuit simulation is a key issue for their large scale circuitry. As a result, an accurate and efficient compact model of the poly-Si TFTs is required in the simulation. The surface-potential-based model structure is a choice for the new generation compact MOSFET models and the approach is recognized as both the most physical and the most difficult to implement. In the surface-potential-based models, the key issue is the calculation of the surface potential.
In order to calculate the surface potential, if we start from the basic Poisson's equation, the carrier density is needed. In order to well characterize it, the distribution of the channel potential, which is defined as bulk-referenced quasi-Fermi potential, is required. However, there are few discussions about the model of the channel potential. Or just a given value is assigned to the channel potential without discussing its dependence on the applied biases and the device structure parameters [2][3][4]. And if the channel potential is arbitrarily given, the relevant model is essentially a one-dimensional analysis. In this paper, an approximate analytical channel potential model of poly-Si TFTs with the ultrathin polysilicon layer in the strong inversion region under the high gate and low drain biases is presented and is verified by the two-dimensional-device simulator MEDICI under various gate voltages, drain voltages and channel lengths. It is helpful in solving the two-dimensional-device problem by onedimensional Poisson's equation since the drain bias is taken into account in the channel potential.

Model formulation
In the vicinity of the surface, for n-type poly-Si TFTs, the channel potential ( ) Fermi potential at the bulk [5].
According to the previous work [6], for n-type poly-Si TFTs with the ultrathin polysilicon layer, the drain current can be expressed as: where ds I is the drain current, W is the channel width, s μ is the surface mobility, q is the electron charge, Aa N is the active acceptor concentration, channel t is assumed as ε is the silicon permittivity, T N is the acceptor type grain-boundary surface state (areal) density, g L is the grain size, t E is the energy level difference between the trap level and the intrinsic level, t φ is the thermal voltage, ox C is the unit gate oxide capacitance, g V is the gate voltage, fb V is the flat band voltage.
Meanwhile, in the strong inversion region, the first-order approximation of the surface potential is where V c is equal to 0 V and the drain bias V d at the source and drain electrode, respectively [7]. So when in the strong inversion region under the high gate and low drain biases, in the integrand of (1), all terms related to s Ψ become neglectable compared with that with V g . So the integrand of (1) can be determined by the term with V g . And it is almost constant depending on V g . Therefore, (1) can be approximately rewritten as At y=L, With (2) and (3), the approximate analytical channel potential model is derived.

Result and discussion
The approximate analytical channel potential model of poly-Si TFTs in the strong inversion region under the high gate and low drain biases has been compared with the two-dimensional-device Since the source side is biased at 0 V, the quasi-Fermi potential at the source electrode, which equals to the bulk Fermi potential, is equal to 0 V. Therefore, the electron quasi-Fermi potential in the MEDICI is the same as the channel potential in this paper.
In figure 1, the correlation of the channel potential with the relative position (y/L) in the channel is shown under the various gate voltage V g = 15 V, 20 V and 30 V while the drain voltage V d = 1 V and the channel length L= 10 μm. And the model presents the well agreement with the simulation results. Moreover, since the term with the gate voltage plays a more important role in (1) under the higher gate bias, the model agrees with the simulation better.
In figure 2, the correlation of the channel potential with the relative position in the channel is shown under the different V d = 0.1 V, 0.5 V and 1 V while V g = 15 V and L= 10 μm. The model presents the well agreement with the simulation results. Furthermore, the smaller drain bias is, the more excellent agreement it achieves since the term related to s Ψ in (1) turns to be less.
In figure 3, the correlation of the channel potential with the relative position in the channel is shown under the various L= 5 μm, 10 μm and 25 μm while V g = 30 V, V d = 1 V. The model presents the well agreement with the simulation results and is less affected by the different channel lengths.
In order to have an explicit insight on the differences between the model and the simulation results, the relative errors are compared under the different V g , V d and L in figure 4. In figure 4 (a), the relative error decreases to 2% under the higher gate voltage V g = 30 V. The relative error is within about 2% under the lower drain voltage V d = 0.1 V shown in figure 4 (b). And no obvious differences can be found in various channel lengths in figure 4 (c). It can be concluded that under the higher V g and lower V d , this approximate analytical model (4) can better depict the channel potential along the channel, regardless of the channel length.

Conclusion
The approximate analytical channel potential model of poly-Si TFTs with the ultrathin polysilicon layer in the strong inversion region under the high gate and low drain biases is obtained. The channel potential shows a linear dependence on the drain bias with the ratio factor y/L. Compared with the two-dimensional-device simulation results, this model is proved under different gate voltages, drain voltages and channel lengths. And the relative error decreases to about 2% under the higher gate voltage and the lower drain voltage respectively and is less affected by the different channel lengths. It presents that this model is more suitable under the higher V g and lower V d , regardless of the channel length. And this approximate analytical model is helpful in solving the two-dimensional-device problem by one-dimensional Poisson's equation since the drain bias is taken into account in the channel potential.