Influence of a SiN Drift-Barrier on the Charge Decay in Parylene-C Electret Layers

This paper reports on the attempt to improve the charge carrier life time in Parylene-C electret layers by implementing a drift barrier layer close to the surface. The barrier layer is intended to avoid the rapid discharge by ionic drift through the electret layer. For this purpose, we fabricated test chips comprising silicon nitride drift barriers with thicknesses of 50nm, 100nm and 200 nm sandwiched between a 7.1-μm-thick Parylene-C base layer and capping Parylene-C electret layers of three thicknesses, charged using the corona discharge method. Experimentally, it turns out that there is no pronounced influence on the charging process due to the drift barrier. Surface potential measurements were repeated over a period of 20days. Up to t = 10days a weak improvement of the remaining surface potential can be interpreted into the data. However, thereafter the surface potentials decrease rapidly. Surface potential line scans over the samples show that the decreased width of the charge carrier distribution, likely due to an enhanced horizontal drift or diffusion, is the reason. This effect is not observed on charged Parylene-C layers without drift barrier.