Abstract
The ATLAS Cathode Strip Chamber system consists of two end-caps with 16 chambers each. The CSC Readout Drivers (RODs) are purpose-built boards encapsulating 13 DSPs and around 40 FPGAs. The principal responsibility of each ROD is for the extraction of data from two chambers at a maximum trigger rate of 75 KHz. In addition, each ROD is in charge of the setup, control and monitoring of the on-detector electronics. This paper introduces the design of the CSC ROD software. The main features of this design include an event flow schema that decentralizes the different dataflow streams, which can thus operate asynchronously at its own natural rate; an event building mechanism that associates data transferred by the asynchronous streams belonging to the same event; and a sparcification algorithm that discards uninteresting events and thus reduces the data occupancy volume. The time constraints imposed by the trigger rate have made paramount the use of optimization techniques such as the curiously recurrent template pattern and the programming of critical code in assembly language. The behaviour of the CSC RODs has been characterized in order to validate its performance.
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