High-performance, micromachined GaN-on-Si high-electron-mobility transistor with backside diamondlike carbon/titanium heat-dissipation layer

Owing to its high breakdown voltage, high saturation drain current, and low ON-resistance (R_ON), the AlGaN/GaN-based high-electron-mobility transistor (HEMT) is considered to be an excellent candidate for next-generation power devices.^1,2) Based on these properties, GaN-based power converters enable more efficient and compact power-conversion systems than the conventional Si-based converters. For practical usage in industry, GaN-on-Si HEMTs have been studied and evaluated according to reliability testing and the mechanism of failure modes.³⁾ However, GaN-on-Si power HEMTs generate a considerable amount of heat during high-current operation, and the device reliability depends directly on the maximum operating temperature. The device performance continues to suffer from other limitations, such as power-conversion efficiency in high-current levels and poor thermal conductivity of the Si substrate compared to a SiC substrate. In order to dissipate surface heat during operation, Tadjer et al. proposed a low self-heating device that incorporates GaN on the HEMT, along with nanocrystal diamond capping layers grown prior to gate deposition.⁴⁾ In this study, a micromachined AlGaN/GaN power HEMT (M-HEMT) on a Si substrate with a diamondlike carbon (DLC) heat-dissipation layer design is proposed. DLC layers provide excellent thermal conductivity [600 W/(m K)], and their coefficient of thermal expansion (CTE) value is similar to that of GaN.⁵⁾ Therefore, the insulator between the GaN and the backside heat-dissipation layer, which was utilized in the device from our previous study, can be avoided.⁶⁾ Based on the wafer bending evaluation, the current density of the micromachined device with backside DLC layers was less influenced by the 0.01% substrate bending strain, owing to the similar CTE between GaN/Ti/DLC. In addition, the self-heating phenomenon was also improved for our proposed device due to the 1.5 µm back DLC layer design, which provided superior thermal conductivity.

The photograph and the scanning electron microscope (SEM) cross-sectional view of the AlGaN/GaN M-HEMT on Si substrate with backside DLC/Ti layers are shown in Fig. 1. A 2-µm-thick AlGaN/GaN composited buffer was first grown by MOCVD on a 4-in. 625-µm-thick, p-type (111) Si wafer. A 1-µm-thick, undoped GaN channel layer was grown on top of a buffer layer, and an 18-nm-thick, undoped Al_0.27Ga_0.73N Schottky layer was sandwiched between the GaN channel layer and the 1 nm, undoped GaN cap layer. Device processing started with the device isolation using the BCl₃ + Cl₂ mixed gas plasma to form a 300-nm-depth mesa region in a reactive ion etching (RIE) chamber. Ohmic contacts were prepared by electron beam evaporation of a multilayered Ti/Al/Ni/Au (with thicknesses of 30, 125, 50, and 200 nm, respectively) sequence, followed by rapid thermal annealing at 850 °C for 30 s in a nitrogen-rich environment. As a first passivation layer for the field-plate gate process, a 100-nm-thick SiO₂ layer was deposited on the HEMT surface, using plasma-enhanced chemical vapor deposition at 280 °C. The 3-µm-long, T-shaped field-plate gate was evaporated on a 2-µm-long SiO₂ removed gate fingers pattern. For the power cell design, the air-bridged matrix (ABM) heat-distribution layout was adopted, and the device gate was zigzagged along with the inter-digital drain/source spacing.⁶⁾ Regarding the power device geometry, the gate length was 2 µm, with an active region area of 1.25 × 1.25 mm² for both standard and M-HEMT devices. The total gate width of the M-HEMT device was 22.8 mm, compared to the value of 40 mm (1.25 mm/finger, 32 fingers) for standard devices. After the completion of the front-side fabrication, the Si substrate was thinned down to 100 µm. At this point, the Si substrate beneath the active region was removed by SF₆ plasma etching, thereby exposing the N-face buffer layer. The partial GaN transition layer was also removed by BCl₃ + Cl₂ mixed gas plasma. An air-bridged 5 × 5 matrix power device with micromachined Si substrate removal is shown in Fig. 1(b). The Si substrate beneath the pad was retained for the convenience of wire bond or flip-chip packages. Finally, the DLC/Ti materials were deposited on the backside of 4 in. Si substrate as a heat-dissipating layer.

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The metal-hydrocarbon target in this study was tungsten carbide. The DLC film coating was prepared by reactive DC magnetron sputtering with high-temperature chamber design. Based on the material characteristics shown Fig. 1(c), the DLC layers can perform as an effective heat-dissipation enhancer; moreover, the DLC material exhibits a similar thermal expansion coefficient to that of GaN. The deposition rate of DLC film was around 1 Å/s. The thickness of the Ti layer was 200 nm, which was beneficial for increasing the film adhesion and electrical conductivity of the DLC/Ti heat-dissipating layer. To ensure efficient heat dissipation, the total thickness of the DLC layer should be more than 1 µm. Therefore, after considering the strain effect and heat-dissipation effect in concert with each other, two pairs of DLC/Ti (with thicknesses of 200 and 550 nm, respectively) composite layers were employed. The measured CTE of DLC/Ti was increased to 7 ppm/°C. The interface quality and adhesion of the DLC/Ti composite layer shown in Fig. 1(e) were reliable.

The three-terminal breakdown voltages (V_BR) of the devices shown in Fig. 2 were measured using an Agilent B1505A measurement system, with the samples being immersed in an inert liquid (Fluorinert FC-43) to prevent surface flashover. In this study, V_BR is defined as the voltage at which a drain leakage current between the drain and the source terminals reaches 1 mA/mm at a V_GS of −8 V. The two-terminal buffer breakdown voltage was also measured on structures where source and drain contacts were isolated by 300 nm mesa plasma etching, as shown in the inset figure of Fig. 2. Based on the inset figure, the buffer breakdown voltage of the devices on the Si substrate saturates around 1100 V. This value can be further enhanced to 1400 V in M-HEMT with DLC layer design, which evidences the fact that the Si substrate is the limiting factor for the maximum breakdown voltage of the GaN-on-Si HEMT. As to the device off-state breakdown voltage, the drain (I_D) leakage current of a standard GaN HEMT increases rapidly following an increase of V_DS (V_GS = −8 V), and its V_BR is 450 V. As can be seen, the drain-to-source leakage through the buffer is one order of magnitude lower in M-HEMT than that in standard HEMT; therefore, the impact of the ionization-induced breakdown mechanism can be slightly suppressed to improve the V_BR of M-HEMT with DLC layer design to 637 V.

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Figure 3 displays I_DS and g_m data with respect to V_GS for both devices, with an identical active region (1.25 × 1.25 mm²). An obvious current-improving phenomenon is observed for M-HEMT with DLC layers due to the air-bridge matrix structure. Additionally, it is evident that the backside DLC film dissipated the junction heat rapidly, especially at high gate-voltage operation. The threshold voltage of both devices is −2.3 V; however, the saturated I_DS is 2.18 A for standard HEMT, but increases to 4.97 A for M-HEMT with DLC layers. Figure 3 also shows the I_DS and g_m characteristics of the standard devices, along with those of M-HEMTs with DLC layers, obtained on flat and bending conditions (strain: 0.01%).⁷⁾ Under this strain condition, the maximum I_DS of the standard device exhibited a 30% reduction, which can be explained as the result of thermal effects and the change of lattice strain. The Si substrate beneath the GaN active region was removed for the M-HEMT device. Therefore, the strain is extremely small for thin 3 µm GaN film (buffer layer included), because the strain force from 100 µm Si was disappeared. In addition, the CTE value was similar for DLC and GaN; therefore, for M-HEMT with DLC layer design, the current degradation was only 5% because the strain induced polarization variation was slight in the GaN/Ti/DLC structure.⁸⁾

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The GaN switching power transistor is expected to be useful for high-temperature power electronics, which often refers to operation temperatures of approximately 200 °C. In order to further illustrate the thermal dissipation improvement of the M-HEMT with DLC heat-distribution layers, Fig. 4 shows the R_ON characteristics for both devices from room temperature (25 °C) to 200 °C. The slope of R_ON versus temperatures was 2.77 mΩ/°C for standard HEMT and 1.51 mΩ/°C for HEMT with backside, 1.5-µm-thick, DLC/Ti composite layers. An apparently stable thermal performance can be found in M-HEMT with DLC heat-distribution layers due to the immediate dispersal of heat by the DLC backside layers, which improved the channel mobility caused by temperature induced phonon scattering.

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To measure the surface temperature distribution within the HEMT, an infrared (IR) thermographic system with micro-Raman spectroscopy was utilized, and the IR radiation of the device was probed using a Neo Thermal TVS-700 detector. The surface temperature map was obtained from the IR-radiation intensity following emissivity calibration, which was performed for the unpowered device at various I_DS. For the thermal image testing, the devices were mounted on a copper plate for thermal dissipated consideration. As shown in Fig. 5, the standard power HEMT (multi-finger layer, 100 µm Si substrate thickness) exhibited a peak surface temperature of 172.3 °C under I_DS = 1 A and V_DS = 10 V bias conditions. In addition, the surface temperature distribution is not uniform, which immediately causes issues relating to hot spot reliability. The surface temperature was reduced to 125 °C in the ABM power HEMT, owing to its 3-µm-thick Au air-bridge thermal-redistribution layer; however, it still remains difficult to dissipate the heat stored in the 100 µm Si substrate. For M-HEMTs with DLC layer design, the lowest surface temperature can be obtained; moreover, the surface temperature distribution is comparatively uniform, owing to the high thermal conductivity of the DLC/Ti composite layer.

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The dynamic R_ON transient measurement methodology, which allows the observation of R_ON transients after a switching event, was measured for the standard HEMT, M-HEMT without DLC layers, and M-HEMT with DLC layers. The dynamic switching performance was determined by calculating the ratio of dynamic R_ON to DC R_ON (R_DC). The value of dynamic R_ON was obtained under test conditions in which V_DS,test and V_GS,test were respectively set to 1 and 0 V after applying the OFF-state stress. The devices under test were stressed in high V_DS OFF-state (V_DS,stress) for 1 s, then synchronous switching V_GS and V_DS to the test condition by an Agilent B1505 power device analyzer. The value of R_DC was obtained under test conditions in which V_DS and V_GS were respectively set at 1 and 0 V without applying the OFF-state stress. Figure 6 shows the dynamic switching results of the R_ON transients for various HEMTs under the V_DS,stress of 200 V. For the standard HEMT, the dynamic R_ON/R_DC ratio was higher than that of the micromachined HEMTs because the carriers' switching behavior was limited by a deep-level capture mechanism caused by the buffer/transition layer traps. Moreover, the 100 µm Si substrate of the standard HEMT also generated a parasitic effect, leading to its carriers' relaxation corner time of 0.05 ms. With micromachined through substrate via hole technology, the device carriers' relaxation corner time can be reduced to 0.03 ms. By comparing the dynamic R_ON/R_DC ratio of M-HEMTs with and without DLC thermal dissipation layers, it is clear that the recovery behaviors of M-HEMTs with DLC layer can be slightly improved due to the reduction of device thermal resistance, which is beneficial for relaxing and conducting the carriers at ON-state operation.⁹⁾

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In summary, the temperature-dependent performance of standard AlGaN/GaN power HEMTs and M-HEMTs with DLC layers was evaluated. The thermal performance of both devices was studied using electrical DC characterization and IR thermography measurement. The M-HEMTs with DLC layers exhibited the better thermal stability because their device characteristics were less influenced by temperature, owing to superior thermal conductivity. Additionally, the M-HEMTs with DLC layers better retained the device characteristics under wafer bending strain evaluation, because the CTE values of DLC and GaN are significantly similar. Based on the dynamic switching transient measurement, the micromachined through substrate via technology and DLC dissipation design are beneficial for improving the device's dynamic R_ON/R_DC ratio and carriers' relaxation corner time. The superior thermal stability and resistance to bending-induced degradation make it clear that DCL/Ti composite layers exhibit great potential in power device applications.

Acknowledgments