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Performance evaluation of multiple (32 channels) sub-nanosecond TDC implemented in low-cost FPGA

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Published 10 March 2014 © CERN 2014
, , Citation P Lichard et al 2014 JINST 9 C03013 DOI 10.1088/1748-0221/9/03/C03013

1748-0221/9/03/C03013

Abstract

NA62 experiment Straw tracker frontend board serves as a gas-tight detector cover and integrates two CARIOCA chips, a low cost FPGA (Cyclon III, Altera) and a set of 400Mbit/s links to the backend. The FPGA houses 16 pairs of sub-nanosecond resolution TDCs with derandomizers and an output link serializer. Evaluation methods, including simulations, and performance results of the system in the lab and on a detector prototype are presented.

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10.1088/1748-0221/9/03/C03013