Abstract
The radiation response of a 0.25 μm silicon-on-sapphire CMOS technology is characterized at the transistor and circuit levels utilizing both standard and enclosed layout devices. The threshold-voltage shift is less than 170 mV and the leakage-current increase is less than 1 nA for individual standard-layout nMOSFET and pMOSFET devices at a total dose of 100 krad(SiO2). The increase in power supply current at the circuit level was less than 5%, consistent with the small change in off-state transistor leakage current. The technology exhibits good characteristics for use in the electronics of the ATLAS experiment at the Large Hadron Collider.