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Journal of Instrumentation Volume 3 March 2008 Create an alert RSS this journal

M Dahoumane et al 2008 JINST 3 P03002 doi:10.1088/1748-0221/3/03/P03002

A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for Monolithic Active Pixel Sensors

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M Dahoumane1,2, D Dzahini1, J Bouvier1, E Lagorio1, L Gallin-Martel1, J Y Hostachy1, O Rossetto1, Y Hu2, H Ghazlane3 and D Dallet4

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Abstract References Cited By
A 4 bit very low power and low incoming signal analog to digital converter (ADC) using a double sampling switched capacitor technique, designed for use in CMOS monolithic active pixels sensor readout, has been implemented in 0.35μm CMOS technology. A non-resetting sample and hold stage is integrated to amplify the incoming signal by 4. This first stage compensates both the amplifier offset effect and the input common mode voltage fluctuations. The converter is composed of a 2.5 bit pipeline stage followed by a 2 bit flash stage. This prototype consists of 4 ADC double-channels; each one is sampling at 50MS/s and dissipates only 2.6mW at 3.3V supply voltage. A bias pulsing stage is integrated in the circuit. Therefore, the analog part is switched OFF or ON in less than 1μs. The size for the layout is 80μm*0.9mm. This corresponds to the pitch of 4 pixel columns, each one is 20μm wide.

Keywords

Front-end electronics for detector readout

VLSI circuits

Analogue electronic circuits

PACS

84.30.Sk Pulse and digital circuits

84.32.Tt Capacitors

07.07.Df Sensors (chemical, optical, electrical, movement, gas, etc.); remote sensing

85.30.Tv Field effect devices

85.40.-e Microelectronics: LSI, VLSI, ULSI; integrated circuit fabrication technology

Subjects

Electronics and devices

Semiconductors

Instrumentation and measurement

Dates

Issue 03 (March 2008)

Received 25 October 2007, accepted for publication 20 February 2008

Published 11 March 2008



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