Q Liu et al 2006 J. Phys.: Conf. Ser. 43 1171 doi:10.1088/1742-6596/43/1/285
Q Liu1, T Van Duzer1, K Fujiwara1,2 and N Yoshikawa2
Show affiliationsRecent progress on demonstrating components of the 64 kb Josephson-CMOS hybrid memory has encouraged exploration of the advancement possible with use of advanced technologies for both the Josephson and CMOS parts of the memory, as well as considerations of the effect of memory size on access time and power dissipation. The simulations to be reported depend on the use of an approximate model for 90 nm CMOS at 4 K. This model is an extension of the one we developed for 0.25 µm CMOS and have already verified. For the Josephson parts, we have chosen 20 kA/cm2 technology, which was recently demonstrated. The calculations show that power dissipation and access time increase rather slowly with increasing size of the memory.
85.25.Hv Superconducting logic elements and memory devices; microelectronic circuits
Issue 1 (2006)
Q Liu et al 2006 J. Phys.: Conf. Ser. 43 1171
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