A nanomechanical computer—exploring new avenues of computing

Robert H Blick¹, Hua Qin, Hyun-Seok Kim and Robert Marsland

Electrical and Computer Engineering, University of Wisconsin-Madison, 1415 Engineering Drive, Madison, WI 53706, USA

¹ Author to whom any correspondence should be addressed.

Email: blick@engr.wisc.edu

Received 19 May 2007
Published 24 July 2007

Contents

• 1. Introduction
• 2. Logic elements
• 3. Memory
• 4. Power
• Acknowledgments
• References

1. Introduction

Power dissipation in highly integrated circuits turns out to be a major concern for the semiconductor industry as well as for energy producers. The US wide power consumption by computers reaches about 20% of the total energy provided and is rising [1]. On a more fundamental level the question is what the actual limit for energy dissipation is without compromising data integrity. An early estimate was performed by Landauer [2], whose extrapolation sets the energy consumed by a single gate operation to reach the fundamental energy of k_BT of around 10 zeptoJoule by 2015, where k_B is the Boltzmann constant and the temperature is assumed to be 300 K. The main point in Landauer's paper was that if this temperature limit is reached, one would have to consider Carnot-efficient computing, i.e. `reversible computing becomes significant' [2]. In other words new approaches to computing will have to be found, which reduce the overall power dissipated and which finally might allow reversible computing. Here, we offer a possible solution for reducing dynamic power dissipation in the first place by using nanomechanical devices for building computational elements. This approach might also have potential for reversible computing, if one makes use of the thermal energy of the environment.

It has to be clearly stated that current operating speeds of nano-electromechanical single electron transistors (NEMSETs) are of the order of 1 GHz [3], which is not competitive with standard complimentary metal oxide semiconductors (CMOS). However, this is sufficient for many families of micro-processors, which are used for a broad range of mundane tasks. A nanomechanical computer (NMC) will not address the issue of clock-speed (which actually enhances dissipation), but will be most effective for micro-processor applications which demand robustness, low power consumption and high-temperature applications (T  >  200°C). Finally, it needs to be added that an NMC can be realized in silicon substrates and naturally allows for combining with traditional CMOS circuitry. Hence, we are able to offer a new principle for computational tasks, which is compatible with existing technology.

Based on ultra-hard materials such as diamond, which can be doped and processed straightforwardly, such an NMC can withstand extreme temperatures. The operating temperature can be as high as 500°C. This is of great interest for space-born operation and other harsh environments or when the available power is limited. We estimate that operation with externally applied dc voltages is feasible. These voltages can be generated either by a battery or by a manually actuated battery charger. Another possible energy supply for the NMC can be found in mechanically actuating the supporting substrate either by an acoustic transducer (quartz) or by relying on the thermal lattice vibrations. The NMC thus might constitute the first step towards a Carnot-efficient computing device.

As we have found in recent measurements [4] self-excitation can be exploited to generate mechanical oscillations without any ac excitation. Hence, dc voltages are sufficient to operate the NMC. Basically, a dc voltage creates an electric field to support mechanical oscillations of the nanopillars. A classical example is straightforward to construct [5]. It has to be noted that onset of the mechanical oscillations is induced by a thermal fluctuation, which is found to be enhanced, if the electrical field is inhomogeneous.

2. Logic elements

In order to construct an NMC we need to have the following logic element implemented: the NEMSET. To the earlier work we have to add that we recently were able to demonstrate field emission (FE) in these devices [6]. This enhances the current level by an order of magnitude—see figure 1 for an example of a NEMSET of the current generation. Standard NEMSET configurations are realized in silicon-on-insulator (SOI) substrate with gold contacts added by thermal evaporation. The circuit in figure 1 was defined by using electron-beam lithography, however, standard industry optical lithography now realizes feature sizes of 90 nm by UV-light. Hence, an integrated nanomechanical circuit can be fabricated via inexpensive optical lithography. Other methods, such as nanoimprint lithography with proven feature sizes of only 20 nm, can be applied for large-scale integration. The latter point should especially be important, considering that for the most simple NMC only a single metallic top layer will be required, i.e. all transistor functions should be defined in one litho-step and then transferred into the supporting material (SOI, SSOI, SGOI, GOI, GaAs, AlGaAs and diamond) via dry-etching techniques.

In figure 2, a typical measurement of current versus applied radio frequency on a single NEMSET is shown for a variety of bias voltages. We find two mechanical resonances around 150 and 240 MHz. The inset shows the IV-characteristics for ON- and OFF-mechanical resonance cases. Due to the simultaneously applied ac voltage the threshold for current flow is very low. This is an indication that dc or ac voltages below 1 V will be sufficient for operating the NMC [4] and hence the overall power required can be further reduced. It should be noted that pure dc excitation is preferable for operating an NMC with a large number of logic gates.

Key to any computing machine are logic elements. These require gain to provide a noise margin. It seems that gain might be achieved in a NEMSET by mechanically coupling two sets of pillars. One set, the input set, puts the output set in motion. Gain is achieved if the input set consumes less charge than the output set delivers to the load. This is implemented when the input set contains fewer pillars or if each pillar transfers less charge than a pillar in the output set. The two sets have independent source and drain connections. This provides isolation between input and output and allows for logic restoration.

We constructed a simple model to explore how such a gate can work. If we assume that charge transfer in the NEMSET takes place only during the brief time that the pillar is closest to the source or drain, we can model the NEMSET as a switched-capacitor network with low duty cycle. There are two extremes to the modes of operation for such a network: the pillar might charge or discharge fully in each contact cycle, or the pillar might charge or discharge only infinitesimally. Assuming the latter situation, the average current flow is given by i_AVE  =  (V_DD/2R_P)(Δt/T) where R_P is the pillar contact resistance, V_DD is the voltage of the power-supply, and Δt/T is the duty cycle: source/pillar or drain/pillar contact time divided by the period of oscillation. The NEMSET can then be modelled as an effective resistance, R_Pe  =  2R_P T/Δt in parallel with the source-drain capacitance. Since R_Pe is only present once oscillation begins, a self-starting oscillator will look purely capacitive until oscillation begins and then R_Pe will appear in parallel. The switched capacitor model and its effective equivalent for low duty cycle areshown in figure 3.

Both the figure 3 models can be used to model more complex NEMSET circuits. We model mechanical self-excitation using a comparator connected across the source and drain.When the voltage reaches the threshold of oscillation, the switches of figure 3 (left) begin to toggle. The figure 3 (right) switch simply switches on when the oscillation threshold is reached. Since the full model requires extremely short contact times, Δt, simulation can be time consuming. The low-duty-cycle equivalent provides for extremely fast simulation.

To model a device with gain, two mechanically coupled NEMSETs are required. In the simplest approximation, the mechanical coupling can be represented through the switch actuation. When the drain–source (D–S) voltage gets large enough to initiate switching in the input set, the output set is made to switch as well. In reality, the amplitude of the oscillation produced by the input set of pillars will critically affect the contact resistance of the pillars in the output set. The simple model only accounts for a fixed contact resistance. The coupled-NEMSET device model using the simplified low-duty-cycle equivalent is shown below in figure 4.

A basic inverter using the coupled NEMSET is shown in figure 5. The bottom device will be on for V_in  >  V_t where V_t is the threshold for mechanical self-excitation. The top device will be on for V_in  <  (V_DD – V_t), where again V_DD is the power-supply voltage. If V_t is around V_DD/2, then the top device is on for V_in up to V_DD/2 at which point the bottom device turns on and the top one turns off. If V_t is less than V_DD/2, there will be a range of voltages where both devices are on and the shape of the transfer curve will be determined by the variation of contact resistance with input voltage which in turn depends on the strength of mechanical excitation of the two gates. More complex gates can be formed by adding series and parallel connected devices as is done in designing CMOS gates (see figure 6).

With the model of figure 5, we can predict how such an inverter would perform when driving N identical inverters (fan-out of N). Since we know that input-current is undesirable, it would be best to form the coupled NEMSETs from two types of pillars: a high-contact-resistance pillar for the input and a low-contact-resistance pillar for the output. However, if all the pillars are identical for ease of processing, the following simple rules will apply. The effective resistance varies inversely with the number of pillars connected in parallel. If R_P is the contact resistance of a single pillar, and R_Pe is the effective resistance of a single pillar, and given L input pillars and M output pillars, the equivalent circuit for the fan-out of N is given by figure 7.

Notice that due to the charge transfer of the NEMSETs, there is a static dc voltage drop given by

to keep the voltage drop at less than 10%, we need M/L  =  9N. So, for a fan-out of 4, we require 36 times more coupled output pillars than coupled input pillars. This ratio could be reduced if the contact resistance of the input pillars was increased relative to the output pillars while maintaining the same mechanical strength of oscillation.

We can also use this model to examine the switching speed. The time constant of the circuit in figure 7 is simply R_Pe C_sd. Assuming we can transfer five electrons per cycle with an oscillation frequency of 1 GHz and 1 V bias, R_Pe can be estimated at 1.25 GΩ, and the estimated pillar capacitance is 10 aF. The resulting time constant is ~12 ns which permits logic toggle ratesover 10 MHz.

3. Memory

The concept of nanomechanical memory can be pushed beyond the conventional logic based on the expression of two states with nanomechanical elements (binary logic) [7]. It can be assumed that a nanomechanical system can have several instead of only two stable positions, which then corresponds to a multi-valued logic. A memory state in the conventional sense can be established with a NEMSET by simply starting from a bistable state, where the NEMSET can fall back into two potential minima. This can be achieved by either a magnetic island on the tip of the NEMSET, which can be spin-polarized, or using a bistable pillar in a three-terminal set-up. An example is a conducting magnetic pillar that can be attracted to either the left or the right electrode of a three-terminal set-up and maintain current flow in each state. A NEMSET thus can resonate between the input and either of the two output signals.

4. Power

The scaling of the power of the nanomechanical circuits we find by applying the standard relation for CMOS dynamic power consumption P  =  CV²f. Assuming an operating frequency of f  =  1 GHz, a typical operating voltage of V  =  1 V and a NEMSET total capacitance of C  =  10 aF, we find a total dynamic power of P  =  10 nW. This value can be further reduced by lowering the gating voltage to some 100 mV and the overall capacitance to below 10 aF. Under the assumption that the gate is switched at a speed of 1 GHz the total power corresponds to an energy of E  =  10 aJ per switching event for nanomechanical transistors. At this stage this is only two orders of magnitude above the thermal energy limit E_th  =  k_BT for 300 K. A computing architecture made from nanomechanical transistors thus is competitive with 45 nm CMOS technology^Note2 , while taking a step towards enabling reversible computing.

In summary, we have shown how to construct a computational device purely based on nanomechanical elements—the NMC. Single nanomechanical switches are operational and simulation shows that the concept is feasible for circuit integration.

Acknowledgments

This work was supported in part by the Air Force RSO (F49620-03-1-0420), the Wisconsin Alumni Research Foundation (WARF), and by the DARPA NEMS program.

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Notes

Note2  Based on an inverter with total n and p-type device width of three times the 45 nm minimum feature size and 8.3 × 10^–16 F μm^–1 total gate capacitance.