Material science and device physics in SiC technology for high-voltage power devices

A micropipe defect is a hollow core associated with a superscrew dislocation.^96,97) The magnitude of the Burgers vector for micropipes has been investigated; the minimum values were found to be |3c| for 4H-SiC and |2c| for 6H-SiC (c: fundamental translation vector along the c-axis),^98,99) both of which correspond to 3 nm. Because a micropipe is a micron- or submicron-size pinhole extending along the 〈0001〉 direction through the entire SiC wafer, it is not surprising that SiC devices that contain a micropipe exhibit severely degraded performance, such as an excessive leakage current and premature breakdown.¹⁰⁰⁾ Thus, micropipes were identified as the most important killer defects and were eliminated or reduced to a satisfactory level (<0.1 cm⁻²).

Although a threading screw dislocation (TSD) in compound semiconductors usually creates a spiral with a one-bilayer-height step on {111} (or {0001}) faces, the step height of a spiral in 4H-SiC{0001} is four Si–C bilayers, corresponding to |1c|. (The step often splits into two two-bilayer-height spiral steps.) TSDs in SiC propagate nearly along the 〈0001〉 direction but occasionally they are bent towards the basal planes (and sometimes bent back towards 〈0001〉).¹⁰¹⁾ Recent studies using synchrotron X-ray topography revealed that the majority of TSDs possess a Burgers vector of 1c + a.^102,103) This means that these TSDs are not pure screw dislocations, but mixed dislocations.

A threading edge dislocation (TED) and basal plane dislocation (BPD) possess the same Burgers vector of a ($\langle 11\bar{2}0\rangle /3$). A slip of $\langle 11\bar{2}0\rangle /3$ results in the formation of an extra half plane or a missing half plane while keeping the stacking structure. Conversely, a slip of $\langle 1\bar{1}00\rangle /3$ causes a fault in the stacking. This kind of defect is called a Shockley-type stacking fault (SSF)¹⁰⁴⁾ and plays an important role in bipolar degradation phenomena, as described in Sect. 6.5. Figure 13(a) illustrates an extra (or missing) half plane in a SiC crystal. In this case, a dislocation with a Burgers vector of $[11\bar{2}0]/3$ is present along the edge of the extra half plane. As seen from the figure, the dislocation lying in the basal plane (line AB) is defined as a "basal plane dislocation" (pure edge-type), and the dislocation lying along the 〈0001〉 direction (line BC) is defined as a "threading edge dislocation". Therefore, a BPD and TED have the same basic nature; the name simply differs depending on the dislocation direction. Indeed, BPD-to-TED and TED-to-BPD conversions are commonly observed inside boule crystals.^101,105) Note that pure edge-type BPDs are not very abundant, and quite often, BPDs lie along the $\langle 11\bar{2}0\rangle$ directions, as shown in Fig. 13(b), due to the Peierls potential. In this particular case [Fig. 13(b)], the BPD (line A'B) is a 60° dislocation. The dominant nucleation process of BPDs is plastic deformation caused by thermal stress, which is typically induced by temperature inhomogeneity during crystal growth or a high-temperature process. In this case, BPDs can nucleate heterogeneously as half-loops from the crystal surface or as full-loops inside the crystal.¹⁰⁶⁾

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In the last two decades, extensive studies have been conducted, aiming at reducing extended defects in SiC boules, and one of the most striking techniques is the so-called "Repeated A–Face growth (RAF)" method.¹⁰⁷⁾ The main concept is (i) the preparation of an almost dislocation-free seed by repeating boule growth on $(11\bar{2}0)$ and $(1\bar{1}00)$ faces, and (ii) subsequent sublimation growth on the high-quality seed under stabilized conditions, the details of which are described in Ref. 107. An impressively low total dislocation density of 75 cm⁻² was achieved through this technique. More recently, a "dislocation-free" SiC boule has been fabricated by solution growth using a similar concept.¹⁰⁸⁾ However, the total dislocation density of commercial wafers is still 3000–6000 cm⁻². The stacking fault density in commercial SiC wafers is currently very low (below 1 cm⁻¹).

Figure 14 illustrates the dislocation replication and conversion typically observed in SiC epitaxial layers grown on off-axis {0001} by CVD.^87,109) Almost all the TSDs in a substrate are replicated in an epilayer, but a small portion (typically < 1%) are converted to Frank-type partial dislocations.¹¹⁰⁾ A TSD in the substrate can act as a nucleation site for a "carrot defect", as described in Sect. 6.3. Almost all the TEDs in a substrate are also replicated in an epilayer.

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The behavior of BPDs during epitaxial growth is much more complicated. A BPD is a detrimental defect for SiC bipolar devices because it can act as the source of a Shockley-type stacking fault upon carrier injection, which would locally reduce the carrier lifetime (increase on-resistance) and increase the leakage current.^111–113) This is called "bipolar degradation", and is treated in a separate subsection (Sect. 6.5). Since the elastic energy of a dislocation is naturally proportional to the dislocation length, BPD replication in an epitaxial layer grown on off-axis {0001} results in a large increase in the elastic energy. This energy is greatly decreased by a BPD-to-TED conversion, during which the dislocation length is shortened considerably by a factor of cot θ (θ: off-angle). This dislocation conversion can be explained by a so-called "image force" exerted on the BPD.¹⁰⁴⁾ In reality, most (>95%) BPDs in the substrate are converted to TEDs within a few µm of the initial epitaxial layer without any special treatment.^114–116) Some BPDs, however, are replicated in the SiC epitaxial layer. It has been discovered that all these BPDs propagating in basal planes of an epitaxial layer are of a screw character.^87,117,118) It is known that a perfect BPD in SiC is dissociated into two partial dislocations, and a single SSF is created between the two partials, where the SSF width is about 30–70 nm.¹¹⁹⁾ Conversion from BPDs to TEDs is enhanced by several techniques such as molten KOH etching^120,121) or H₂ etching¹²²⁾ prior to epitaxial growth or interruption during growth.¹²³⁾ The use of a substrate with a smaller off-angle is naturally effective in enhancing the conversion owing to the increased image force.¹²⁴⁾ High-temperature (∼1800 °C) annealing in Ar induces a spontaneous BPD-to-TED conversion near the surface (without growth).¹²⁵⁾ Furthermore, increasing the growth rate also effectively enhances the BPD–TED conversion.¹²⁶⁾ By combining these techniques, the conversion ratio has been increased to 99.9% or even higher. Thus, if the BPD density in a substrate is 1000 cm⁻², the density of BPDs replicated in an epitaxial layer is about 1 cm⁻² or less. It should be noted that BPDs easily glide during growth or high-temperature annealing under stress (misfit and thermal stress) because the critical resolved shear stress in SiC is relatively low, especially at high temperature.¹²⁷⁾ A BPD replicated in an epitaxial layer is deflected to the direction normal to the step flow, and the BPD often lies near the interface between a lightly-doped epitaxial layer and a heavily-doped substrate.^128,129) Such a BPD lying at the epitaxial layer/substrate interface is called an "interface dislocation".

Dislocations in SiC have been detected by molten alkali (e.g., KOH) etching at about 500 °C¹³⁰⁾ or X-ray topography. In recent years, a photoluminescence (PL) mapping or imaging technique has been developed as a fast nondestructive method to detect the location of dislocations and identify their type (TSD/TED/BPD).^131–136) Figure 15 shows (a) a typical PL image taken from a 180-µm-thick n-type SiC(0001) epitaxial layer at 880 nm and (b) an optical micrograph of the same location after molten KOH etching. In PL images taken at the band-edge emission (390 nm), threading dislocations and BPDs appear as dark spots and dark lines (or curves) (not shown), respectively. In contrast, an infrared PL image shows bright spots and bright lines (or curves), which have been identified as the locations of threading dislocations and BPDs, respectively, as shown in Fig. 15(b). TSDs produce much more intense PL in the infrared region (750–900 nm) than TEDs, which makes it possible to distinguish TSDs and TEDs. While the mechanism of the infrared luminescence from dislocations is unclear at present, localized states that are generated near the dislocation cores¹³⁷⁾ may be responsible for the luminescence. PL imaging/mapping is also a powerful method for the detection of stacking faults, as described in the next subsection.

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The nucleation of stacking faults (SFs) takes place during epitaxial growth, even if the substrate is free of stacking faults. So far, several types of "in-grown SFs" have been identified by cross-sectional transmission electron microscopy (TEM). A majority of these SFs are caused by slips in basal planes (Shockley-type). Note that most in-grown SFs are invisible in optical microscopy, and PL imaging/mapping is again a powerful method to detect these defects.^138–142)

Figure 16 shows examples of PL intensity maps taken at (a) 455, (b) 480, and (c) 500 nm from the same location.¹⁴²⁾ An optical micrograph is shown as well [Fig. 16(d)]. The shape of these SFs that show a PL peak at 455 nm is a right-angle triangle with its apex pointed towards the upstream side of the step flow. Conversely, the shape of the SF that shows 480 nm emission is an isosceles triangle elongated along the off-direction. The lengths of all these SFs along the off-direction agree with the projected length of a basal plane in the epitaxial layer. This implies that these SFs nucleated in the initial stage of epitaxial growth. Although the misalignment of atoms during step-flow growth has been suggested as the nucleation mechanism for SFs,¹⁴³⁾ the detailed mechanism is not entirely clear at present. Figure 17 shows high-resolution TEM images taken from the major in-grown SFs that exhibit PL peaks at (a) 455, (b) 480, and (c) 500 nm.¹⁴²⁾ These stacking sequences have been determined to be types (44), (53), and (62), respectively, in Zhdanov's notation. A one-to-one correlation has been established between the PL peak position and the stacking sequence. Frank-type in-grown stacking faults have also been reported.¹⁴⁴⁾ The density of these in-grown stacking faults is typically 0.1–1 cm⁻² but tends to increase in fast epitaxy.¹⁴³⁾

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SiC epitaxial layers grown on off-axis {0001} substrates occasionally exhibit several types of surface defects, most of which contain some kind of extended defect(s). Figure 18 shows the typical surface defects observed in SiC{0001} homoepitaxial layers: (a) "carrot" defect^145–147) and shallow pit,^148,149) (b) triangular defect,^150,151) and (c) down-fall. Although the exact formation mechanisms of these defects are not fully understood, these defects are usually created by technical problems such as the incomplete removal of polishing damage or non-optimized growth processes. The down-fall is generated by the falling of a SiC particle released from the susceptor wall. The density of these defects is mostly influenced by the surface quality of the substrates and the growth conditions. TEM studies revealed that the carrot (and comet) defects contain both a basal plane fault and a prismatic plane fault.^145–147) The triangular defects exhibit a variety of structures. In some triangular defects, the triangular region is actually cubic SiC (3C-SiC), while in others, only a 3C-like laminar region with a thickness of several Si–C bilayers is extended in the basal plane.^150,151) Several other types of surface morphological defects that contain extended defects have been reported.¹⁵²⁾

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Extended defects can affect the performance and reliability of semiconductor devices.¹⁵³⁾ However, the effects of extended defects in SiC are still not well understood. This subsection will summarize our current understanding of the effects of extended defects on SiC device performance and reliability (Table IV).

All kinds of macroscopic defects that are generated during epitaxial growth cause a considerable increase in leakage current and reduction in blocking voltage, and are detrimental to SiC devices.^12,154) These defects include triangular defects, carrot defects, and macro-defects induced by particles ("down-falls"). These defects usually contain stacking faults in a basal plane and/or a prismatic plane or contain a 3C-lamella, as described in the previous subsection. The density of these defects is typically 0.1–1 cm⁻² and tends to be higher in thick epitaxial layers.

In-grown stacking faults also cause increased leakage current and reduce the blocking voltage of SiC devices. It has been predicted that the bandgap is locally reduced at an in-grown stacking fault.^139,155) When SiC SBDs contain an in-grown stacking fault, the barrier height is locally reduced, leading to excessive leakage currents.¹⁵⁶⁾

The effects of TSDs and TEDs on device characteristics have been investigated by many research groups, and some conflicting results have been reported. Neudeck et al. reported the effects of a TSD on SiC(0001) pn diodes by direct comparison between the diode characteristics and the dislocation sites as determined by synchrotron X-ray topography.¹⁵⁷⁾ When a diode contained one TSD, the leakage current abruptly increased at a bias voltage slightly lower than the breakdown voltage. Along with the increase in leakage current, a microplasma was simultaneously observed at the location of the TSD. However, the breakdown voltage itself was hardly affected by the presence of a single TSD. Extensive comparisons between the characteristics of SiC SBDs and their dislocation sites have also been conducted by several groups.^158,159) However, no direct evidence was obtained for the negative effects of TSDs and TEDs on diode characteristics. An example of such results is shown in Fig. 19. The leakage current of Ni/SiC SBDs containing 15–20 TSDs is almost identical to that of TSD-free diodes. Many groups have found that the impact of TSDs and TEDs on the characteristics of SiC pn diodes was negligibly small.

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In recent years, the SiC community has learned that surface pits can be formed at TSD and TED sites. The depth of these pits is typically 3–20 nm, and the pits are deeper for TSDs than for TEDs.¹⁶⁰⁾ When the pits are created, local electric field crowding occurs, simply because of a geometric effect.¹⁶¹⁾ Fujiwara et al. found that the negative effects of TSDs on the diode characteristics could be eliminated almost entirely by suppressing the formation of dislocation-induced pits.¹⁶²⁾ Figure 20 shows the reverse characteristics of SiC SBDs fabricated on wafers (a) with surface pits associated with dislocations and (b) without such pits.¹⁶²⁾ It was confirmed that the locations of excessive leakage current for the diodes shown in Fig. 20(a) exactly matched the surface pits. Upon removing these pits, however, all the diodes exhibited a low leakage current regardless of the number of dislocations present inside the diode area. The size and depth of these dislocation-induced pits strongly depend on the growth conditions and processing conditions. This may be the main reason why different groups have observed somewhat different results for the effects of dislocations. As described above, the negative effects of dislocation-induced pits can be minimized to a satisfactory level by suppressing pit formation or by preparing pit-free surfaces via polishing.

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To isolate the effects of dislocations (without surface pits) on SiC devices, the change in the electronic states near the dislocation cores must be taken into account. Chung et al. conducted electron holography measurements on TSDs in n-type SiC and reported that a deep state (E_c − 0.89 eV) was formed near a TSD core.¹³⁷⁾ Because the chemical bonds near a dislocation core are severely distorted (or broken), which is a major disturbance in the periodic potential inherent to SiC, localized states and/or local changes in the bandgap are expected to occur near the dislocation core.¹⁵³⁾ The states associated with these dislocations must, of course, be active under high electric fields, making them potential candidates for excessive leakage current. The total leakage current of a SiC junction (I_leakage) can be obtained roughly using the following equation:

$$\begin{equation} I_{\text{leakage}} = I_{0} + I_{\text{gen}} + \sum_{i}^{n}I_{i}\,(\text{dislocation}), \end{equation} \tag{ 2 }$$

where I₀ is the ideal leakage current determined for a defect-free SiC junction and I_gen is the generation current, which is dominated by bulk carrier generation via deep levels and by surface carrier generation via surface states. I_i (dislocation) is the leakage (generation) current induced by the ith dislocation inside the junction. The ideal leakage current (I₀) of a pn diode is proportional to $n_{\text{i}}^{2}$ (n_i: intrinsic carrier density), while the generation current due to point defects, surface states, and dislocations is basically proportional to n_i.^53,153) Because of the very low intrinsic carrier density of SiC (∼10⁻⁹ cm⁻³ at 300 K), the ideal leakage current (I₀) of SiC pn diodes is estimated to be in the 10⁻⁴⁰ A/cm² range or lower. Thus, the observed leakage current of SiC pn diodes is clearly governed by the generation current (via the point defects, surface states, and dislocations).^12,154) The dominant leakage path depends on the densities of the defects (point defects, surface states, and dislocations). As indicated by Eq. (2), each dislocation (TSD or TED) adds a small component of generation current to the leakage current, but these dislocations do not have a detrimental effect on SiC devices because of their relatively low density in state-of-the-art SiC epitaxial wafers. Carrier generation at dislocation sites must become significant when the electric field strength is high, for example, higher than 3 MV/cm. Therefore, leakage current through dislocations will be pronounced for low-voltage (<300 V) devices,¹⁵⁷⁾ where the maximum electric field strength can exceed 3 MV/cm. For relatively high-voltage (>1 kV) devices, where the electric field strength does not exceed 3 MV/cm (because the breakdown electric field strength decreases with decreasing the doping density, as shown in Fig. 11), the third term in Eq. (2) is small and can only be unacceptably large when the dislocation density is very high (≫10⁶ cm⁻²), as in the case of heteroepitaxially grown materials.

It is often found that when the device area is scaled up, the leakage current density for SiC devices increases significantly while the breakdown voltage decreases. In such large devices, the probability that the device contains macroscopic defects generated by epitaxial growth (triangular defects, carrot defects, in-grown stacking faults, and down-falls) increases. Indeed, many groups have observed that these epitaxially induced defects have a detrimental effect on SiC devices. Figure 21 shows histograms of the breakdown voltage of 1500-V-class SiC pn diodes containing such epitaxially induced defects. One can immediately see how damaging these defects are. This is the main reason why a larger number of devices exhibit a high leakage current density and low breakdown voltage as the device area is scaled up. Therefore, the most critical device-killing defects in state-of-the-art SiC epitaxial wafers are not TSDs or TEDs but ultimately these epitaxially induced defects. Improvement of the epitaxial process of SiC is strongly required to achieve a high yield in fabrication of large-area devices.

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The correlation between gate-oxide reliability and the dislocations in SiC has also been investigated. In earlier studies, it was found that TSDs and BPDs severely degrade the oxide reliability (reduction of the mean failure time under high electric fields or reduction of the charge-to-breakdown).^163–166) A more recent study has found that these negative effects can be minimized by removing the surface pits created at the dislocation sites.¹⁶⁷⁾ The epitaxially induced defects are far more detrimental to the dielectric properties of gate oxides than threading dislocations. However, the impact of dislocations on oxide reliability has not been fully clarified, and careful investigations are required before a definitive conclusion can be reached.

BPDs, on the other hand, are clearly detrimental to all types of SiC bipolar devices because upon carrier injection, BPDs cause the phenomenon of bipolar degradation.^111,112) All kinds of BPDs (including interface dislocations¹²⁸⁾ and the basal plane segment of a dislocation half-loop) act as nucleation sites for SSFs upon minority-carrier injection and recombination,^112,168) as described in the next subsection.

Assuming a uniform distribution of device-killing defects, the yield (Y), which is defined as the number of good devices divided by the number of fabricated devices, can be obtained approximately using the following equation:¹⁶⁹⁾

$$\begin{equation} Y = \exp(-DA), \end{equation} \tag{ 3 }$$

where D and A are the device-killing defect density and the device area, respectively. Figure 22 plots the device yield versus the device area calculated from Eq. (3) by varying the device-killing defect density (D) as a parameter. In the figure, rough values of the rated current are indicated on the upper horizontal axis, assuming a current density of 200 A/cm². If the device-killing defect density is 10 cm⁻², then to attain a high yield of 80%, the maximum device area must be smaller than 2 mm², which corresponds to a maximum rated current of only 4 A. To fabricate 100 A devices (device area ≈50 mm²) with a yield of 80%, the device-killing defect density must be reduced to 0.4 cm⁻². On the basis of the above discussion, the main device-killing defects in state-of-the-art SiC epitaxial wafers can thus be assumed to be epitaxially induced defects (including triangular defects, carrot defects, in-grown stacking faults, and particles) for unipolar devices, and both epitaxially induced defects and BPDs for bipolar devices. However, much more extensive studies are required to elucidate all aspects of defect electronics in SiC.

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After carrier injection (or excitation) followed by carrier recombination in SiC, the nucleation and expansion of a SSF takes place at the location of a BPD or at a basal plane segment of other dislocations.^111,112) The expanded SSF causes a significant reduction in the carrier lifetime and also the formation of potential barriers for carrier transport, leading to an increase in the forward voltage drop in SiC bipolar devices such as PiN diodes, BJTs, and thyristors. The expanded SSF also acts as a severe leakage current path in a reverse-biased junction. These observations are due to a phenomenon called "bipolar degradation", which is detrimental to the reliability of SiC-based bipolar devices. Note that pure SiC unipolar devices such as SBDs do not exhibit this degradation because of the absence of carrier injection. A comprehensive review of bipolar degradation in SiC is available in the literature.¹¹²⁾

Figure 23 shows examples of bipolar degradation observed in SiC PiN diodes: (a) the forward current–voltage characteristics and (b) the change in the forward voltage drop at 100 A/cm² as a function of the stress time. In this experiment, the diodes were stressed under a constant current (100 A/cm²). The forward voltage drop exhibits irregular increases at several different times, reaching 6 V or even higher in some diodes. A low current density of 1–10 A/cm² is sufficient to cause this degradation. In a degraded PiN diode, multiple dark triangular (or trapezoidal) regions, which correspond to expanded stacking fault planes, are observed in near-band-edge PL or cathodoluminescence (CL) images.¹¹¹⁾ On the other hand, the stacking-fault regions exhibit a distinctive luminescence with a peak wavelength of 424 nm at room temperature.¹⁷⁰⁾

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The exact stacking structure of expanded stacking faults has been identified by cross-sectional TEM.¹⁷¹⁾ Figure 24 shows (a) a high-resolution TEM image of the fault region of a 4H-SiC(0001) PiN diode and schematics of the stacking sequence of (b) the observed structure and (c) perfect 4H-SiC. The stacking fault can be denoted by the (31) structure using Zhdanov's notation, while perfect 4H-SiC has the (22) structure. The energy position of the electronic states formed by this type of SSF in 4H-SiC is calculated to be E_c − 0.22 eV,¹⁷²⁾ which is consistent with the luminescence result.

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The expansion of SSFs occurs because the activation energy for the glide motion of the partial dislocations is significantly reduced by the energy transfer in the electron–hole recombination process. Thus, this phenomenon is not only observed during the on-state operation of SiC bipolar devices but also during PL or CL measurements. In real SiC bipolar devices, however, the morphology of the expanded SSFs is influenced by the device structure. In SiC PiN (p⁺/i/n⁺ structure) diodes, for example, carrier recombination mainly occurs within the lightly-doped i-region, where a high-density electron–hole plasma is created by forward biasing. (Carrier recombination also occurs inside the p⁺-anode and n⁺-cathode, roughly within a distance equivalent to the diffusion length of minority carriers in individual highly-doped regions.) Therefore, the expansion of the SSFs almost ends when the fronts of the gliding partials reach the p⁺/i or i/n⁺ interface. Schematic illustrations of SSF expansion from a BPD in an epitaxial layer replicated from a substrate are shown in Fig. 25. In this figure, a screw-type BPD ($\boldsymbol{{b}} = [11\bar{2}0]/3$, dislocation line ∥ $[11\bar{2}0]$) in a SiC PiN diode is schematized in (a) and the SSF expansion inside a SiC PiN diode is shown in (b). In the PiN diode, the SSF expansion is restricted by not only the immobile C-core partial dislocation but also the electron–hole recombination region. For the reasons described above, the majority of the expanded SSFs in PiN diodes (or other devices) are triangular in shape. On the other hand, an SSF expanded from a BPD segment of a dislocation half-loop exhibits a rhombic shape.^112,173)

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The driving force behind the SSF expansion has been studied and was found to be intrinsic to the material and not caused by stress.¹¹²⁾ Therefore, complete elimination of nucleation sites is essential for the development of SiC bipolar devices. Bipolar degradation is the most serious problem in the development of SiC bipolar devices and can also be harmful to SiC field-effect transistors when the body diodes (p⁺ body/n⁻ drift layer) are forward-biased. The reduction of BPD density in bulk growth, enhanced conversion from BPDs to TEDs during epitaxial growth, and the elimination of BPD nucleation during device processing are the most important remaining issues in SiC technology.

Another important type of defect in epitaxial layers is point defects, which create deep level(s) in a bandgap.¹⁷⁴⁾ Deep levels are usually characterized by deep-level transient spectroscopy (DLTS) measurements^175–177) on SiC Schottky (or pn) structures. The density of deep levels in lightly-doped as-grown SiC(0001) epitaxial layers is typically 5 × 10¹²–2 × 10¹³ cm⁻³, depending on the growth conditions. This value is fairly low for a compound semiconductor and is acceptable for the fabrication of unipolar devices. In the fabrication of power MOSFETs, for example, deep levels created by ion implantation are more important. For bipolar device applications, however, the above-mentioned density is not low enough, especially when a long carrier lifetime is required. Details are presented in Sect. 7.2.

Figure 26 shows the energy levels of major deep levels observed in as-grown n- and p-type 4H-SiC epitaxial layers.^178–183) Among these levels, the Z_1/2 (E_c − 0.63 eV)¹⁷⁸⁾ and EH6/7 (E_c − 1.55 eV)¹⁷⁹⁾ centers are the dominant defects commonly observed at densities of (0.3–2) × 10¹³ cm⁻³ in all as-grown epitaxial layers grown by CVD. Both centers are extremely stable against high-temperature (∼1700 °C) annealing. In the lower half of the bandgap, the HK2 (E_v + 0.84 eV), HK3 (E_v + 1.24 eV), and HK4 (E_v + 1.44 eV)¹⁸³⁾ centers are dominant deep levels. The densities of HK2, HK3, and HK4 centers are typically in the range of (1–4) × 10¹² cm⁻³. Because the HK2, HK3, and HK4 centers almost disappear upon annealing at 1450–1550 °C,¹⁸³⁾ the Z_1/2 and EH6/7 centers are more important. Note that the Z_1/2 and EH6/7 centers are also dominant in ion-implanted regions and dry-etched regions of SiC.^{178,184–186)} In addition to these levels, a few impurity-related levels are often observed in as-grown SiC epitaxial layers. For example, boron is a typical impurity that can be unintentionally doped from reactor parts (such as graphite susceptors). Boron contamination creates the boron acceptor level [E_v + (0.28–0.35) eV]⁶⁶⁾ and the boron-related "D center" (E_v + 0.55 eV).⁶⁶⁾ Another common impurity is titanium (Ti), which also originates from graphite parts as well as from pumping oil. Titanium creates very shallow electron traps (E_c − 0.11/0.17 eV) in 4H-SiC.¹⁸⁷⁾ The typical impurity density in CVD-grown SiC epitaxial layers is about (0.5–5) × 10¹³ cm⁻³ for boron and (0.5–5) × 10¹² cm⁻³ for titanium.

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The Z_1/2 center and EH6/7 center (or at least the EH7 center) are observed with almost identical density in all SiC samples.¹⁸⁰⁾ The origin of the Z_1/2 center and the EH7 center was unambiguously identified as a carbon monovacancy (V_C) with different charge states on the basis of theoretical calculations¹⁸⁸⁾ and a compartive study using DLTS and electron paramagnetic resonance (EPR).^189–191) Figure 27(a) plots the area density for single-negatively-charged carbon vacancies [V_C(−)] as determined by EPR versus the area density of Z_1/2 centers taken from the depth profile obtained by DLTS measurements.¹⁹¹⁾ Because V_C(2−) is not EPR-active (because it contains no unpaired electrons), the V_C density is estimated by producing V_C(−) through the photoexcitation of n-type SiC. As shown in Fig. 27(a), the V_C density is very close to the Z_1/2 center density for a series of samples. Figure 27(b) depicts the energy levels of a carbon monovacancy, Z_1/2, and EH7 centers.¹⁸⁹⁾ The Z_1/2 and EH7 centers are ascribed to the acceptor (negative-U)¹⁸²⁾ and donor levels of the carbon monovacancy, respectively.

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The densities of Z_1/2 and EH6/7 centers are strongly dependent on the C/Si ratio and growth temperature.^192–194) However, the growth rate only has a minor effect on defect generation, even when the growth rate is changed from 5 to 80 µm/h.⁸⁷⁾ Both the Z_1/2 and EH6/7 densities can be considerably reduced by increasing the C/Si ratio during CVD on (0001). Both defect densities increase significantly with increasing growth temperature. The Z_1/2 and EH6/7 centers in SiC are thermally stable, and the densities of the Z_1/2 and EH6/7 centers in the epitaxial layers have been found to increase rapidly through thermal annealing in Ar at temperatures above 1750 °C.¹⁹⁵⁾ This can be attributed to the higher equilibrium density of the carbon vacancy in SiC at higher temperatures. An Arrhenius plot of the density of the Z_1/2 center as a function of the inverse of the annealing temperature yields a free energy of the defect (carbon vacancy) formation of approximately 5.8 eV.

The Z_1/2 center is the most important defect because of its abundance and its being a major carrier-lifetime killer, at least in n-type 4H-SiC.^196,197) Figure 28 shows the inverse of the carrier lifetime versus the measured density of the Z_1/2 center for 50-µm-thick n-type SiC epitaxial layers.^197,198) At Z_1/2 densities above (1–2) × 10¹³ cm⁻³, the inverse of the carrier lifetime is proportional to the Z_1/2 density, indicating that the lifetime is governed by Shockley–Read–Hall (SRH) recombination via the Z_1/2 center. However, the correlation between the lifetime and the Z_1/2 density is unclear when the Z_1/2 density is in the 10¹¹–10¹² cm⁻³ range. In a semiconductor, multiple recombination processes occur, including SRH recombination and several other recombination processes. Thus, the carrier lifetime (τ) can be expressed by the following equation:

$$\begin{equation} \frac{1}{\tau} = \frac{1}{\tau_{\text{SRH}}} + \frac{1}{\tau_{\text{other}}}, \end{equation} \tag{ 4 }$$

where τ_SRH is the SRH lifetime governed by recombination centers, and τ_other is the carrier lifetime governed by other recombination processes, such as surface recombination, recombination in the substrate, Auger recombination, and recombination at extended defects. Here, the inverse of τ_SRH is proportional to the density of the recombination centers (1/τ_SRH = aN_Z1/2, where a is a constant, and N_Z1/2 is the density of the Z_1/2 center), while τ_other can be assumed to be independent of the Z_1/2 density. Experimental data can be fitted by using the model expressed by Eq. (4). The fitted result is shown as a solid line for 1/τ_SRH + 1/τ_other and as two broken lines for 1/τ_SRH and 1/τ_other in Fig. 28. Here the 1/τ_other line is determined by recombination at the surface and in the substrate owing to the limited thickness of the epitaxial layers (50 µm in this plot), and this component is decreased by using thicker epitaxial layers. The details have been described elsewhere.¹⁹⁹⁾

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To obtain a long carrier lifetime, which is beneficial for reducing the on-resistance in bipolar devices, the density of the Z_1/2 center must be decreased to the order of 1 × 10¹² cm⁻³ or lower. Thus far, two successful techniques have been proposed to eliminate the Z_1/2 center (or carbon vacancy).

In the first technique, excess carbon atoms are introduced from the outside and the diffusion of these carbon atoms into the bulk region is promoted by high-temperature annealing.^200,201) This can actually be achieved by carbon ion implantation and subsequent annealing in Ar at 1650–1700 °C. Figure 29 shows the DLTS spectra obtained from n-type SiC epitaxial layers before and after carbon ion implantation followed by high-temperature Ar annealing. The Z_1/2 and EH6/7 centers are both eliminated by this process to below the detection limit (approximately 1 × 10¹¹ cm⁻³ in this case). Because the created carbon interstitials have large diffusion coefficients above 1400–1500 °C, the excess carbon interstitials diffuse and fill the carbon vacancies, leading to the elimination of the Z_1/2 and EH6/7 centers from the surface region to the bulk. After annealing, the defective implanted region near the surface is removed by plasma etching.

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In the second technique, the thermal oxidation of SiC under appropriate conditions eliminates the Z_1/2 and EH6/7 centers.^202,203) During the thermal oxidation, carbon atoms are mostly removed by the production of carbon monoxide (CO). However, a certain proportion of the carbon atoms are emitted into the bulk region and diffuse deep into the SiC. As in the case of carbon ion implantation, the diffusion coefficient of the carbon interstitials is so large that the depth to which the Z_1/2 and EH6/7 centers are eliminated can exceed 100 µm by either the combination of oxidation and subsequent high-temperature Ar annealing or by high-temperature oxidation (1300–1400 °C).²⁰⁴⁾ It should be noted that the migration energy of the carbon interstitials is much lower than that of the silicon interstitials,⁵⁸⁾ and the experimentally obtained self-diffusion coefficient of carbon is much larger than that of silicon.²⁰⁵⁾ During high-temperature oxidation or annealing, carbon vacancies (or Z_1/2 center) are almost immobile because of the extremely low diffusion coefficient in SiC.^58,178) Figure 30 shows the depth profile of the Z_1/2 center density for SiC epitaxial layers after thermal oxidation.²⁰⁴⁾ By extending the oxidation time or raising the oxidation temperature, the "Z_1/2-free" region extending from the surface becomes thicker (100 µm or even thicker).

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Figure 31 plots the microwave-detected photoconductance (µ-PCD) decay curves at room temperature obtained from a 220-µm-thick n-type SiC epitaxial layer.¹³⁶⁾ The decay curves for the as-grown material and for the material after Z_1/2-center reduction through thermal oxidation at 1400 °C for 48 h are shown. For the as-grown epitaxial layer, the measured lifetime is 1.1 µs, while the lifetime is greatly improved to 26 µs after the defect reduction process. The depth of the Z_1/2-eliminated region of this particular sample is estimated to be about 230 µm, indicating that the defects are eliminated throughout the entire thickness of the epitaxial layer. After lifetime measurement of the defect-eliminated sample, the surface was passivated with a 20-nm-thick deposited oxide annealed in nitric oxide (NO) at 1250 °C for 30 min. After this surface passivation, the lifetime increased to 33 µs, and then to 47 µs at a measurement temperature of 200 °C. Similar carrier lifetimes can be achieved by carbon ion implantation and subsequent Ar annealing.²⁰⁶⁾

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The carrier lifetime in p-type SiC is more complicated. Because the Fermi level is close to the valence band in p-type SiC, the carbon vacancy defect must be positively charged [V_C(+): EH7 center] in equilibrium. Thus, it is expected that any excess electrons will quickly be trapped by the defect, and the charge state will change to neutral. However, accurate capture cross sections for electrons and holes are not yet known for this neutral defect. The carrier lifetime of as-grown p-type SiC epilayers is typically about 1 µs, increasing to 2–3 µs after the carbon-vacancy reduction process (carbon implantation or high-temperature oxidation).^207,208) The measured lifetimes seem to be more sensitive to the surface passivation compared with the case of n-type SiC. Through the carbon-vacancy reduction process and subsequent hydrogen annealing at 1000 °C for 10 min, a long carrier lifetime of 10 µs has been obtained for lightly-doped p-type SiC epilayers (acceptor density: 2 × 10¹⁴ cm⁻³).²⁰⁹⁾ It should be pointed out that the measured lifetimes are severely underestimated, especially when the lifetime is long, due to the influence of surface recombination.¹⁹⁹⁾ Accurate determination of the surface recombination velocity of SiC is an important subject of study.²¹⁰⁾

It has been reported that the on-resistance of ultrahigh-voltage (>10 kV) SiC PiN diodes can be improved dramatically by such lifetime enhancement.^109,211) One example is shown in Fig. 32, where the forward current density versus voltage characteristics of 13-kV-class SiC PiN diodes are plotted.³⁹⁾ The thickness and donor density of the voltage-blocking layer (i-layer) are 98 µm and 2 × 10¹⁴ cm⁻³, respectively. Before epitaxial growth of the p-type anode layer, one wafer was oxidized at 1400 °C for 24 h to enhance the carrier lifetime, while the other wafer was processed without oxidation. Through this lifetime enhancement process, the differential on-resistance at a current density of 100 A/cm² improved markedly from 6.7 to 1.8 mΩ cm². To achieve a low on-state loss and switching loss, control of the carrier lifetime will be required in the future.¹⁹⁷⁾

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Figure 33 plots the barrier height versus metal work function for n-type SiC SBDs with various metals.^212–216) Data for SiC(0001), $(000\bar{1})$, and $(11\bar{2}0)$ are shown. For a given metal, the barrier height is slightly higher on $(000\bar{1})$ and slightly lower on (0001), with the value for $(11\bar{2}0)$ in between them. This difference may be attributed to the presence of polarity-dependent dipoles at the interface and/or the different distribution of surface states. The slope of this plot is 0.8–0.9, indicating that the metal/SiC interface is free from Fermi level pinning and close to the Schottky–Mott limit.^217,218) The barrier heights can be changed slightly by employing different processes, such as surface treatment, prior to metal deposition.

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Schottky barrier heights on p-type SiC have been much less studied,²¹⁹⁾ but it has been found that the sum of the Schottky barrier heights on n- and p-type SiC (ϕ_Bn, ϕ_Bp) for a given Schottky metal material is close to the bandgap (E_g):

$$\begin{equation} \phi_{\text{Bn}} + \phi_{\text{Bp}}\approx E_{\text{g}}. \end{equation} \tag{ 5 }$$

Therefore, a metal having a small work function such as Ti gives a high barrier height on p-type SiC. This insight is useful not only for the design of SiC SBDs but also for the process optimization of ohmic contacts.

Unique device physics is involved in the reverse leakage current of SiC SBDs. In SiC, the electric field strength in the space-charge region can be almost ten times higher than that for Si-based devices. Therefore, the band bending can be so sharp that the potential barrier can be very thin. Figure 34(a) illustrates the band diagram for an n-type SiC Schottky barrier under high reverse bias. In Si SBDs, the reverse leakage current is well described by a thermionic emission model, taking into account the barrier height lowering by the image force,^53,217) unless the semiconductor is heavily doped. In SiC SBDs, however, the observed leakage current density is many orders of magnitude higher than the value calculated by the thermionic emission model (taking into account barrier height lowering). In the early stage, a leakage current through crystalline defects or severe local lowering of the Schottky barrier height was suspected to occur. However, it turned out that there is an important reason for the relatively large leakage current in SiC SBDs. In SiC, the triangular-like potential barrier can be very thin because of the high electric field, and the leakage current is governed by thermionic field emission,^220,221) as shown in Fig. 34(a). The leakage current density based on a thermionic field emission (TFE) model can be expressed by the following equation:²²¹⁾

$$\begin{align} J_{\text{TFE}} &= \frac{A^{*}Tq\hbar E}{k}\sqrt{\frac{\pi}{2m^{*}kT}}\\ &\quad\times \exp \left\{-\frac{1}{kT}\left[\phi_{\text{B}} - \frac{(q\hbar E)^{2}}{24m^{*}(kT)^{2}}\right]\right\}, \end{align} \tag{ 6 }$$

where m^* and E are the tunneling mass of carriers and the electric field strength, respectively. Here q, k, and T are the elementary charge, Boltzmann constant, and absolute temperature, respectively. A^* is the effective Richardson's constant for the semiconductor. In SBDs on n-type 4H-SiC(0001), A^* has been determined to be 146 A cm⁻² K⁻² by using M_c (number of equivalent conduction band minima) = 3 and m^* = 0.4 m₀.¹⁵⁾ This value agrees with that obtained from a careful experiment.²²²⁾ Note that the effective Richardson's constant depends on the crystal face as well as on the conductivity type (n- or p-type). Figure 34(b) shows an example of reverse current–voltage characteristics of a Ti/SiC(n-type) SBD at various temperatures.²²¹⁾ The considerable increase in leakage current with increasing bias voltage, as well as the small temperature dependence, can be well reproduced by the TFE model. It has been reported that the leakage current in SBDs formed on high-quality GaN(0001) can also be reproduced by the TFE model.²²³⁾ Thus, the TFE current will be dominant in SBDs on any wide-bandgap material that exhibits a high electric field strength, such as SiC, GaN, gallium oxide (Ga₂O₃), and diamond.

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Therefore, an effective way to reduce the leakage current of SiC SBDs is to minimize the electric field strength near the Schottky barrier interface so that the potential barrier does not become too thin. For this purpose, several diode structures have been developed. Figure 35 shows schematics of (a) a junction barrier Schottky (JBS) diode^17,224,225) and (b) a trench SBD.⁴⁸⁾ In JBS diodes, p-type islands (or stripes) are formed beneath the Schottky contact by aluminum ion implantation. At a high reverse bias voltage, the space-charge regions extending from the pn junctions (p-type island/n-type drift layer) merge and the electric field strength near the Schottky interface is reduced. The concept is very similar in trench SBDs, where the space-charge regions extending from the pn junctions at the trench bottom play an important role. In either case, the width and spacing of the p-island or trench are critical, because otherwise the on-resistance can be severely increased by the space-charge regions. Since the TFE current is very sensitive to the barrier height, the uniformity of the Schottky barrier height is essential to ensure a low leakage current.^159,226,227) A small area having a smaller barrier height can be a dominant leakage path in SiC SBDs.

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Figure 36 shows a schematic of a DIMOSFET, where the major components of resistance are indicated.^3,4) The on-resistance of a power MOSFET naturally consists of a series connection of several resistances, such as the source resistance, the channel resistance, the drift-layer resistance, and the substrate resistance. In DIMOSFETs, the resistance between two neighboring p-wells ("JFET resistance") cannot be neglected. For SiC DIMOSFETs, the drift-layer resistance is more than 100 times lower than that of Si power MOSFETs having the same blocking voltage, as described in Sect. 2. On the other hand, the channel resistance and JFET resistance are dominant factors in SiC MOSFETs with blocking voltages up to about 2–3 kV. Above 3–5 kV, the on-resistance of SiC MOSFETs is dominated by the drift-layer resistance, as in the case of 600–1200 V Si MOSFETs.

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It has been pointed out that the performance of SiC MOSFETs can be limited by a low channel mobility, which yields a high channel resistance.^12,13,16) To improve the channel resistance, the following approaches have been used:

• (i)   
  Enhancement of channel mobility
• (ii)   
  Decrease in channel length
• (iii)   
  Reduction of cell pitch.

Enhancement of the channel mobility, which is a challenge, will be described in the subsequent subsections. A shortened channel length can directly contribute to the reduction of on-resistance. However, one has to be vigilant of the short-channel effect.²²⁸⁾ Without appropriate design taking account of the short-channel effect, the threshold voltage decreases and the leakage current increases. Reduction of the cell pitch is effective in increasing the cell density (and thus also the channel width). However, when the spacing between p-wells becomes short, the JFET resistance increases considerably.²²⁹⁾ Thus, careful structure optimization by device simulation is a mandatory requirement to improve the MOSFET performance. Note that trench MOSFETs are, in principle, free of JFET resistance, and the extensive scaling of cells is possible. This is one of the main reasons why very low on-resistances have been reported for trench MOSFETs.^43,48)

Thermal oxides of SiC are commonly employed as a gate dielectric in MOS devices as well as to passivate the SiC surface. However, the most striking difference from Si technology is, of course, the presence of carbon, one of the host elements in SiC. A number of review papers have been published on SiC MOS structures.^230–237) Despite continuous improvement of the SiC MOS interface, the interface quality and the scientific community's understanding of the factors that control this quality are still far from satisfactory. This subsection briefly describes the common features, present understanding, and problems of SiC MOS technology.

Conventional dry oxidation usually yields a high density of interface states and poor channel mobility of below 10 cm² V⁻¹ s⁻¹. The situation is not improved even when annealing is performed in a hydrogen ambient.^230,231) In recent years, however, low interface state densities have been obtained through careful adjustment of the oxidation conditions, taking into account the oxidation reactions of SiC.^238,239) When oxidation is carried out in a wet ambient, SiC MOSFETs on $(000\bar{1})$²⁴⁰⁾ and $(11\bar{2}0)$^241,242) exhibit relatively high mobilities of 90–200 cm² V⁻¹ s⁻¹.

One promising process to improve the properties of SiC MOS structures is post-oxidation nitridation in a nitrogen-containing gas such as NO,^243–251) nitrous oxide (N₂O),^252–254) or ammonia (NH₃).²⁵⁵⁾ Direct oxidation in N₂O or NO was also proposed. In particular, interface nitridation by NO or N₂O is widely employed in academic research as well as in the mass production of SiC power MOSFETs. Figure 37 depicts the distribution of the interface state density (D_IT) near the conduction and valence band edges obtained from n- and p-type SiC(0001) MOS capacitors, respectively.²³⁵⁾ The interface state densities of MOS structures formed by dry oxidation, and dry oxidation followed by nitridation in NO or N₂O are plotted. In this figure, the interface state density was evaluated by the conventional high (1 MHz)-low method. Clearly, a reduction in the interface state density over the entire range of energies within the bandgap is achieved by nitridation. As a result, the effective mobility of n-channel SiC(0001) MOSFETs fabricated on lightly-doped p-type epitaxial layers was enhanced from 4–8 cm² V⁻¹ s⁻¹ for dry oxides to 25–35 cm² V⁻¹ s⁻¹ for N₂O-nitrided oxides, and to 40–52 cm² V⁻¹ s⁻¹ for NO-nitrided oxides. The effective mobility of p-channel MOSFETs is also improved from 1–2 cm² V⁻¹ s⁻¹ for dry oxides to 7–12 cm² V⁻¹ s⁻¹ for nitrided oxides.²⁵⁶⁾

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It has been found that a high density of very fast interface states is generated near the conduction band edge by nitridation annealing,²⁵⁷⁾ although the density of relatively slow interface states is markedly reduced by nitridation, as shown in Fig. 37. The very fast states can respond to a probe frequency of 100 MHz or even higher (>GHz) at room temperature. Figure 38 shows the interface state densities obtained for SiC(0001) MOS capacitors by the high (1 MHz)–low method, the C–ψ_S method,²⁵⁸⁾ and the conductance method, where E_c − E_T (E_T: energy level of interface traps) on the horizontal axis is determined from the surface potential calculated by the depletion approximation.²⁵⁸⁾ In the conductance measurements, the highest probe frequency was 100 MHz. All measurements were performed on the same MOS capacitor with a roughly 40-nm-thick dry oxide annealed in NO. The D_IT distribution obtained by the high (1 MHz)–low method is much lower than that obtained by the C–ψ_S method because fast interface states that respond to frequencies above 1 MHz are not detected. Even for SiC MOS structures without nitridation (without fast interface states generated by nitridation), the D_IT distribution is markedly underestimated by the high (1 MHz)–low method. The limitations of the high-low method have been summarized in the literature.²⁵⁹⁾ Despite recent process development, the interface state density of SiC MOS structures is still very high: about (0.5–1) × 10¹³ cm⁻² eV⁻¹ at E_c − 0.2 eV after appropriate nitridation.

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Annealing in NO or N₂O naturally results in the accumulation of nitrogen at the SiO₂/SiC interface. The nitrogen atom density at the interface strongly depends on the nitridation conditions and can reach 5 × 10²⁰ cm⁻³ or higher. A correlation between the increase in nitrogen density at the interface and the reduction in interface state density has been indicated. However, it is unclear how the interface defects are passivated by nitridation. The passivation of dangling bonds with nitrogen or a simple shift in defect energy levels by nitridation is unlikely.

Post-oxidation nitridation or direct oxidation in a nitrogen-containing gas is also effective in reducing the interface state density on SiC$(000\bar{1})$, $(11\bar{2}0)$, and $(1\bar{1}00)$.^{250,253,260,261)} Figure 39 shows the field-effect mobility as a function of the gate voltage of n-channel MOSFETs fabricated on SiC(0001), $(000\bar{1})$, $(11\bar{2}0)$, and $(1\bar{1}00)$. Roughly 40-nm-thick oxides were grown by dry oxidation, and subsequent nitridation was performed in a NO (10%)/N₂ (90%) atmosphere at 1250 °C. The channel mobility obtained is reasonably high, 46 cm² V⁻¹ s⁻¹, on $(000\bar{1})$, and very high, 95–115 cm² V⁻¹ s⁻¹, on $(11\bar{2}0)$ and $(1\bar{1}00)$. The latter result is promising for the development of trench MOSFETs on SiC(0001) wafers. The effects of the tilt angle on the channel mobility of SiC MOSFETs with $(11\bar{2}0)$ and $(1\bar{1}00)$ sidewalls have also been investigated.²⁶²⁾

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The exact origin of the high interface state density for SiC is not very well understood. In the case of Si MOS structures, dangling bonds at the interface are the dominant defects (for example, the P_b center).²⁶³⁾ Since the interface state density for thermal oxide/Si structures is in the 10⁹–10¹⁰ cm⁻² eV⁻¹ range, it is unlikely that the high interface state density (10¹²–10¹³ cm⁻² eV⁻¹) for SiC MOS structures is attributable simply to dangling bonds. Afanas'ev et al. suggested that the donor-like interface states in the lower half of the bandgap may originate from carbon clusters (carbon-cluster model), on the basis of internal photoemission spectroscopy studies of SiC MOS structures and graphite.²³¹⁾ Although it has been suggested that residual carbon near the interface may play a role, a direct link between the carbon density near the interface and the interface state density has not been established. The abnormally high interface state density near the conduction band edge of SiC(0001) also remains a mystery. To elucidate the origin of interface states and the nitridation mechanism, theoretical studies^264–266) as well as structural analyses such as EPR²⁶⁷⁾ and high-resolution electron energy loss spectroscopy (EELS)^268,269) are required.

The physical reason for the low channel mobility of SiC MOSFETs has been debated. In Si MOSFETs, the main factors limiting the channel mobility are the fixed charge and surface roughness²⁷⁰⁾ because the interface state density in Si MOS structures formed by an adequate process is low enough not to limit the channel mobility. In SiC MOSFETs, Coulomb scattering has often been proposed as the main limiting factor. This model arises from the fact that the channel mobility of SiC(0001) MOSFETs usually exhibits a positive temperature coefficient (increasing at elevated temperatures). However, this is a misleading interpretation, and thermally activated transport or electron localization in inversion layers^232,271) is more likely to be responsible.

In estimations of field-effect mobility or effective mobility, it is assumed that all the electrons in the inversion layer are mobile, travelling in the conduction band from the source to the drain. In other words, the sheet electron density in the inversion layer, n_sheet, is approximately given by C_ox(V_G − V_T), where C_ox is the oxide capacitance, V_G the gate voltage, and V_T the threshold voltage. However, the interface state density in SiC MOS structures is so high that the integrated density of interface states can be of the same order as the induced sheet electron density (∼10¹² cm⁻²). Electrons trapped at the interface states must be almost immobile. If 90% of induced electrons are trapped, for example, only 10% of induced electrons can travel and contribute to the drain current. Even if the mobile electrons drift with a mobility of 100 cm² V⁻¹ s⁻¹, the overall channel mobility is calculated to be 10 cm² V⁻¹ s⁻¹. Under these circumstances, an increasing number of electrons are excited to the conduction band and become mobile with increasing temperature. As a result, the calculated channel mobility shows a positive temperature coefficient. Therefore, the "electron trapping effect" is a more correct term to explain the mobility behavior. The temperature dependence of field-effect mobility or effective mobility does not give clear insight into the scattering mechanisms involved in carrier transport.

As described above, the total density of induced electrons (n_total) is given by

$$\begin{equation} n_{\text{total}} = n_{\text{mobile}} + n_{\text{trap}}, \end{equation} \tag{ 7 }$$

where n_mobile and n_trap are the densities of mobile electrons and of electrons trapped at interface states, respectively. The real mobility of mobile electrons (μ_real) and the calculated mobility (μ_ch) are linked by the following equation:

$$\begin{equation} \mu_{\text{ch}} = \mu_{\text{real}}\frac{n_{\text{mobile}}}{n_{\text{mobile}} + n_{\text{trap}}}. \end{equation} \tag{ 8 }$$

The real mobility of mobile electrons in the conduction band can be obtained by MOS-Hall effect measurements.^272–274) Through MOS-Hall effect measurements, not only the real mobility but also the real mobile electron density (n_mobile) can be determined. Since the total density of induced electrons (n_total) is given by C_ox(V_G − V_T), the degree of electron trapping [(n_total − n_mobile)/n_total] can also be estimated.

When the interface state density is very high, one can see a rough correlation between the n-channel mobility and the interface state density near the conduction band edge. However, it is not very clear what the main mobility-limiting factor is once the interface state density has been reduced by nitridation or other processes. Figure 40 shows the correlation between the effective mobility (acceptor density of implanted p-body: 1 × 10¹⁷ cm⁻³) and interface state density integrated from E_c − 0.2 eV to E_c − 0.5 eV (N_it) for SiC(0001), $(11\bar{2}0)$, and $(1\bar{1}00)$ MOSFETs with nitrided gate oxides.²⁶¹⁾ When the D_it distribution determined by the high (1 MHz)–low method (only slow states) is employed to calculate N_it, the mobility shows poor correlation with N_it, as shown in Fig. 40(a). For example, a large difference in channel mobility between (0001) and nonpolar faces exists at similar N_it. However, a nearly one-to-one correlation (slope ≈ −1) is observed when N_it determined from the D_it distribution by the C–ψ_S method is employed, as shown in Fig. 40(b). The main difference between the high-low and C–ψ_S methods is the capability of fast state detection by the C–ψ_S method, as mentioned above. These results indicate the following:^12,261,275)

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• (i)   
  The n-channel mobility of SiC MOSFETs is still limited mainly by the very high interface state density, even after the recent process optimization.
• (ii)   
  The channel mobility is affected not only by relatively slow states, which are detected by the conventional high (1 MHz)–low method, but also by very fast interface states, which can be detected by the C–ψ_S method [and not by the high (1 MHz)–low method].
• (iii)   
  The smaller density of fast interface states for SiC MOS structures on nonpolar faces may be the main reason why higher mobilities can be attained on these faces than on (0001).

In general, SiC MOSFETs exhibit poor subthreshold slopes of 200–500 mV/decade, much larger than the ideal value of approximately 60 mV/decade, at room temperature. The poor subthreshold slope can be reproduced well using the distribution of the interface state density determined by the C–ψ_S method.^12,275)

However, the mechanism of channel conduction in SiC MOSFETs must be much more complicated. The surface roughness of SiC is much larger than that of Si because of the usage of off-axis {0001} wafers and immature surface preparation technology. The roughness scattering may become prominent when the interface state density is further reduced. This is especially important at a high gate bias, at which real MOS devices operate. The influence of the real (not effective) fixed charge on channel mobility has not yet been clarified. Another possible problem is the large fluctuation in surface potential, as revealed by conductance measurements.^230,261,276) Since the interface structure of SiC MOS structures can be highly inhomogeneous, the surface potential can fluctuate inside the MOS channel. Thus, the total conduction in the inversion layer may be limited by microscopic regions where the conductivity is greatly suppressed by the fluctuation.

It should be noted that a significant reduction of the interface state density and the improvement of n-channel mobility (120–150 cm² V⁻¹ s⁻¹) have been achieved on SiC(0001) by "sodium (Na)-contaminated" oxidation.²⁷⁷⁾ An accelerated oxidation rate has been reported for this Na-contaminated oxidation. Another strikingly effective technique to enhance the channel mobility is post-oxidation annealing in POCl₃.²⁷⁸⁾ By annealing in POCl₃ at 1000 °C for 10 min, a high channel mobility of 89 cm² V⁻¹ s⁻¹ is attained. The mobility can be further improved to 101 cm² V⁻¹ s⁻¹ by two-step annealing in POCl₃ at 1000 °C and in a forming gas at 700 °C.²⁷⁹⁾ The interface state density and the subthreshold slope for MOSFETs are also significantly improved by the POCl₃ annealing. A high channel mobility of 102 cm² V⁻¹ s⁻¹ has also been attained by boron diffusion into the thermal oxide.²⁸⁰⁾ Although these techniques cannot be employed directly in device manufacturing, it is worth investigating the mechanism of mobility improvement in greater detail in order to acquire important insights into mobility-limiting factors.