Graphene for nanoelectronics ^†

It has been a long time since the limitation of the miniaturization of Si LSIs was first pointed out. Although the time at which the limit will be reached has been gradually postponed, the limit may be reached around 2020 when the channel length of transistors becomes less than 10 nm. Can graphene, the topic of this review, solve this problem? We sometimes hear that the application of graphene to transistors is difficult and that graphene cannot be applied to logic transistors although it may be applied to high-frequency transistors. However, I do not agree with this opinion. I think that graphene has high potential as a future electronic material and that the application of graphene should not be abandoned before our techniques of controlling graphene have matured, although I do not intend to claim that graphene will completely replace Si in electronic devices in the future. It has been just around ten years since graphene was "rediscovered". As explained later, various problems must be solved before graphene can be applied to transistors. The technical advances toward achieving graphene transistors have been remarkable in the last five years. I believe that attractive graphene devices different from Si devices or with functions exceeding those of Si transistors will be realized in the future. In practice, it will take some more time to realize graphene transistors. The application of graphene to transparent electrodes, heat dissipation techniques, and optical devices will probably precede the realization of graphite transistors. The structure of logic transistors using graphene may be different from the currently available MOS structure. Considering these factors, I will briefly introduce the properties of graphene and clarify the current and future challenges by reviewing previous studies, particularly focusing on graphene transistors. Application of graphene to interconnects and the graphene formation techniques required for the realization of various applications are also reviewed. Finally, the prospects for applying graphene to electronic devices are discussed.

Graphene is an ideal two-dimensional one-atom-thick honeycomb lattice made of carbon atoms. The atomic structure of graphene is shown in Fig. 1. Graphene is a one-atom-thick layer of graphite as a layered material and its existence has been theoretically known for many years;^1–3) however, a one-atom-thick layer of graphene has been considered to be thermodynamically unstable.^4,5) Novoselov et al. experimentally identified graphene as a one-atom-thick layer for the first time (which is not necessarily contradictory to the theory because the layer was supported by a substrate).⁶⁾ They experimentally demonstrated its high mobility while examining its electrical properties. This study,⁶⁾ along with studies on the unique quantum Hall effect published the following year,^7,8) and the fact that graphene is easily prepared using adhesive tape, triggered a boom in graphene research in subsequent years.

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Graphene has excellent properties, such as a high mobility (approximately 100,000 cm² V⁻¹ s⁻¹ at room temperature), durability at a high current density (10⁹ A/cm²), good mechanical properties, and high thermal conductivity. The unique electronic state of graphene results in its excellent electrical properties. Figure 2 shows a three-dimensional plot of the energy band dispersion of graphene. The existence of K and K' points where the dispersion relationship is conical, with the energy being proportional to the wave number around the Fermi energy, is characteristic of graphene. This electronic state originates from the existence of two nonequivalent carbon atoms in a unit cell. Details of the electronic state of graphene are not explained here (refer to Ref. 9). This electronic state induces various characteristic phenomena, such as the suppression of backscattering^10–12) and Klein tunneling.^13,14) In this review, however, electrical properties from the viewpoint of its application to electronic devices, rather than the physical aspects of graphene, are mainly discussed.

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Graphene is a zero-gap semiconductor with a high electrical conductance. However, unlike general metals, the current can be modulated by gate biasing. Figure 3 shows a scanning electron microscopy (SEM) image of the first back-gate transistor with a graphene channel demonstrated by Novoselov et al.⁶⁾ The key to facilitating the observation of monolayer graphene was to place the graphene layer on a SiO₂ layer, which can be observed using an optical microscope.¹⁵⁾ The mobility of the graphene channel was approximately 10,000 cm² V⁻¹ s⁻¹. This value is not particularly high compared with that of compound semiconductors; however, it is surprising considering that this value was obtained for a device made from common graphite crystals using ordinary adhesive tape. Graphene is also very attractive as a semiconductor material because of its equal hole and electron mobilities.

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There have been a number of reports on the factors that affect the mobility of graphene. Thus far, scattering of carriers by charged impurities originated from the SiO₂ substrate,^16–18) scattering by the acoustic phonon of graphene itself,^19,20) and scattering by polar optical phonons of the substrate^19,21) have been pointed out as such factors. Hwang et al. theoretically predicted that a mobility of approximately 2,000,000 cm²/V can be achieved by suppressing the amount of charged impurities.¹⁷⁾ Chen et al. demonstrated that 1) the room-temperature mobility of graphene is suppressed to approximately 40,000 cm² V⁻¹ s⁻¹ by the effect of polar optical phonons of SiO₂ and 2) the room-temperature mobility is approximately 200,000 cm² V⁻¹ s⁻¹ when only acoustic phonons of graphene, not SiO₂, affect the mobility (at a carrier density of approximately 10¹² cm⁻² for both cases).¹⁹⁾ The results of this study indicate that the type of substrate significantly affects the mobility of graphene. Bolotin et al. fabricated a device in which a graphene channel was suspended to remove the effects of the substrate. Mobilities of 200,000 cm² V⁻¹ s⁻¹ at liquid helium temperature and 120,000 cm² V⁻¹ s⁻¹ at 120 K were obtained at a relatively low carrier density of 2 × 10¹¹ cm⁻².²²⁾ After that, Mayorov et al. demonstrated that 1) a mobility of 1,000,000 cm² V⁻¹ s⁻¹ can be obtained at low temperatures and 2) the mobility decreases to 20,000–30,000 cm² V⁻¹ s⁻¹ at about room temperature because of flexural phonons.²³⁾ Dean et al. fabricated graphene transistors on a hexagonal boron nitride (h-BN) flake, which have an atomically smooth surface and a higher optical phonon energy than graphene. A mobility of 140,000 cm² V⁻¹ s⁻¹ was obtained near the charge neutrality point at room temperature, and a mobility of approximately 25,000 cm² V⁻¹ s⁻¹ was obtained at a high carrier density.²⁴⁾ From their results, the improvement in mobility is considered to be caused mainly by decrease in charged impurities, which was also supported by Kelvin probe force microscopy results.²⁵⁾

As explained above, the effects of disturbance factors, such as charged impurities and the phonons in substrates, should be suppressed to bring out the inherent electrical properties of graphene. Although many papers have reported that the density of charged impurity residues caused by device-fabrication processes can be decreased by annealing,^22,26) optimization appropriate for each process may be necessary. The above-mentioned h-BN substrates can be used to suppress the effects of substrates; however, a technique for synthesizing high-quality large-area h-BN substrates has not yet been established. Developing such a technique as well as investigating other materials will be necessary in the future.

The high mobility of graphene is certainly attractive. However, the on–off current ratio of transistors with a graphene channel is only approximately 10 because there is no bandgap in graphene (Fig. 3). Increasing the on–off current ratio will be essential to apply graphene to transistors, and the formation of a bandgap in graphene has been attempted. The details are explained in the next section.

There have been many reports on the formation of a bandgap in graphene. The methods used include the formation of graphene nanoribbons (GNRs), the application of an electric field to bilayer graphene, and the modification of graphene. These methods are explained sequentially in this section.

4.1. Formation of GNRs

Japanese scientists had already reported the electronic states of GNRs before graphene attracted its current attention.^27,28) The results of tight-binding calculations showed that GNRs with armchair-shaped edges have a bandgap under certain conditions, whereas in GNRs with zigzag-shaped edges, the edge states appear at the Fermi level, in which the charge density strongly localized on the zigzag edge sites. Graphene with armchair edges behaves as a metal when the number of dimer lines is N_a = 3p − 1, where p is an integer (Fig. 4). The ratio of GNRs with metallic behavior is 1/3, which is equal to that for carbon nanotubes (CNTs). Son et al. demonstrated that GNRs have a bandgap regardless of the edge termination (armchair or zigzag) by performing a first-principles calculation [local density approximation (LDA)].²⁹⁾ The bandgap and its dependence on the ribbon width differ with the type of edge termination and N_a (the case of GNRs with armchair-shaped edges is shown in Fig. 5). Yang et al. demonstrated that the bandgap is estimated to be larger when the effects of the electron–electron interaction are taken into consideration using a first-principles many-electron Green's function approach within the GW approximation (Fig. 5).³⁰⁾

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GNRs have been experimentally fabricated by a top-down approach using electron beam lithography and oxygen plasma etching.^31–33) Han et al. fabricated GNRs with a width of down to 14 nm and demonstrated that the energy gap, E_g, is expressed as a function of the ribbon width as

$$\begin{equation} E_{\text{g}} = \frac{\alpha}{W - W^{*}}, \end{equation} \tag{ 1 }$$

where α = 2 eV and W^* = 16 nm (Fig. 6).³³⁾ W^* is the inactive edge width and is interpreted as the difference between the apparent ribbon width and the actual ribbon width or the decrease in the effective ribbon width as a result of edge defects. Research on the electron transport in GNRs fabricated by a top-down approach has since continued, and the above energy gap is now interpreted as a transport gap, which is generally larger than the theoretically calculated bandgap.^34,35) The transport gap has been interpreted using various models including Anderson localization, variable-range hopping, and the Coulomb blockade model. In all models, the existence of defects at the edges causes the transport gap. Thus far, GNRs with ideal edges have not been successfully fabricated by any top-down approach. Further improvement in lithography and etching techniques will be required.

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Other methods have also been used in attempts to form GNRs. For example, Li et al. formed GNRs by heating expandable graphite at 1,000 °C in a forming gas, dispersing the resulting graphite in a 1,2-dichloroethane (DCE) solution of poly(m-phenylenevinylene-co-2,5-dioctoxy-p-phenylenevinylene) (PmPV), and ultrasonicating the solution.³⁶⁾ GNRs with a width ≤10 nm were obtained. Transmission electron microscopy (TEM) revealed that these GNRs had ultrasmooth edges. Regarding the electrical properties, an on–off current ratio of 10⁵–10⁷ was obtained for the GNRs with a width <10 nm at room temperature, which was a significant advance considering that the maximum on–off current ratio of the GNRs fabricated by a top-down approach was only 10–100. Similarly, a mobility of 100–200 cm² V⁻¹ s⁻¹ was obtained for the GNRs. This combination of the on–off current ratio (10⁵–10⁷) and mobility (100–200 cm² V⁻¹ s⁻¹) is the best reported combination for GNRs, to the best of my knowledge. The bandgap was also in reasonable agreement with that obtained by first-principles calculation (without consideration of the many-body effect). With this method, relatively high-quality GNRs can be obtained; however, the control of the ribbon width is difficult.

Methods of fabricating GNRs from CNTs have also been proposed.^37,38) In one method, GNRs were fabricated by cutting the side walls of multiwalled CNTs in the lengthwise direction with the treatment of multiwalled CNTs with a strong oxidant.³⁸⁾ Here, the obtained GNRs were graphene oxide; they had poor electrical properties and required reduction treatment for use as graphene. After this method was proposed, another method of fabricating GNRs by mildly oxidizing multiwalled CNTs in a gas phase and dispersing the resulting multiwalled CNTs in a DCE solution of PmPV was reported.³⁹⁾ The obtained GNRs had smooth edges. A high mobility of 1,500 cm² V⁻¹ s⁻¹ was obtained for the GNRs with a width of 14 nm. The above methods of fabricating GNRs from CNTs have been successful only for relatively thick multiwalled CNTs and only relatively wide GNRs have been obtained.

As a true bottom-up approach, a method of fabricating GNRs with a uniform width from anthracene dimers as a precursor was reported in 2010.⁴⁰⁾ Figure 7 shows the fabrication method. First, anthracene dimers with both ends terminated with Br are deposited on Au substrate. When the substrate temperature is increased to 200 °C, debromination occurs and the sites from which Br atoms have been removed bond with each other. When the temperature is further increased to 400 °C, cyclodehydrogenation occurs to form GNRs. As shown in Fig. 7(b), the ribbon width is well controlled and a Raman vibration mode that depends on the ribbon width is observed. According to the representation in Fig. 4, the fabricated GNRs are those with armchair-shaped edges with N = 7, and the bandgap is approximately 3.7 eV (Fig. 5). Ruffieux et al. estimated the bandgap by scanning tunneling microscopy (STM) to be approximately 2.7 eV,⁴¹⁾ in reasonable agreement with the theoretical bandgap considering the mirror charge effect of the Au substrate. The electrical properties of GNRs were measured by STM and insulating behavior was obtained as expected.⁴²⁾

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The bandgap of 3.7 eV may be too large for the application of GNRs to transistors. More recently, the fabrication of GNRs with larger widths has been reported.⁴³⁾ It is expected that the bandgap will be freely controlled in the future.

4.2. Use of bilayer graphene

Another method of forming a bandgap in graphene is to apply an electric field perpendicularly to an AB-stacked bilayer graphene (Fig. 8). The formation of a bandgap in graphene by this method was first predicted by theoretical calculations.^44,45) The essence of this method is to place two types of carbon atom (A- and B-site carbons) in different environments, which is realized by applying an electric field perpendicularly to the bilayer graphene. Theoretically, the formation of a bandgap of 200–300 meV is considered to be possible by applying a displacement field of approximately 1 V/nm.⁴⁶⁾

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Bandgap formation was first observed in bilayer graphene formed on a SiC substrate without the application of an electric field.⁴⁷⁾ This is because the SiC-side layer in the bilayer graphene on the SiC substrate is electron-doped, resulting in an inequality in the charge density (potential) between the two layers. Afterward, Oostinga et al. experimentally demonstrated that a bandgap can be formed by applying an electric field between electrodes placed above and below a bilayer graphene channel.⁴⁸⁾ However, the bandgap estimated from the electrical properties was no more than 10 meV and the effects of defects on the energy level within the bandgap were pointed out. Zhang et al. optically estimated the bandgap by infrared microspectroscopy and obtained a bandgap of approximately 250 meV for a displacement field of approximately 3 V/nm.⁴⁹⁾ In this case, however, the energy gap obtained from the electrical properties was much smaller than 250 meV. A research group of IBM Corporation obtained an on–off current ratio of approximately 100 at room temperature by applying a displacement field of approximately 2.2 V/nm. Researchers estimated a bandgap of approximately 130 meV from the temperature dependence of the on–off current ratio.⁵⁰⁾ This is the highest-level bandgap obtained from electrical properties.

The application of an electric field, as explained above, not only requires complicated device structures but also poses a risk of dielectric breakdown. As an alternative method, the formation of a bandgap by the molecular doping of bilayer graphene has been attempted.^51–54) Park et al. transferred a bilayer graphene onto a self-assembled monolayer (SAM) serving as an n-dopant, on which tetrafluoro-tetrafluorotetracyano-quinodimethane (F4-TCNQ) was deposited as a p-dopant.⁵⁴⁾ The on–off current ratio was approximately 25 at room temperature, which was much lower than expected and may have been affected by the energy levels due to defects. This method is possibly promising compared with the method of actually applying an electric field, because a relatively large effective electric field can be applied to the bilayer graphene if appropriate molecular materials for doping are selected. Theoretically, the formation of a bandgap exceeding 300 meV is expected.⁵⁵⁾

4.3. Formation of bandgap in graphene by other methods

4.4. Issues to be resolved in bandgap formation

A bandgap can be formed in graphene by the methods discussed above. However, graphene with both a bandgap and high mobility has not been realized. The reason behind this is the trade-off relationship between bandgap formation and high mobility (Fig. 9).^72–74) In addition, insufficient control of the edges of GNRs and the interface of bilayer graphene is considered to be a major cause of low mobility. For example, a GNR with an ideal edge is considered to have mobility (experimentally, approximately 100,000 cm² V⁻¹ s^{−1 75)}) and device performance comparable to those achieved by CNTs. In fact, performances equivalent to those of CNTs or superior to those of Si were predicted in the simulation of transistors using ideal GNRs.^76–78)

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5.1. Techniques of depositing gate-insulator and passivation films

5.2. Contact resistance

5.3. Doping

Exfoliating a monolayer of graphene from graphite is an ideal method of obtaining graphene to study its properties. However, for the application of graphene to industrial use, the development of techniques to form uniform large-area graphene films is essential. Methods of forming graphene that have recently attracted attention as research targets include the annealing of a SiC substrate surface^117–121) and CVD. In 1975, graphene was first formed on a SiC substrate in high vacuum by heating the SiC.¹²¹⁾ Since then, several prominent papers, such as those on the first evaluation of the electrical properties of graphene,¹¹⁷⁾ determination of the number of layers by low-energy electron microscopy (LEEM),¹¹⁹⁾ improving the surface roughness and the uniformity of the number of graphene layers formed by annealing in an Ar atmosphere,¹¹⁸⁾ and the formation of quasi-free-standing graphene,¹²⁰⁾ have been published. Because of space limitations, details of these methods are not discussed here. The formation of graphene by CVD is reviewed below.

In CVD, graphene films are generally synthesized on a substrate with a thin catalyst film, such as Cu, Ni, or Co film, or on a metal catalyst foil by heating the substrate or the foil and introducing a hydrocarbon gas.^122–126) CVD is an effective method for application to electronic devices because it can be easily used with large-area substrates and is a versatile semiconductor process.

Attempts to form graphene by CVD started with the formation of graphene on polycrystalline Ni films/foils.^122,125,126) The formation of graphene on Ni films is considered to be due to the precipitation of solid-solution carbon because of a high solubility of carbon in Ni. When catalysts with a high solubility of carbon, such as Ni and Co, are used, multilayer graphene is generally formed. Controlling the number of layers is difficult owing to the variation in the amount of carbon deposited among different grains of polycrystalline films. Our group attempted to form graphene on Fe films and obtained similar results.^123,127) To obtain a graphene monolayer, a Cu catalyst is superior in terms of controlling the number of layers, as reported in 2009, and enables the synthesis of a graphene monolayer over the entire substrate.¹²⁴⁾ The formation of graphene on Cu is understood to be a result of a catalytic reaction of hydrocarbons because of the low solubility of carbon in Cu.¹²⁸⁾ Recently, graphene having grains of millimeter-order size has been formed on Cu foils (Fig. 10).^129–131) Methane gas was used as the carbon source. The methane partial pressure as well as the amount of hydrogen were found to significantly affect the formation of graphene.^131,132) Similar graphene monolayers can be synthesized on a Cu film on a Si substrate, in addition to on a Cu foil alone. Our group has recently succeeded in synthesizing graphene on a 300-mm-diameter Si wafer (Fig. 11).¹³³⁾

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The catalysts used in the above experiments were polycrystalline and the formed graphene was also polycrystalline over the entire substrate, although the grain size differed. Recently, epitaxial monolayer graphene of centimeter-order size has been formed using epitaxial catalysts, such as Co and Cu.^134–136) The evaluation of whether the obtained graphene is truly single crystals or not is difficult; however, these studies provide a direction for developing methods of forming single-crystal graphene.

As explained above, the techniques used to form graphene over an entire substrate while controlling the grain size are making rapid progress these days. Mobility of up to approximately 25,000 cm² V⁻¹ s⁻¹ has been obtained at room temperature,¹³⁷⁾ which is equivalent to that of an exfoliated monolayer of graphene. From the viewpoint of applying graphene to transistors, the formation of GNRs by CVD using a bottom-up approach is desirable. Our group has recently found that GNRs can be grown selectively at the narrow twin crystal regions formed when Cu films are annealed.¹³⁸⁾ A recent report showed that GNR was formed by MBE, instead of CVD, using a vicinal SiC substrate as a template.¹³⁹⁾ I hope that further technical developments will be made in this field in the future.

Because graphene is formed on metal catalyst foils by CVD, as discussed above, a transfer process is generally required to fabricate graphene transistors. Several research groups including our group have reported the transfer-free fabrication of transistors.^123,140) The challenge is to form graphene directly on an insulating substrate. Although several attemps have been reported,^141,142) the quality of the formed graphene has generally been low. Future developments in this field are also expected.

The application of graphene to devices operating at high frequencies has been mainly reported by researchers of IBM Corporation.^143–148) Table I summarizes the history of their achievements reported. The cutoff frequency (f_T) was as low as 26 GHz in 2009¹⁴⁴⁾ but had increased approximately tenfold by 2012.¹⁴⁵⁾ As shown in Table I, f_T did not necessarily increase in inverse proportion to the gate length at the beginning; however, f_T was inversely proportional to the gate length in the 2012 report. This improvement is due to various factors, including the control of the quality and interface of graphene, and the reduction in contact resistance. According to their reports, the values of f_T and the gate length of the graphene formed by CVD were equivalent to those for the graphene synthesized on SiC. It is noteworthy that the properties of transistors with CVD graphene were improved when fabricated on diamond-like carbon (DLC) film,¹⁴⁶⁾ because of the high energy of its optical phonons compared with that of SiO₂. To the best of my knowledge, the highest f_T of 427 GHz was reported by a research group at University of California, Los Angeles (UCLA).¹⁴⁹⁾ Their method is distinctive in that arrays of gate stacks were fabricated separately and then transferred onto a substrate with graphene on top, on which the source and drain electrodes were formed by a self-aligned process. An f_T of 427 GHz was obtained for an exfoliated monolayer of graphene, and f_T for the graphene formed by CVD was 212 GHz, which is close to that reported by the research group of IBM.

Figure 12 shows the relationship between f_T and the gate length for various semiconductor materials including graphene. Values of f_T for compound semiconductors are still superior to that of graphene, although f_T for graphene is approaching the best value for compound semiconductors. Theoretically, f_T exceeding 1 THz has been predicted for graphene.¹⁵⁰⁾ To realize this value, decreases in the contact resistance and EOT are essential. Although higher values of f_T have gradually been obtained, the maximum oscillation frequency (f_max) reported by the research groups of IBM was only 40 GHz, which is one order of magnitude smaller than that of compound semiconductors. The reason behind this is the inability to decrease the drain conductance (g_ds) because of the poor saturation properties. A method of decreasing the apparent g_ds was proposed,¹⁵¹⁾ but it is still unsatisfactory. To improve the saturation properties, the formation of a bandgap is naturally the final goal.

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For the application of graphene to devices operated at high frequencies, the use of the ambipolar properties of graphene has been proposed. Our group proposed an inverter and a one-transistor binary digital phase modulator with both a top gate and a back gate.¹⁵²⁾ Wang et al. proposed frequency doublers.¹⁵³⁾ The application of graphene to these kinds of devices utilizing its unique properties is expected to expand in the future.

In this review, the application of graphene to transistors has mainly been discussed. In this section, I will briefly explain the application of graphene to interconnects. Along with the miniaturization of devices, LSI interconnects are facing two problems: decreased reliability and increased effective resistivity of Cu interconnects. According to the International Technology Roadmap for Semiconductors 2011, the resistivity of Cu interconnects is estimated to exceed 10 µΩ cm (1.7 µΩ cm for bulk Cu) by about 2020 when the linewidth is expected to have become smaller than 10 nm. Therefore, CNTs and graphene have been attracting attention as new interconnect materials.

It was reported that the reliability of graphene interconnects, as well as CNT interconnects, is superior to that of Cu interconnects. The breakdown current densities of both an exfoliated monolayer of graphene and CVD graphene are of the order of 10⁸–10⁹ A/cm².^154,155) Figure 13 shows the results of a reliability test conducted by our group.¹⁵⁶⁾ The current density durability of the CVD graphene is superior to that of Cu.

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However, graphene interconnects having lower resistance than that of Cu interconnects have not been reported and the development of such graphene interconnects is a current challenge. The resistivity of bulk graphite is about 40 µΩ cm, which is one order of magnitude higher than that of Cu (1.7 µΩ cm). Interconnects with a low resistivity cannot be obtained simply by patterning graphene.^157,158) One method of reducing resistivity is to use the ballistic conduction of GNRs, similarly to the case of CNTs. The resistivity of GNR interconnects was first estimated by simulation.^159,160) Although the simulation results vary depending on the assumptions, for linewidths smaller than 10 nm, the resistivity of graphene becomes lower than that of Cu owing to the increase in the effective resistivity of Cu.¹⁶⁰⁾ Note that this result is greatly affected by the state of edge termination.¹⁵⁹⁾ The complete specular reflection of electrons at the edges is ideal; however, it is very difficult to obtain ideal edges by a top-down approach.

Intercalation is another method of reducing the resistivity of graphene. Lowering the resistivity of graphene by intercalation was first reported many years ago.¹⁶¹⁾ Some materials have been reported to achieve resistivity lower than that of Cu by intercalation to graphite. Xu et al. demonstrated by simulation that AsF₅-doped multilayer GNRs can have lower resistivity than that of Cu.¹⁵⁹⁾ Murali experimentally demonstrated that an electrostatically doped exfoliated GNR monolayer can have a resistivity comparable to that of Cu. Our group obtained a resistivity of 4.1 µΩ cm, which is equivalent to that of Cu, by the intercalation of FeCl₃ in CVD graphene interconnects.¹⁶²⁾ This value was obtained for graphene interconnects with a width of several microns. It is necessary to examine the feasibility of obtaining resistivity lower than that of Cu for much narrower interconnects.

Recently, there has been a move to develop graphene switching devices based on new concepts because the formation of a bandgap in graphene is still difficult, as explained earlier. This new trend is explained in this section.

Yang et al. fabricated a device with a heterojunction between graphene and hydrogen-terminated Si (Fig. 14).¹⁶³⁾ Switching operation was realized by changing the Schottky barrier height through the adjustment of the gate voltage to control the Fermi level of graphene. They called this device a graphene "barristor" and obtained an on–off current ratio of approximately 10⁵. However, this device has some drawbacks, such as a relatively small on-current and the difficulty of obtaining saturation characteristics, as observed in general transistors, with increasing bias current.

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Britnell et al. fabricated tunneling transistors with two graphene layers sandwiching either BN or MoS₂.¹⁶⁴⁾ Here, the tunneling current could be modulated by changing the Fermi energy of the two graphene layers through the adjustment of the back-gate voltage. Vaziri et al. fabricated graphene-based hot electron transistors.¹⁶⁵⁾ The tunneling current was controlled by changing the potential applied to the graphene, although details are not given here for space limitation. An on–off current ratio exceeding 10⁴ was obtained for these devices, but there was a problem of a small on-current.

Banerjee et al. proposed a device called a bilayer pseudospin field-effect transistor (BiSFET) that was based on a completely new concept.^166,167) In this device, a thin insulating film is sandwiched between two graphene layers. When the electron concentration in one graphene layer and the hole concentration in another graphene layer are balanced at a high concentration, the Bose condensation of electron–hole pairs (excitons) is induced to markedly decrease the tunneling resistance, allowing current to flow. They reported that the power consumption per clock cycle of this device is much smaller than that of currently available metal–oxide–semiconductor field-effect transistors (MOSFETs). The device is very attractive as it is based on a new concept, although they recognized some issues to be addressed in their theory.

As explained above, new devices based on new concepts have been proposed. The key to the realization of future devices will be to utilize the unique characteristics of graphene and graphene heterojunctions with other two-dimensional materials.

In this review, research on graphene transistors has mainly been discussed. Graphene has excellent electrical properties, and a bandgap can be created by, for example, forming GNRs; however, these potential properties of graphene have not been fully brought out. This is mainly due to the insufficient control of interfaces and edges. To solve these problems, techniques for the heteroepitaxial growth of other two-dimensional materials, such as h-BN, may be necessary. Considering the recent rapid advances in technology, the control of interfaces and edges is expected to be possible in the near future.

The use of conventional miniaturization technologies to improve the performance of semiconductor devices is predicted to reach its limit in the near future. Although the use of graphene will not necessarily advance the miniaturization of semiconductor devices, graphene is expected to be used as a material for "More Moore" high-end logic channels with a higher speed and lower power consumption at the same dimensions. Its application to tunneling transistors is also expected. From the viewpoint of the "More than Moore" approach, the combination of high-frequency or optical devices using graphene with Si devices is expected, which would be less difficult and realized before "More Moore" devices. Now that the realization of graphene with a low resistivity is being reached, the application of graphene to LSI interconnects and flexible/transparent interconnects is also promising.

In the previous section, I introduced a layered device consisting of graphene and other two-dimensional materials that operates on the basis of a new concept. For the realization of new properties of graphene and their application, the combination of graphene with other two-dimensional materials and topological insulators will play a key role; this is an area of research of interest to the author.

Most of our studies introduced in this review were supported by the Cabinet Office, Government of Japan and the Japan Society for the Promotion of Science (JSPS) through the Funding Program for World-Leading Innovative R&D on Science and Technology (FIRST Program). I would like to thank Dr. Naoki Yokoyama, Leader of Collaborative Research Team Green Nanoelectronics Center, the National Institute of Advanced Industrial Science and Technology, for his advice and support, as well as colleagues in my research team who supported my research.