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Implementation of silicon-on-glass MEMS devices with embedded through-wafer silicon vias using the glass reflow process for wafer-level packaging and 3D chip integration

Chiung-Wen Lin1, Chia-Pao Hsu2, Hsueh-An Yang3, Wei Chung Wang1,3 and Weileun Fang1,2

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This study presents a novel system architecture to implement silicon-on-glass (SOG) MEMS devices on Si–glass compound substrate with embedded silicon vias. Thus, the 3D integration of MEMS devices can be accomplished by means of through-wafer silicon vias. The silicon vias connecting to the pads of devices are embedded inside the Pyrex glass. Parasitic capacitance for both vias and microstructures is decreased and mismatch of coefficient of thermal expansion (CTE) is reduced. In applications, the glass reflow process together with the SOG micromachining processes were employed to implement the presented concept. Successful driving of the resonator through the silicon vias is demonstrated. The wafer-level hermetic packaging can be further achieved by anodic bonding of a Pyrex7740 wafer. Hermeticity of the packaged device performed by helium leak test satisfied MIL-STD-883E. The packaged SOG device is SMT (surface mount technology) compatible and ready for 3D microsystem integration.


PACS

85.85.+j Micro- and nano-electromechanical systems (MEMS/NEMS) and devices

85.30.-z Semiconductor devices

85.40.-e Microelectronics: LSI, VLSI, ULSI; integrated circuit fabrication technology

Subjects

Electronics and devices

Semiconductors

Nanoscale science and low-D systems

Dates

Issue 2 (February 2008)

Received 23 October 2007, in final form 30 November 2007

Published 4 January 2008



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