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Through silicon vias filled with planarized carbon nanotube bundles

Teng Wang1,2, Kjell Jeppson1, Niklas Olofsson3, Eleanor E B Campbell4,5 and Johan Liu1,6

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The feasibility of using carbon nanotube (CNT) bundles as the fillers of through silicon vias (TSVs) has been demonstrated. CNT bundles are synthesized directly inside TSVs by thermal chemical vapor deposition (TCVD). The growth of CNTs in vias is found to be highly dependent on the geometric dimensions and arrangement patterns of the vias at atmospheric pressure. The CNT–Si structure is planarized by a combined lapping and polishing process to achieve both a high removal rate and a fine surface finish. Electrical tests of the CNT TSVs have been performed and their electrical resistance was found to be in the few hundred ohms range. The reasons for the high electrical resistance have been discussed and possible methods to decrease the electrical resistance have been proposed.


PACS

81.07.De Nanotubes

81.15.Gh Chemical vapor deposition (including plasma-enhanced CVD, MOCVD, etc.)

73.63.Fg Nanotubes

81.16.-c Methods of nanofabrication and processing

85.40.Ls Metallization, contacts, interconnects; device isolation

81.65.Ps Polishing, grinding, surface finishing

Subjects

Electronics and devices

Surfaces, interfaces and thin films

Nanoscale science and low-D systems

Dates

Issue 48 (2 December 2009)

Received 30 September 2009, in final form 1 October 2009

Published 4 November 2009



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