Hong-Quan Zhao et al 2009 Nanotechnology 20 245203 doi:10.1088/0957-4484/20/24/245203
A binary-decision-diagram-based two-bit arithmetic logic unit on a GaAs-based regular nanowire network with hexagonal topology
Hong-Quan Zhao1, Seiya Kasai1,2,3, Yuta Shiratori1,2 and Tamotsu Hashizume1,2
Show affiliationsA two-bit arithmetic logic unit (ALU) was successfully fabricated on a GaAs-based regular nanowire network with hexagonal topology. This fundamental building block of central processing units can be implemented on a regular nanowire network structure with simple circuit architecture based on graphical representation of logic functions using a binary decision diagram and topology control of the graph. The four-instruction ALU was designed by integrating subgraphs representing each instruction, and the circuitry was implemented by transferring the logical graph structure to a GaAs-based nanowire network formed by electron beam lithography and wet chemical etching. A path switching function was implemented in nodes by Schottky wrap gate control of nanowires. The fabricated circuit integrating 32 node devices exhibits the correct output waveforms at room temperature allowing for threshold voltage variation.
- PACS
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84.30.Sk Pulse and digital circuits
61.46.-w Structure of nanoscale materials
81.07.-b Nanoscale materials and structures: fabrication and characterization
85.40.Bh Computer-aided design of microcircuits; layout and modeling
- Subjects
- Dates
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Issue 24 (17 June 2009)
Received 9 January 2009, in final form 27 April 2009
Published 26 May 2009
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A binary-decision-diagram-based two-bit arithmetic logic unit on a GaAs-based regular nanowire network with hexagonal topology
Hong-Quan Zhao et al 2009 Nanotechnology 20 245203
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Determinable solutions for one-dimensional quantum potentials: scattering, quasi-bound and bound-state problems
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Getting a grip on spider attachment: an AFM approach to microstructure adhesion in arthropods
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