Opinions differ widely as to the type of architecture most suitable for achieving the tremendous performance gains expected with computers built by nanotechnology. In this context little research effort has gone into asynchronous cellular arrays, an architecture that is promising for nanocomputers due to (1) its regular structure of locally interconnected cells, and (2) its asynchronous mode of timing. The first facilitates bottom-up manufacturing techniques like directed self-assembly. The second allows the cells' operations to be timed randomly and independently of each other, mitigating the problems accompanying a central clock, like high power consumption and heat dissipation. The advantages of asynchronous timing notwithstanding, it makes computation less straightforward. Attempts to compute on asynchronous cellular arrays have therefore focused on simulating synchronous operation on them, at the price of more complex cells. Here we advance a more effective approach based on the configuration on an asynchronous cellular array of delay-insensitive circuits, a type of asynchronous circuit that is robust to arbitrary delays in signals. Our results may be a step towards future nanocomputers with a huge number of autonomously operating cells organized in homogeneous arrays that can be programmed by configuring them as delay-insensitive circuits.