P L Cheng et al 2007 Semicond. Sci. Technol. 22 S140 doi:10.1088/0268-1242/22/1/S33
P L Cheng1,3, C I Liao1, H R Wu1, Y C Chen1, C C Chien1, C L Yang1, S F Tzou1, J Tang2, R Kodali2, L Washington2, Y Cho2, V C Chang2, T Fu2 and W S Hsu3
Show affiliationsSeveral dry and wet surface treatment methods are explored for a selective SiGe epitaxial film used to fabricate embedded SiGe pMOSFETs. Pre-clean conditions for the device wafers used in this study were limited by a realistic CMOS process window with tight thermal and chemical budgets due to dopant diffusion and hardmask erosion concerns. The effectiveness of these pre-clean methods is evaluated by SiGe epitaxial film quality and SIMS profiles of key residual contaminants such as C and O at the SiGe–Si substrate interface. As an effective low-temperature dry surface treatment, chemical bake in HCl/H2 at temperature below 800 °C is found to reduce interface C and O peak concentrations by an order of magnitude. Wet clean in multiple cycles of DIW-O3 (ozonated water), SC1 and diluted HF (DHF) is also presented to prepare epitaxial growth surfaces with accumulated damage and chemical residues from previous process steps. SiGe epitaxial film morphology is also observed to improve by increasing DHF clean time. For further improvement of film quality on the most difficult surfaces, Si seed layer was employed to initiate SiGe film nucleation and yield smooth film growth.
68.55.A- Nucleation and growth
68.37.Hk Scanning electron microscopy (SEM) (including EBIC)
79.20.Rf Atomic, molecular, and ion beam impact and interactions with surfaces
Issue 1 (January 2007)
Received 4 July 2006
Published 5 December 2006
P L Cheng et al 2007 Semicond. Sci. Technol. 22 S140
Niclas Wyllard JHEP11(2009)002
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