In the present paper, we propose a new scaling theory to model short channel effects (SCEs) in nanoscale double gate (DG) SOI MOSFETs, addressing two important technological issues—source/drain extension (SDE) region engineering and high-κ gate dielectrics. The impact of SDE region engineering through the optimization of lateral source/drain doping gradient and spacer width on SCEs is extensively analysed in DG devices with high-κ gate dielectrics, using the analytical model and 2D device simulations. Novel technology dependent scaling parameters, i.e., spacer-to-gradient ratio (ρ) and effective channel length (L_eff), are proposed for source/drain-engineered DG MOSFETs, and their significance in minimizing SCEs in high-κ gate dielectrics is discussed in detail. Results show that the optimal spacer-to-gradient ratio should be increased with the permittivity of high-κ dielectrics in order to maintain SCEs to an acceptable level. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients, high-κ gate dielectrics and effective channel lengths. The present work provides valuable design insights in the performance of nanoscale source/drain-engineered DG SOI devices with high-κ gate dielectrics and serves as an accurate tool to optimize important device parameters aiding technology development.