Xia An et al 2004 Semicond. Sci. Technol. 19 347 doi:10.1088/0268-1242/19/3/009
Xia An, Ru Huang, Baoying Zhao, Xing Zhang and Yangyuan Wang
Show affiliationsWith the decrease in gate length scaling, the leakage current has become more and more significant. Ultra-thin body (UTB) silicon-on-insulator (SOI) metal–oxide semiconductor field effect transistors (MOSFETs) are promising candidates for sub-50 nm MOSFETs. In this paper, we investigate the trade-off of a 50 nm undoped-body UTB SOI device with different gate workfunctions (Φm) and silicon body thickness (TSi). For the first time, the optimal regions of gate workfunctions and the silicon body thickness for low operating power (LOP) and high-performance logic (HP) applications are given respectively, which shed light on UTB MOSFET design. The simulation results show that in comparison with HP devices, LOP devices can exhibit a relatively wider design window. It is identified that UTB SOI devices can offer a better device solution for LOP applications.
73.30.+y Surface double layers, Schottky barriers, and work functions
73.40.Qv Metal-insulator-semiconductor structures (including semiconductor-to-insulator)
Issue 3 (March 2004)
Received 18 September 2003
Published 25 November 2003
Xia An et al 2004 Semicond. Sci. Technol. 19 347
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